tegra234-clock.h - OpenGrok cross reference for /linux-6.14.4/include/dt-bindings/clock/tegra234-clock.h

Lines Matching +full:gate +full:- +full:clock
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
9  * @defgroup bpmp_clock_ids Clock ID's
14 /** @brief output of gate CLK_ENB_ADSP */
16 /** @brief output of gate CLK_ENB_ADSPNEON */
20 /** @brief output of gate CLK_ENB_APB2APE */
30 /** @brief output of gate CLK_ENB_CAN1_HOST */
34 /** @brief output of gate CLK_ENB_CAN2_HOST */
46 /** @brief output of gate CLK_ENB_DPAUX */
58 /** @brief clock recovered from EAVB input */
73  * @brief controls the EMC clock frequency.
74  * @details Doing a clk_set_rate on this clock will select the
75  * appropriate clock source, program the source rate and execute a
76  * specific sequence to switch to the new clock source for both memory
85 /** @brief output of gate CLK_ENB_EQOS_RX */
97 /** @brief output of gate CLK_ENB_FUSE */
126 /** @brief clock recovered from I2S1 input */
130 /** @brief clock recovered from I2S2 input */
134 /** @brief clock recovered from I2S3 input */
138 /** @brief clock recovered from I2S4 input */
142 /** @brief clock recovered from I2S5 input */
146 /** @brief clock recovered from I2S6 input */
150 /** @brief Monitored branch of EQOS_RX clock */
154 /** @brief output of gate CLK_ENB_MIPI_CAL */
158 /** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */
160 /** @brief output of gate CLK_ENB_MPHY_L0_RX_LS_BIT */
162 /** @brief output of gate CLK_ENB_MPHY_L0_RX_SYMB */
164 /** @brief output of gate CLK_ENB_MPHY_L0_TX_LS_3XBIT */
166 /** @brief output of gate CLK_ENB_MPHY_L0_TX_SYMB */
168 /** @brief output of gate CLK_ENB_MPHY_L1_RX_ANA */
256 /** @brief output of gate CLK_ENB_SOR_SAFE */
314 /** @brief output of gate CLK_ENB_PEX1_CORE_6 */
322 /** @brief output of gate CLK_ENB_USB2_TRK */
334 /** @brief output of gate CLK_ENB_PEX2_CORE_7 */
336 /** @brief output of gate CLK_ENB_PEX2_CORE_8 */
338 /** @brief output of gate CLK_ENB_PEX2_CORE_9 */
352 /** @brief DP macro feedback clock (same as LINKA_SYM CLKOUT) */
362 /** @brief output of gate CLK_ENB_PEX2_CORE_10 */
382 /** @brief NAFLL clock source for BPMP */
384 /** @brief NAFLL clock source for SCE */
386 /** @brief NAFLL clock source for NVDEC */
388 /** @brief NAFLL clock source for NVJPG */
390 /** @brief NAFLL clock source for TSEC */
392 /** @brief NAFLL clock source for VI */
394 /** @brief NAFLL clock source for SE */
396 /** @brief NAFLL clock source for NVENC */
398 /** @brief NAFLL clock source for ISP */
400 /** @brief NAFLL clock source for VIC */
402 /** @brief NAFLL clock source for AXICBB */
404 /** @brief NAFLL clock source for NVJPG1 */
406 /** @brief NAFLL clock source for PVA core */
408 /** @brief NAFLL clock source for PVA VPS */
412 /** @brief NAFLL clock source for RCE */
418 /** @brief AXI_CBB branch sharing gate control with SDMMC4 */
422 /** @brief output of gate CLK_ENB_PEX0_CORE_0 */
424 /** @brief output of gate CLK_ENB_PEX0_CORE_1 */
426 /** @brief output of gate CLK_ENB_PEX0_CORE_2 */
428 /** @brief output of gate CLK_ENB_PEX0_CORE_3 */
430 /** @brief output of gate CLK_ENB_PEX0_CORE_4 */
432 /** @brief output of gate CLK_ENB_PEX1_CORE_5 */
434 /** @brief Monitored branch of PEX0_C0_CORE clock */
436 /** @brief Monitored branch of PEX0_C1_CORE clock */
438 /** @brief Monitored branch of PEX0_C2_CORE clock */
440 /** @brief Monitored branch of PEX0_C3_CORE clock */
442 /** @brief Monitored branch of PEX0_C4_CORE clock */
444 /** @brief Monitored branch of PEX1_C5_CORE clock */
446 /** @brief Monitored branch of PEX1_C6_CORE clock */
462 /** @brief Monitored branch of PEX2_C7_CORE clock */
464 /** @brief Monitored branch of PEX2_C8_CORE clock */
466 /** @brief Monitored branch of PEX2_C9_CORE clock */
468 /** @brief Monitored branch of PEX2_C10_CORE clock */
470 /** @brief RX clock recovered from MGBE0 lane input */
472 /** @brief RX clock recovered from MGBE1 lane input */
474 /** @brief RX clock recovered from MGBE2 lane input */
476 /** @brief RX clock recovered from MGBE3 lane input */
518 /** @brief NAFLL clock source for CPU cluster 0 */
521 /** @brief NAFLL clock source for CPU cluster 1 */
524 /** @brief NAFLL clock source for CPU cluster 2 */
537 /** @brief 32K input clock provided by PMIC */
539 /** @brief Fixed 48MHz clock divided down from utmipll */
541 /** @brief Fixed 480MHz clock divided down from utmipll */
559 /** @brief GPU system clock */
567 /** @brief output of gate CLK_ENB_BPMP_CPU */
585 /** @brief Dummy clock to ensure minimum SoC voltage for fuse burning */
601 /** @brief CLK_ENB_PLLREFE_OUT gate output */
611 /** @brief NAFLL clock source for OFA */
615 /** @brief NAFLL clock source for SEU1 */
627 /** @brief NAFLL clock source for DCE */
629 /** @brief Monitored branch of MPHY_L0_RX_ANA clock */
631 /** @brief Monitored branch of MPHY_L1_RX_ANA clock */
633 /** @brief ungated version of TX symbol clock after fixed 1/2 divider */
637 /** @brief output of gate CLK_ENB_MPHY_L0_TX_2X_SYMB */
645 /** @brief Monitored branch of MPHY_L0_TX_SYMB clock */
655 /** @brief Monitored branch of MPHY_L0_RX_SYMB clock */
657 /** @brief Monitored branch of MBGE0 RX input clock */
659 /** @brief Monitored branch of MBGE1 RX input clock */
661 /** @brief Monitored branch of MBGE2 RX input clock */
663 /** @brief Monitored branch of MBGE3 RX input clock */
681 /** @brief RX PCS clock recovered from MGBE0 lane input */
683 /** @brief RX PCS clock recovered from MGBE1 lane input */
685 /** @brief RX PCS clock recovered from MGBE2 lane input */
687 /** @brief RX PCS clock recovered from MGBE3 lane input */
697 /** @brief GBE_UPHY_MGBE0_MAC_CLK gate output */
699 /** @brief GBE_UPHY_MGBE0_MACSEC_CLK gate output */
701 /** @brief GBE_UPHY_MGBE0_EEE_PCS_CLK gate output */
703 /** @brief GBE_UPHY_MGBE0_APP_CLK gate output */
715 /** @brief GBE_UPHY_MGBE1_MAC_CLK gate output */
717 /** @brief GBE_UPHY_MGBE1_MACSEC_CLK gate output */
719 /** @brief GBE_UPHY_MGBE1_EEE_PCS_CLK gate output */
721 /** @brief GBE_UPHY_MGBE1_APP_CLK gate output */
733 /** @brief GBE_UPHY_MGBE2_MAC_CLK gate output */
735 /** @brief GBE_UPHY_MGBE2_MACSEC_CLK gate output */
737 /** @brief GBE_UPHY_MGBE2_EEE_PCS_CLK gate output */
739 /** @brief GBE_UPHY_MGBE2_APP_CLK gate output */
751 /** @brief GBE_UPHY_MGBE3_MAC_CLK gate output */
753 /** @brief GBE_UPHY_MGBE3_MACSEC_CLK gate output */
755 /** @brief GBE_UPHY_MGBE3_EEE_PCS_CLK gate output */
757 /** @brief GBE_UPHY_MGBE3_APP_CLK gate output */
769 /** @brief output of gate CLK_ENB_EQOS_MACSEC_RX */
771 /** @brief output of gate CLK_ENB_EQOS_MACSEC_TX */
779 /** @brief clock recovered from I2S7 input */
787 /** @brief clock recovered from I2S8 input */
795 /** @brief NAFLL clock source for GPU GPC0 */
797 /** @brief NAFLL clock source for GPU GPC1 */
799 /** @brief NAFLL clock source for GPU SYSCLK */
801 /** @brief NAFLL clock source for CPU cluster 0 DSUCLK */
804 /** @brief NAFLL clock source for CPU cluster 1 DSUCLK */
807 /** @brief NAFLL clock source for CPU cluster 2 DSUCLK */
810 /** @brief output of gate CLK_ENB_SCE_CPU */
812 /** @brief output of gate CLK_ENB_RCE_CPU */
814 /** @brief output of gate CLK_ENB_DCE_CPU */
842 /** @brief VPLL0 reference clock */
874 /** @brief Link clock input from DP macro brick PLL */
876 /** @brief SOR AFIFO clock outut */