Lines Matching +full:gate +full:- +full:clock

1 /* SPDX-License-Identifier: GPL-2.0 */
8  * @defgroup clock_ids Clock Identifiers
235  *   @defgroup nafll_clks NAFLL clock sources
350 /** @brief output of gate CLK_ENB_FUSE */
354  * @details output of gate CLK_ENB_GPU. This output connects to the GPU
355  * pwrclk. @warning: This is almost certainly not the clock you think
356  * it is. If you're looking for the clock of the graphics engine, see
360 /** @brief output of gate CLK_ENB_PCIE */
364 /** @brief output of gate CLK_ENB_PCIE2_IOBIST */
366 /** @brief output of gate CLK_ENB_PCIERX0*/
368 /** @brief output of gate CLK_ENB_PCIERX1*/
370 /** @brief output of gate CLK_ENB_PCIERX2*/
372 /** @brief output of gate CLK_ENB_PCIERX3*/
374 /** @brief output of gate CLK_ENB_PCIERX4*/
376 /** @brief output branch of PLL_C for ISP, controlled by gate CLK_ENB_PLLC_OUT_ISP */
378 /** @brief output branch of PLL_C for VI, controlled by gate CLK_ENB_PLLC_OUT_VE */
380 /** @brief output branch of PLL_C for AON domain, controlled by gate CLK_ENB_PLLC_OUT_AON */
382 /** @brief output of gate CLK_ENB_SOR_SAFE */
390 /** @brief output of gate CLK_ENB_SPDIF_DOUBLER */
417  * @brief controls the EMC clock frequency.
418  * @details Doing a clk_set_rate on this clock will select the
419  * appropriate clock source, program the source rate and execute a
420  * specific sequence to switch to the new clock source for both memory
437 /** output of gate CLK_ENB_DTV */
441 /** @brief output of gate CLK_ENB_DP2 */
463 /** @brief output of gate CLK_ENB_CEC */
465 /** @brief output of gate CLK_ENB_DPAUX1 */
467 /** @brief output of gate CLK_ENB_DPAUX */
471 /** @brief output of gate CLK_ENB_HDA2HDMICODEC */
475 /** @brief output of gate CLK_ENB_SATA_OOB */
477 /** @brief output of gate CLK_ENB_SATA_IOBIST */
483 /** @brief output of gate CLK_ENB_APB2APE */
487 /** @brief output of gate CLK_ENB_IQC1 */
489 /** @brief output of gate CLK_ENB_IQC2 */
493 /** @brief output of gate CLK_ENB_PLLREFE_PLL_REF */
495 /** @brief output of gate CLK_ENB_PLLC4_OUT */
505 /** @brief output of gate CLK_ENB_DSI */
507 /** @brief output of gate CLK_ENB_MIPI_CAL */
511 /** @brief output of gate CLK_ENB_DSIB */
539 /** @brief output of gate CLK_ENB_HSIC_TRK */
541 /** @brief output of gate CLK_ENB_USB2_TRK */
547 /** @brief output of gate CLK_ENB_ADSP */
549 /** @brief output of gate CLK_ENB_ADSPNEON */
553 /** @brief output of gate CLK_ENB_MPHY_L0_RX_LS_BIT */
557 /** @brief output of gate CLK_ENB_MPHY_L0_TX_LS_3XBIT */
559 /** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */
561 /** @brief output of gate CLK_ENB_MPHY_L1_RX_ANA */
585 /** @brief output of gate CLK_ENB_NVDISPLAY_DSC */
595 /** @brief output of gate CLK_ENB_EQOS */
597 /** @brief output of gate CLK_ENB_EQOS_RX */
647 /** @brief output of gate CLK_ENB_CAN1_HOST */
651 /** @brief output of gate CLK_ENB_CAN2_HOST */
677 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSC. This clock object is read…
685 /** @brief output of gate CLK_ENB_DSIC */
689 /** @brief output of gate CLK_ENB_DSID */
739 /** @brief output of gate CLK_ENB_PLLREFE_OUT */
742   *      * VCO/pdiv defined by this clock object
755 /** fixed 48MHz clock divided down from TEGRA186_CLK_PLL_U */
757 /** fixed 480MHz clock divided down from TEGRA186_CLK_PLL_U */
761 /** fixed /3 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/3 */
763 /** fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/5 */
779 /** A fake clock which must be enabled during KFUSE read operations to ensure adequate VDD_CORE vol…
783  * @details This clock only has enable and disable methods. When the
791 /** fixed 60MHz clock divided down from, TEGRA186_CLK_PLL_U */
797 /** @brief fixed /5 divider.  Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used a…
818  * @brief GPC2CLK-div-2
820  * TEGRA186_CLK_GPC2CLK/2. The frequency of this clock is the
841  * @details Note that this clock only controls the VCO output, before
842  * the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more
850 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDP_BASE for use as the DP link clock */
870 /** @brief NAFLL clock source for AXI_CBB */
872 /** @brief NAFLL clock source for BPMP */
874 /** @brief NAFLL clock source for ISP */
876 /** @brief NAFLL clock source for NVDEC */
878 /** @brief NAFLL clock source for NVENC */
880 /** @brief NAFLL clock source for NVJPG */
882 /** @brief NAFLL clock source for SCE */
884 /** @brief NAFLL clock source for SE */
886 /** @brief NAFLL clock source for TSEC */
888 /** @brief NAFLL clock source for TSECB */
890 /** @brief NAFLL clock source for VI */
892 /** @brief NAFLL clock source for VIC */
894 /** @brief NAFLL clock source for DISP */
896 /** @brief NAFLL clock source for GPU */
898 /** @brief NAFLL clock source for M-CPU cluster */
900 /** @brief NAFLL clock source for B-CPU cluster */
910 /** @brief clock recovered from EAVB input */
912 /** @brief clock recovered from DTV input */
918 /** @brief clock recovered from I2S1 input */
920 /** @brief clock recovered from I2S2 input */
922 /** @brief clock recovered from I2S3 input */
924 /** @brief clock recovered from I2S4 input */
926 /** @brief clock recovered from I2S5 input */
928 /** @brief clock recovered from I2S6 input */
930 /** @brief clock recovered from SPDIFIN input */
935  * @details maximum clock identifier value plus one.