21 #define SIO_F71808FG_LD_WDT	0x07	/* Watchdog timer logical device */
22 #define SIO_UNLOCK_KEY		0x87	/* Key to enable Super-I/O */
23 #define SIO_LOCK_KEY		0xAA	/* Key to disable Super-I/O */
25 #define SIO_REG_LDSEL		0x07	/* Logical device select */
26 #define SIO_REG_DEVID		0x20	/* Device ID (2 bytes) */
27 #define SIO_REG_DEVREV		0x22	/* Device revision */
28 #define SIO_REG_MANID		0x23	/* Fintek ID (2 bytes) */
29 #define SIO_REG_CLOCK_SEL	0x26	/* Clock select */
30 #define SIO_REG_ROM_ADDR_SEL	0x27	/* ROM address select */
31 #define SIO_F81866_REG_PORT_SEL	0x27	/* F81866 Multi-Function Register */
32 #define SIO_REG_TSI_LEVEL_SEL	0x28	/* TSI Level select */
33 #define SIO_REG_MFUNCT1		0x29	/* Multi function select 1 */
34 #define SIO_REG_MFUNCT2		0x2a	/* Multi function select 2 */
35 #define SIO_REG_MFUNCT3		0x2b	/* Multi function select 3 */
36 #define SIO_F81866_REG_GPIO1	0x2c	/* F81866 GPIO1 Enable Register */
37 #define SIO_REG_ENABLE		0x30	/* Logical device enable */
38 #define SIO_REG_ADDR		0x60	/* Logical device address (2 bytes) */
40 #define SIO_FINTEK_ID		0x1934	/* Manufacturers ID */
41 #define SIO_F71808_ID		0x0901	/* Chipset ID */
42 #define SIO_F71858_ID		0x0507	/* Chipset ID */
43 #define SIO_F71862_ID		0x0601	/* Chipset ID */
44 #define SIO_F71868_ID		0x1106	/* Chipset ID */
45 #define SIO_F71869_ID		0x0814	/* Chipset ID */
46 #define SIO_F71869A_ID		0x1007	/* Chipset ID */
47 #define SIO_F71882_ID		0x0541	/* Chipset ID */
48 #define SIO_F71889_ID		0x0723	/* Chipset ID */
49 #define SIO_F81803_ID		0x1210	/* Chipset ID */
50 #define SIO_F81865_ID		0x0704	/* Chipset ID */
51 #define SIO_F81866_ID		0x1010	/* Chipset ID */
52 #define SIO_F81966_ID		0x1502  /* F81804 chipset ID, same for f81966 */
54 #define F71808FG_REG_WDO_CONF		0xf0
55 #define F71808FG_REG_WDT_CONF		0xf5
56 #define F71808FG_REG_WD_TIME		0xf6
65 #define F81865_REG_WDO_CONF		0xfa
66 #define F81865_FLAG_WDOUT_EN		0
77 module_param(force_id, ushort, 0);
81 module_param(timeout, int, 0);
88 module_param(pulse_width, uint, 0);
90 	"Watchdog signal pulse width. 0(=level), 1, 25, 30, 125, 150, 5000 or 6000 ms"
94 module_param(f71862fg_pin, uint, 0);
104 module_param(start_withtimeout, uint, 0);
190 		pr_err("I/O address 0x%04x already in use\n", (int)base);  in superio_enter()
198 	return 0;  in superio_enter()
217 	if (timeout > 0xff) {  in fintek_wdt_set_timeout()
228 	return 0;  in fintek_wdt_set_timeout()
242 		wd->pulse_val = 0;  in fintek_wdt_set_pulse_width()
256 	return 0;  in fintek_wdt_set_pulse_width()
284 	return 0;  in fintek_wdt_keepalive()
335 			superio_inb(wd->sioaddr, SIO_REG_MFUNCT3) & 0xcf);  in fintek_wdt_start()
342 		superio_outb(wd->sioaddr, SIO_REG_TSI_LEVEL_SEL, 0x5f &  in fintek_wdt_start()
354 		 * GPIO1 Control Register when 27h BIT3:2 = 01 & BIT0 = 0.  in fintek_wdt_start()
356 		 *     BIT5: 0 -> WDTRST#  in fintek_wdt_start()
360 		tmp &= ~(BIT(3) | BIT(0));  in fintek_wdt_start()
377 	superio_set_bit(wd->sioaddr, SIO_REG_ENABLE, 0);  in fintek_wdt_start()
394 		/* Set WD_PSWIDTH bits (1:0) */  in fintek_wdt_start()
395 		wdt_conf = (wdt_conf & 0xfc) | (wd->pulse_val & 0x03);  in fintek_wdt_start()
428 	return 0;  in fintek_wdt_stop()
433 	return (superio_inb(wd->sioaddr, SIO_REG_ENABLE) & BIT(0))  in fintek_wdt_is_running()
451 	int wdt_conf, err = 0;  in fintek_wdt_probe()
455 	res = platform_get_resource(pdev, IORESOURCE_IO, 0);  in fintek_wdt_probe()
616 	static const unsigned short addrs[] = { 0x2e, 0x4e };  in fintek_wdt_init()
627 	for (i = 0; i < ARRAY_SIZE(addrs); i++) {  in fintek_wdt_init()
629 		if (ret >= 0)  in fintek_wdt_init()
654 	return 0;  in fintek_wdt_init()