Lines Matching +full:sr +full:- +full:idle +full:- +full:ns
2 * linux/drivers/video/savagefb.c -- S3 Savage Framebuffer Driver
4 * Copyright (c) 2001-2002 Denis Oliver Kropp <[email protected]>
16 * - hardware accelerated clear and move
19 * - wait for vertical retrace before writing to cr67
21 * - use synchronization registers cr23 and cr26
24 * - reset 3D engine
25 * - don't return alpha bits for 32bit format
28 * - added WaitIdle functions for all Savage types
29 * - do WaitIdle before mode switching
30 * - code cleanup
33 * - first working version
37 * - clock validations in decode_var
40 * - white margin on bootup
65 /* --------------------------------------------------------------------- */
72 MODULE_AUTHOR("(c) 2001-2002 Denis Oliver Kropp <[email protected]>");
79 /* --------------------------------------------------------------------- */
121 VGAwMISC(reg->MiscOutReg, par); in vgaHWRestore()
124 VGAwSEQ(i, reg->Sequencer[i], par); in vgaHWRestore()
126 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 or in vgaHWRestore()
128 VGAwCR(17, reg->CRTC[17] & ~0x80, par); in vgaHWRestore()
131 VGAwCR(i, reg->CRTC[i], par); in vgaHWRestore()
134 VGAwGR(i, reg->Graphics[i], par); in vgaHWRestore()
139 VGAwATTR(i, reg->Attribute[i], par); in vgaHWRestore()
149 reg->MiscOutReg = 0x23; in vgaHWInit()
151 if (!(timings->sync & FB_SYNC_HOR_HIGH_ACT)) in vgaHWInit()
152 reg->MiscOutReg |= 0x40; in vgaHWInit()
154 if (!(timings->sync & FB_SYNC_VERT_HIGH_ACT)) in vgaHWInit()
155 reg->MiscOutReg |= 0x80; in vgaHWInit()
160 reg->Sequencer[0x00] = 0x00; in vgaHWInit()
161 reg->Sequencer[0x01] = 0x01; in vgaHWInit()
162 reg->Sequencer[0x02] = 0x0F; in vgaHWInit()
163 reg->Sequencer[0x03] = 0x00; /* Font select */ in vgaHWInit()
164 reg->Sequencer[0x04] = 0x0E; /* Misc */ in vgaHWInit()
169 reg->CRTC[0x00] = (timings->HTotal >> 3) - 5; in vgaHWInit()
170 reg->CRTC[0x01] = (timings->HDisplay >> 3) - 1; in vgaHWInit()
171 reg->CRTC[0x02] = (timings->HSyncStart >> 3) - 1; in vgaHWInit()
172 reg->CRTC[0x03] = (((timings->HSyncEnd >> 3) - 1) & 0x1f) | 0x80; in vgaHWInit()
173 reg->CRTC[0x04] = (timings->HSyncStart >> 3); in vgaHWInit()
174 reg->CRTC[0x05] = ((((timings->HSyncEnd >> 3) - 1) & 0x20) << 2) | in vgaHWInit()
175 (((timings->HSyncEnd >> 3)) & 0x1f); in vgaHWInit()
176 reg->CRTC[0x06] = (timings->VTotal - 2) & 0xFF; in vgaHWInit()
177 reg->CRTC[0x07] = (((timings->VTotal - 2) & 0x100) >> 8) | in vgaHWInit()
178 (((timings->VDisplay - 1) & 0x100) >> 7) | in vgaHWInit()
179 ((timings->VSyncStart & 0x100) >> 6) | in vgaHWInit()
180 (((timings->VSyncStart - 1) & 0x100) >> 5) | in vgaHWInit()
182 (((timings->VTotal - 2) & 0x200) >> 4) | in vgaHWInit()
183 (((timings->VDisplay - 1) & 0x200) >> 3) | in vgaHWInit()
184 ((timings->VSyncStart & 0x200) >> 2); in vgaHWInit()
185 reg->CRTC[0x08] = 0x00; in vgaHWInit()
186 reg->CRTC[0x09] = (((timings->VSyncStart - 1) & 0x200) >> 4) | 0x40; in vgaHWInit()
188 if (timings->dblscan) in vgaHWInit()
189 reg->CRTC[0x09] |= 0x80; in vgaHWInit()
191 reg->CRTC[0x0a] = 0x00; in vgaHWInit()
192 reg->CRTC[0x0b] = 0x00; in vgaHWInit()
193 reg->CRTC[0x0c] = 0x00; in vgaHWInit()
194 reg->CRTC[0x0d] = 0x00; in vgaHWInit()
195 reg->CRTC[0x0e] = 0x00; in vgaHWInit()
196 reg->CRTC[0x0f] = 0x00; in vgaHWInit()
197 reg->CRTC[0x10] = timings->VSyncStart & 0xff; in vgaHWInit()
198 reg->CRTC[0x11] = (timings->VSyncEnd & 0x0f) | 0x20; in vgaHWInit()
199 reg->CRTC[0x12] = (timings->VDisplay - 1) & 0xff; in vgaHWInit()
200 reg->CRTC[0x13] = var->xres_virtual >> 4; in vgaHWInit()
201 reg->CRTC[0x14] = 0x00; in vgaHWInit()
202 reg->CRTC[0x15] = (timings->VSyncStart - 1) & 0xff; in vgaHWInit()
203 reg->CRTC[0x16] = (timings->VSyncEnd - 1) & 0xff; in vgaHWInit()
204 reg->CRTC[0x17] = 0xc3; in vgaHWInit()
205 reg->CRTC[0x18] = 0xff; in vgaHWInit()
216 reg->Graphics[0x00] = 0x00; in vgaHWInit()
217 reg->Graphics[0x01] = 0x00; in vgaHWInit()
218 reg->Graphics[0x02] = 0x00; in vgaHWInit()
219 reg->Graphics[0x03] = 0x00; in vgaHWInit()
220 reg->Graphics[0x04] = 0x00; in vgaHWInit()
221 reg->Graphics[0x05] = 0x40; in vgaHWInit()
222 reg->Graphics[0x06] = 0x05; /* only map 64k VGA memory !!!! */ in vgaHWInit()
223 reg->Graphics[0x07] = 0x0F; in vgaHWInit()
224 reg->Graphics[0x08] = 0xFF; in vgaHWInit()
227 reg->Attribute[0x00] = 0x00; /* standard colormap translation */ in vgaHWInit()
228 reg->Attribute[0x01] = 0x01; in vgaHWInit()
229 reg->Attribute[0x02] = 0x02; in vgaHWInit()
230 reg->Attribute[0x03] = 0x03; in vgaHWInit()
231 reg->Attribute[0x04] = 0x04; in vgaHWInit()
232 reg->Attribute[0x05] = 0x05; in vgaHWInit()
233 reg->Attribute[0x06] = 0x06; in vgaHWInit()
234 reg->Attribute[0x07] = 0x07; in vgaHWInit()
235 reg->Attribute[0x08] = 0x08; in vgaHWInit()
236 reg->Attribute[0x09] = 0x09; in vgaHWInit()
237 reg->Attribute[0x0a] = 0x0A; in vgaHWInit()
238 reg->Attribute[0x0b] = 0x0B; in vgaHWInit()
239 reg->Attribute[0x0c] = 0x0C; in vgaHWInit()
240 reg->Attribute[0x0d] = 0x0D; in vgaHWInit()
241 reg->Attribute[0x0e] = 0x0E; in vgaHWInit()
242 reg->Attribute[0x0f] = 0x0F; in vgaHWInit()
243 reg->Attribute[0x10] = 0x41; in vgaHWInit()
244 reg->Attribute[0x11] = 0xFF; in vgaHWInit()
245 reg->Attribute[0x12] = 0x0F; in vgaHWInit()
246 reg->Attribute[0x13] = 0x00; in vgaHWInit()
247 reg->Attribute[0x14] = 0x00; in vgaHWInit()
250 /* -------------------- Hardware specific routines ------------------------- */
260 int slots = MAXFIFO - space; in savage3D_waitfifo()
268 int slots = MAXFIFO - space; in savage4_waitfifo()
276 int slots = MAXFIFO - space; in savage2000_waitfifo()
281 /* Wait for idle accelerator */
307 BCI_BD_SET_BPP(GlobalBitmapDescriptor, par->depth); in SavageSetup2DEngine()
308 BCI_BD_SET_STRIDE(GlobalBitmapDescriptor, par->vwidth); in SavageSetup2DEngine()
310 switch(par->chip) { in SavageSetup2DEngine()
317 (par->cob_offset >> 11) | (par->cob_index << 29), in SavageSetup2DEngine()
343 (par->cob_offset >> 7) | (par->cob_index), in SavageSetup2DEngine()
354 /* Turn on 16-bit register access. */ in SavageSetup2DEngine()
376 par->bci_ptr = 0; in SavageSetup2DEngine()
377 par->SavageWaitFifo(par, 4); in SavageSetup2DEngine()
387 * --Tony in SavageSetup2DEngine()
389 par->bci_ptr = 0; in SavageSetup2DEngine()
390 par->SavageWaitFifo(par, 4); in SavageSetup2DEngine()
400 struct savagefb_par *par = info->par; in savagefb_set_clip()
404 par->bci_ptr = 0; in savagefb_set_clip()
405 par->SavageWaitFifo(par,3); in savagefb_set_clip()
444 diff = freq * (1 << n2) * n1 - BASE_FREQ * m; in SavageCalcClock()
446 diff = -diff; in SavageCalcClock()
457 *ndiv = best_n1 - 2; in SavageCalcClock()
459 *mdiv = best_m - 2; in SavageCalcClock()
482 diff = freq * (1 << n2) * n1 - BASE_FREQ * m; in common_calc_clock()
484 diff = -diff; in common_calc_clock()
496 *ndiv = (best_n1 - 2) | (best_n2 << 6); in common_calc_clock()
498 *ndiv = (best_n1 - 2) | (best_n2 << 5); in common_calc_clock()
500 *mdiv = best_m - 2; in common_calc_clock()
514 printk(KERN_DEBUG "SR x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE " in SavagePrintRegs()
538 /* --------------------------------------------------------------------- */
570 reg->SR08 = vga_in8(0x3c5, par); in savage_get_default_par()
575 reg->CR31 = vga_in8(0x3d5, par); in savage_get_default_par()
577 reg->CR32 = vga_in8(0x3d5, par); in savage_get_default_par()
579 reg->CR34 = vga_in8(0x3d5, par); in savage_get_default_par()
581 reg->CR36 = vga_in8(0x3d5, par); in savage_get_default_par()
583 reg->CR3A = vga_in8(0x3d5, par); in savage_get_default_par()
585 reg->CR40 = vga_in8(0x3d5, par); in savage_get_default_par()
587 reg->CR42 = vga_in8(0x3d5, par); in savage_get_default_par()
589 reg->CR45 = vga_in8(0x3d5, par); in savage_get_default_par()
591 reg->CR50 = vga_in8(0x3d5, par); in savage_get_default_par()
593 reg->CR51 = vga_in8(0x3d5, par); in savage_get_default_par()
595 reg->CR53 = vga_in8(0x3d5, par); in savage_get_default_par()
597 reg->CR58 = vga_in8(0x3d5, par); in savage_get_default_par()
599 reg->CR60 = vga_in8(0x3d5, par); in savage_get_default_par()
601 reg->CR66 = vga_in8(0x3d5, par); in savage_get_default_par()
603 reg->CR67 = vga_in8(0x3d5, par); in savage_get_default_par()
605 reg->CR68 = vga_in8(0x3d5, par); in savage_get_default_par()
607 reg->CR69 = vga_in8(0x3d5, par); in savage_get_default_par()
609 reg->CR6F = vga_in8(0x3d5, par); in savage_get_default_par()
612 reg->CR33 = vga_in8(0x3d5, par); in savage_get_default_par()
614 reg->CR86 = vga_in8(0x3d5, par); in savage_get_default_par()
616 reg->CR88 = vga_in8(0x3d5, par); in savage_get_default_par()
618 reg->CR90 = vga_in8(0x3d5, par); in savage_get_default_par()
620 reg->CR91 = vga_in8(0x3d5, par); in savage_get_default_par()
622 reg->CRB0 = vga_in8(0x3d5, par) | 0x80; in savage_get_default_par()
626 reg->CR3B = vga_in8(0x3d5, par); in savage_get_default_par()
628 reg->CR3C = vga_in8(0x3d5, par); in savage_get_default_par()
630 reg->CR43 = vga_in8(0x3d5, par); in savage_get_default_par()
632 reg->CR5D = vga_in8(0x3d5, par); in savage_get_default_par()
634 reg->CR5E = vga_in8(0x3d5, par); in savage_get_default_par()
636 reg->CR65 = vga_in8(0x3d5, par); in savage_get_default_par()
640 reg->SR0E = vga_in8(0x3c5, par); in savage_get_default_par()
642 reg->SR0F = vga_in8(0x3c5, par); in savage_get_default_par()
644 reg->SR10 = vga_in8(0x3c5, par); in savage_get_default_par()
646 reg->SR11 = vga_in8(0x3c5, par); in savage_get_default_par()
648 reg->SR12 = vga_in8(0x3c5, par); in savage_get_default_par()
650 reg->SR13 = vga_in8(0x3c5, par); in savage_get_default_par()
652 reg->SR29 = vga_in8(0x3c5, par); in savage_get_default_par()
655 reg->SR15 = vga_in8(0x3c5, par); in savage_get_default_par()
657 reg->SR30 = vga_in8(0x3c5, par); in savage_get_default_par()
659 reg->SR18 = vga_in8(0x3c5, par); in savage_get_default_par()
662 if (par->chip == S3_SAVAGE_MX) { in savage_get_default_par()
667 reg->SR54[i] = vga_in8(0x3c5, par); in savage_get_default_par()
679 if (par->chip != S3_SAVAGE_MX) { in savage_get_default_par()
680 reg->MMPR0 = savage_in32(FIFO_CONTROL_REG, par); in savage_get_default_par()
681 reg->MMPR1 = savage_in32(MIU_CONTROL_REG, par); in savage_get_default_par()
682 reg->MMPR2 = savage_in32(STREAMS_TIMEOUT_REG, par); in savage_get_default_par()
683 reg->MMPR3 = savage_in32(MISC_TIMEOUT_REG, par); in savage_get_default_par()
723 vga_out8(0x3c5, reg->SR08, par); in savage_set_default_par()
728 vga_out8(0x3d5, reg->CR31, par); in savage_set_default_par()
730 vga_out8(0x3d5, reg->CR32, par); in savage_set_default_par()
732 vga_out8(0x3d5, reg->CR34, par); in savage_set_default_par()
734 vga_out8(0x3d5,reg->CR36, par); in savage_set_default_par()
736 vga_out8(0x3d5, reg->CR3A, par); in savage_set_default_par()
738 vga_out8(0x3d5, reg->CR40, par); in savage_set_default_par()
740 vga_out8(0x3d5, reg->CR42, par); in savage_set_default_par()
742 vga_out8(0x3d5, reg->CR45, par); in savage_set_default_par()
744 vga_out8(0x3d5, reg->CR50, par); in savage_set_default_par()
746 vga_out8(0x3d5, reg->CR51, par); in savage_set_default_par()
748 vga_out8(0x3d5, reg->CR53, par); in savage_set_default_par()
750 vga_out8(0x3d5, reg->CR58, par); in savage_set_default_par()
752 vga_out8(0x3d5, reg->CR60, par); in savage_set_default_par()
754 vga_out8(0x3d5, reg->CR66, par); in savage_set_default_par()
756 vga_out8(0x3d5, reg->CR67, par); in savage_set_default_par()
758 vga_out8(0x3d5, reg->CR68, par); in savage_set_default_par()
760 vga_out8(0x3d5, reg->CR69, par); in savage_set_default_par()
762 vga_out8(0x3d5, reg->CR6F, par); in savage_set_default_par()
765 vga_out8(0x3d5, reg->CR33, par); in savage_set_default_par()
767 vga_out8(0x3d5, reg->CR86, par); in savage_set_default_par()
769 vga_out8(0x3d5, reg->CR88, par); in savage_set_default_par()
771 vga_out8(0x3d5, reg->CR90, par); in savage_set_default_par()
773 vga_out8(0x3d5, reg->CR91, par); in savage_set_default_par()
775 vga_out8(0x3d5, reg->CRB0, par); in savage_set_default_par()
779 vga_out8(0x3d5, reg->CR3B, par); in savage_set_default_par()
781 vga_out8(0x3d5, reg->CR3C, par); in savage_set_default_par()
783 vga_out8(0x3d5, reg->CR43, par); in savage_set_default_par()
785 vga_out8(0x3d5, reg->CR5D, par); in savage_set_default_par()
787 vga_out8(0x3d5, reg->CR5E, par); in savage_set_default_par()
789 vga_out8(0x3d5, reg->CR65, par); in savage_set_default_par()
793 vga_out8(0x3c5, reg->SR0E, par); in savage_set_default_par()
795 vga_out8(0x3c5, reg->SR0F, par); in savage_set_default_par()
797 vga_out8(0x3c5, reg->SR10, par); in savage_set_default_par()
799 vga_out8(0x3c5, reg->SR11, par); in savage_set_default_par()
801 vga_out8(0x3c5, reg->SR12, par); in savage_set_default_par()
803 vga_out8(0x3c5, reg->SR13, par); in savage_set_default_par()
805 vga_out8(0x3c5, reg->SR29, par); in savage_set_default_par()
808 vga_out8(0x3c5, reg->SR15, par); in savage_set_default_par()
810 vga_out8(0x3c5, reg->SR30, par); in savage_set_default_par()
812 vga_out8(0x3c5, reg->SR18, par); in savage_set_default_par()
815 if (par->chip == S3_SAVAGE_MX) { in savage_set_default_par()
820 vga_out8(0x3c5, reg->SR54[i], par); in savage_set_default_par()
832 if (par->chip != S3_SAVAGE_MX) { in savage_set_default_par()
833 savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par); in savage_set_default_par()
834 savage_out32(MIU_CONTROL_REG, reg->MMPR1, par); in savage_set_default_par()
835 savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par); in savage_set_default_par()
836 savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par); in savage_set_default_par()
848 var->xres = var->xres_virtual = modedb->xres; in savage_update_var()
849 var->yres = modedb->yres; in savage_update_var()
850 if (var->yres_virtual < var->yres) in savage_update_var()
851 var->yres_virtual = var->yres; in savage_update_var()
852 var->xoffset = var->yoffset = 0; in savage_update_var()
853 var->pixclock = modedb->pixclock; in savage_update_var()
854 var->left_margin = modedb->left_margin; in savage_update_var()
855 var->right_margin = modedb->right_margin; in savage_update_var()
856 var->upper_margin = modedb->upper_margin; in savage_update_var()
857 var->lower_margin = modedb->lower_margin; in savage_update_var()
858 var->hsync_len = modedb->hsync_len; in savage_update_var()
859 var->vsync_len = modedb->vsync_len; in savage_update_var()
860 var->sync = modedb->sync; in savage_update_var()
861 var->vmode = modedb->vmode; in savage_update_var()
867 struct savagefb_par *par = info->par; in savagefb_check_var()
872 if (!var->pixclock) in savagefb_check_var()
873 return -EINVAL; in savagefb_check_var()
875 var->transp.offset = 0; in savagefb_check_var()
876 var->transp.length = 0; in savagefb_check_var()
877 switch (var->bits_per_pixel) { in savagefb_check_var()
879 var->red.offset = var->green.offset = in savagefb_check_var()
880 var->blue.offset = 0; in savagefb_check_var()
881 var->red.length = var->green.length = in savagefb_check_var()
882 var->blue.length = var->bits_per_pixel; in savagefb_check_var()
885 var->red.offset = 11; in savagefb_check_var()
886 var->red.length = 5; in savagefb_check_var()
887 var->green.offset = 5; in savagefb_check_var()
888 var->green.length = 6; in savagefb_check_var()
889 var->blue.offset = 0; in savagefb_check_var()
890 var->blue.length = 5; in savagefb_check_var()
893 var->transp.offset = 24; in savagefb_check_var()
894 var->transp.length = 8; in savagefb_check_var()
895 var->red.offset = 16; in savagefb_check_var()
896 var->red.length = 8; in savagefb_check_var()
897 var->green.offset = 8; in savagefb_check_var()
898 var->green.length = 8; in savagefb_check_var()
899 var->blue.offset = 0; in savagefb_check_var()
900 var->blue.length = 8; in savagefb_check_var()
904 return -EINVAL; in savagefb_check_var()
907 if (!info->monspecs.hfmax || !info->monspecs.vfmax || in savagefb_check_var()
908 !info->monspecs.dclkmax || !fb_validate_mode(var, info)) in savagefb_check_var()
912 if (!mode_valid && info->monspecs.gtf) { in savagefb_check_var()
920 mode = fb_find_best_mode(var, &info->modelist); in savagefb_check_var()
927 if (!mode_valid && info->monspecs.modedb_len) in savagefb_check_var()
928 return -EINVAL; in savagefb_check_var()
931 if (par->SavagePanelWidth && in savagefb_check_var()
932 (var->xres > par->SavagePanelWidth || in savagefb_check_var()
933 var->yres > par->SavagePanelHeight)) { in savagefb_check_var()
935 "(%dx%d)\n", var->xres, var->yres, in savagefb_check_var()
936 par->SavagePanelWidth, in savagefb_check_var()
937 par->SavagePanelHeight); in savagefb_check_var()
938 return -1; in savagefb_check_var()
941 if (var->yres_virtual < var->yres) in savagefb_check_var()
942 var->yres_virtual = var->yres; in savagefb_check_var()
943 if (var->xres_virtual < var->xres) in savagefb_check_var()
944 var->xres_virtual = var->xres; in savagefb_check_var()
946 vramlen = info->fix.smem_len; in savagefb_check_var()
948 memlen = var->xres_virtual * var->bits_per_pixel * in savagefb_check_var()
949 var->yres_virtual / 8; in savagefb_check_var()
951 var->yres_virtual = vramlen * 8 / in savagefb_check_var()
952 (var->xres_virtual * var->bits_per_pixel); in savagefb_check_var()
953 memlen = var->xres_virtual * var->bits_per_pixel * in savagefb_check_var()
954 var->yres_virtual / 8; in savagefb_check_var()
958 if it was possible. We should return -EINVAL, but I disagree */ in savagefb_check_var()
959 if (var->yres_virtual < var->yres) in savagefb_check_var()
960 var->yres = var->yres_virtual; in savagefb_check_var()
961 if (var->xres_virtual < var->xres) in savagefb_check_var()
962 var->xres = var->xres_virtual; in savagefb_check_var()
963 if (var->xoffset + var->xres > var->xres_virtual) in savagefb_check_var()
964 var->xoffset = var->xres_virtual - var->xres; in savagefb_check_var()
965 if (var->yoffset + var->yres > var->yres_virtual) in savagefb_check_var()
966 var->yoffset = var->yres_virtual - var->yres; in savagefb_check_var()
980 unsigned int pixclock = var->pixclock; in savagefb_decode_var()
986 if (!pixclock) pixclock = 10000; /* 10ns = 100MHz */ in savagefb_decode_var()
989 timings.dblscan = var->vmode & FB_VMODE_DOUBLE; in savagefb_decode_var()
990 timings.interlaced = var->vmode & FB_VMODE_INTERLACED; in savagefb_decode_var()
991 timings.HDisplay = var->xres; in savagefb_decode_var()
992 timings.HSyncStart = timings.HDisplay + var->right_margin; in savagefb_decode_var()
993 timings.HSyncEnd = timings.HSyncStart + var->hsync_len; in savagefb_decode_var()
994 timings.HTotal = timings.HSyncEnd + var->left_margin; in savagefb_decode_var()
995 timings.VDisplay = var->yres; in savagefb_decode_var()
996 timings.VSyncStart = timings.VDisplay + var->lower_margin; in savagefb_decode_var()
997 timings.VSyncEnd = timings.VSyncStart + var->vsync_len; in savagefb_decode_var()
998 timings.VTotal = timings.VSyncEnd + var->upper_margin; in savagefb_decode_var()
999 timings.sync = var->sync; in savagefb_decode_var()
1002 par->depth = var->bits_per_pixel; in savagefb_decode_var()
1003 par->vwidth = var->xres_virtual; in savagefb_decode_var()
1005 if (var->bits_per_pixel == 16 && par->chip == S3_SAVAGE3D) { in savagefb_decode_var()
1021 reg->CR67 = 0x00; in savagefb_decode_var()
1023 switch(var->bits_per_pixel) { in savagefb_decode_var()
1025 if ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)) in savagefb_decode_var()
1026 reg->CR67 = 0x10; /* 8bpp, 2 pixels/clock */ in savagefb_decode_var()
1028 reg->CR67 = 0x00; /* 8bpp, 1 pixel/clock */ in savagefb_decode_var()
1031 if (S3_SAVAGE_MOBILE_SERIES(par->chip) || in savagefb_decode_var()
1032 ((par->chip == S3_SAVAGE2000) && (dclk >= 230000))) in savagefb_decode_var()
1033 reg->CR67 = 0x30; /* 15bpp, 2 pixel/clock */ in savagefb_decode_var()
1035 reg->CR67 = 0x20; /* 15bpp, 1 pixels/clock */ in savagefb_decode_var()
1038 if (S3_SAVAGE_MOBILE_SERIES(par->chip) || in savagefb_decode_var()
1039 ((par->chip == S3_SAVAGE2000) && (dclk >= 230000))) in savagefb_decode_var()
1040 reg->CR67 = 0x50; /* 16bpp, 2 pixel/clock */ in savagefb_decode_var()
1042 reg->CR67 = 0x40; /* 16bpp, 1 pixels/clock */ in savagefb_decode_var()
1045 reg->CR67 = 0x70; in savagefb_decode_var()
1048 reg->CR67 = 0xd0; in savagefb_decode_var()
1054 * match. Fall back to traditional register-crunching. in savagefb_decode_var()
1059 if (1 /*FIXME:psav->pci_burst*/) in savagefb_decode_var()
1060 reg->CR3A = (tmp & 0x7f) | 0x15; in savagefb_decode_var()
1062 reg->CR3A = tmp | 0x95; in savagefb_decode_var()
1064 reg->CR53 = 0x00; in savagefb_decode_var()
1065 reg->CR31 = 0x8c; in savagefb_decode_var()
1066 reg->CR66 = 0x89; in savagefb_decode_var()
1069 reg->CR58 = vga_in8(0x3d5, par) & 0x80; in savagefb_decode_var()
1070 reg->CR58 |= 0x13; in savagefb_decode_var()
1072 reg->SR15 = 0x03 | 0x80; in savagefb_decode_var()
1073 reg->SR18 = 0x00; in savagefb_decode_var()
1074 reg->CR43 = reg->CR45 = reg->CR65 = 0x00; in savagefb_decode_var()
1077 reg->CR40 = vga_in8(0x3d5, par) & ~0x01; in savagefb_decode_var()
1079 reg->MMPR0 = 0x010400; in savagefb_decode_var()
1080 reg->MMPR1 = 0x00; in savagefb_decode_var()
1081 reg->MMPR2 = 0x0808; in savagefb_decode_var()
1082 reg->MMPR3 = 0x08080810; in savagefb_decode_var()
1087 if (par->MCLK <= 0) { in savagefb_decode_var()
1088 reg->SR10 = 255; in savagefb_decode_var()
1089 reg->SR11 = 255; in savagefb_decode_var()
1091 common_calc_clock(par->MCLK, 1, 1, 31, 0, 3, 135000, 270000, in savagefb_decode_var()
1092 ®->SR11, ®->SR10); in savagefb_decode_var()
1093 /* reg->SR10 = 80; // MCLK == 286000 */ in savagefb_decode_var()
1094 /* reg->SR11 = 125; */ in savagefb_decode_var()
1097 reg->SR12 = (r << 6) | (n & 0x3f); in savagefb_decode_var()
1098 reg->SR13 = m & 0xff; in savagefb_decode_var()
1099 reg->SR29 = (r & 4) | (m & 0x100) >> 5 | (n & 0x40) >> 2; in savagefb_decode_var()
1101 if (var->bits_per_pixel < 24) in savagefb_decode_var()
1102 reg->MMPR0 -= 0x8000; in savagefb_decode_var()
1104 reg->MMPR0 -= 0x4000; in savagefb_decode_var()
1107 reg->CR42 = 0x20; in savagefb_decode_var()
1109 reg->CR42 = 0x00; in savagefb_decode_var()
1111 reg->CR34 = 0x10; /* display fifo */ in savagefb_decode_var()
1113 i = ((((timings.HTotal >> 3) - 5) & 0x100) >> 8) | in savagefb_decode_var()
1114 ((((timings.HDisplay >> 3) - 1) & 0x100) >> 7) | in savagefb_decode_var()
1115 ((((timings.HSyncStart >> 3) - 1) & 0x100) >> 6) | in savagefb_decode_var()
1118 if ((timings.HSyncEnd >> 3) - (timings.HSyncStart >> 3) > 64) in savagefb_decode_var()
1120 if ((timings.HSyncEnd >> 3) - (timings.HSyncStart >> 3) > 32) in savagefb_decode_var()
1123 j = (reg->CRTC[0] + ((i & 0x01) << 8) + in savagefb_decode_var()
1124 reg->CRTC[4] + ((i & 0x10) << 4) + 1) / 2; in savagefb_decode_var()
1126 if (j - (reg->CRTC[4] + ((i & 0x10) << 4)) < 4) { in savagefb_decode_var()
1127 if (reg->CRTC[4] + ((i & 0x10) << 4) + 4 <= in savagefb_decode_var()
1128 reg->CRTC[0] + ((i & 0x01) << 8)) in savagefb_decode_var()
1129 j = reg->CRTC[4] + ((i & 0x10) << 4) + 4; in savagefb_decode_var()
1131 j = reg->CRTC[0] + ((i & 0x01) << 8) + 1; in savagefb_decode_var()
1134 reg->CR3B = j & 0xff; in savagefb_decode_var()
1136 reg->CR3C = (reg->CRTC[0] + ((i & 0x01) << 8)) / 2; in savagefb_decode_var()
1137 reg->CR5D = i; in savagefb_decode_var()
1138 reg->CR5E = (((timings.VTotal - 2) & 0x400) >> 10) | in savagefb_decode_var()
1139 (((timings.VDisplay - 1) & 0x400) >> 9) | in savagefb_decode_var()
1142 width = (var->xres_virtual * ((var->bits_per_pixel+7) / 8)) >> 3; in savagefb_decode_var()
1143 reg->CR91 = reg->CRTC[19] = 0xff & width; in savagefb_decode_var()
1144 reg->CR51 = (0x300 & width) >> 4; in savagefb_decode_var()
1145 reg->CR90 = 0x80 | (width >> 8); in savagefb_decode_var()
1146 reg->MiscOutReg |= 0x0c; in savagefb_decode_var()
1150 if (var->bits_per_pixel <= 8) in savagefb_decode_var()
1151 reg->CR50 = 0; in savagefb_decode_var()
1152 else if (var->bits_per_pixel <= 16) in savagefb_decode_var()
1153 reg->CR50 = 0x10; in savagefb_decode_var()
1155 reg->CR50 = 0x30; in savagefb_decode_var()
1157 if (var->xres_virtual <= 640) in savagefb_decode_var()
1158 reg->CR50 |= 0x40; in savagefb_decode_var()
1159 else if (var->xres_virtual == 800) in savagefb_decode_var()
1160 reg->CR50 |= 0x80; in savagefb_decode_var()
1161 else if (var->xres_virtual == 1024) in savagefb_decode_var()
1162 reg->CR50 |= 0x00; in savagefb_decode_var()
1163 else if (var->xres_virtual == 1152) in savagefb_decode_var()
1164 reg->CR50 |= 0x01; in savagefb_decode_var()
1165 else if (var->xres_virtual == 1280) in savagefb_decode_var()
1166 reg->CR50 |= 0xc0; in savagefb_decode_var()
1167 else if (var->xres_virtual == 1600) in savagefb_decode_var()
1168 reg->CR50 |= 0x81; in savagefb_decode_var()
1170 reg->CR50 |= 0xc1; /* Use GBD */ in savagefb_decode_var()
1172 if (par->chip == S3_SAVAGE2000) in savagefb_decode_var()
1173 reg->CR33 = 0x08; in savagefb_decode_var()
1175 reg->CR33 = 0x20; in savagefb_decode_var()
1177 reg->CRTC[0x17] = 0xeb; in savagefb_decode_var()
1179 reg->CR67 |= 1; in savagefb_decode_var()
1182 reg->CR36 = vga_in8(0x3d5, par); in savagefb_decode_var()
1184 reg->CR68 = vga_in8(0x3d5, par); in savagefb_decode_var()
1185 reg->CR69 = 0; in savagefb_decode_var()
1187 reg->CR6F = vga_in8(0x3d5, par); in savagefb_decode_var()
1189 reg->CR86 = vga_in8(0x3d5, par); in savagefb_decode_var()
1191 reg->CR88 = vga_in8(0x3d5, par) | 0x08; in savagefb_decode_var()
1193 reg->CRB0 = vga_in8(0x3d5, par) | 0x80; in savagefb_decode_var()
1198 /* --------------------------------------------------------------------- */
1210 struct savagefb_par *par = info->par; in savagefb_setcolreg()
1213 return -EINVAL; in savagefb_setcolreg()
1215 par->palette[regno].red = red; in savagefb_setcolreg()
1216 par->palette[regno].green = green; in savagefb_setcolreg()
1217 par->palette[regno].blue = blue; in savagefb_setcolreg()
1218 par->palette[regno].transp = transp; in savagefb_setcolreg()
1220 switch (info->var.bits_per_pixel) { in savagefb_setcolreg()
1231 ((u32 *)info->pseudo_palette)[regno] = in savagefb_setcolreg()
1239 ((u32 *)info->pseudo_palette)[regno] = in savagefb_setcolreg()
1246 ((u32 *)info->pseudo_palette)[regno] = in savagefb_setcolreg()
1266 par->SavageWaitIdle(par); in savagefb_set_par_int()
1279 * haven't been able to find what causes it, but a non-destructive in savagefb_set_par_int()
1286 vga_out8(0x3d5, cr67/*par->CR67*/ & ~0x0c, par); /* no STREAMS yet */ in savagefb_set_par_int()
1295 vga_out8(0x3d5, reg->CR66, par); in savagefb_set_par_int()
1297 vga_out8(0x3d5, reg->CR3A, par); in savagefb_set_par_int()
1299 vga_out8(0x3d5, reg->CR31, par); in savagefb_set_par_int()
1301 vga_out8(0x3d5, reg->CR32, par); in savagefb_set_par_int()
1303 vga_out8(0x3d5, reg->CR58, par); in savagefb_set_par_int()
1305 vga_out8(0x3d5, reg->CR53 & 0x7f, par); in savagefb_set_par_int()
1312 vga_out8(0x3c5, reg->SR0E, par); in savagefb_set_par_int()
1314 vga_out8(0x3c5, reg->SR0F, par); in savagefb_set_par_int()
1316 vga_out8(0x3c5, reg->SR29, par); in savagefb_set_par_int()
1318 vga_out8(0x3c5, reg->SR15, par); in savagefb_set_par_int()
1321 if (par->chip == S3_SAVAGE_MX) { in savagefb_set_par_int()
1326 vga_out8(0x3c5, reg->SR54[i], par); in savagefb_set_par_int()
1334 vga_out8(0x3d5, reg->CR53, par); in savagefb_set_par_int()
1336 vga_out8(0x3d5, reg->CR5D, par); in savagefb_set_par_int()
1338 vga_out8(0x3d5, reg->CR5E, par); in savagefb_set_par_int()
1340 vga_out8(0x3d5, reg->CR3B, par); in savagefb_set_par_int()
1342 vga_out8(0x3d5, reg->CR3C, par); in savagefb_set_par_int()
1344 vga_out8(0x3d5, reg->CR43, par); in savagefb_set_par_int()
1346 vga_out8(0x3d5, reg->CR65, par); in savagefb_set_par_int()
1356 vga_out8(0x3d5, reg->CR67 & ~0x0c, par); in savagefb_set_par_int()
1360 vga_out8(0x3d5, reg->CR34, par); in savagefb_set_par_int()
1362 vga_out8(0x3d5, reg->CR40, par); in savagefb_set_par_int()
1364 vga_out8(0x3d5, reg->CR42, par); in savagefb_set_par_int()
1366 vga_out8(0x3d5, reg->CR45, par); in savagefb_set_par_int()
1368 vga_out8(0x3d5, reg->CR50, par); in savagefb_set_par_int()
1370 vga_out8(0x3d5, reg->CR51, par); in savagefb_set_par_int()
1374 vga_out8(0x3d5, reg->CR36, par); in savagefb_set_par_int()
1376 vga_out8(0x3d5, reg->CR60, par); in savagefb_set_par_int()
1378 vga_out8(0x3d5, reg->CR68, par); in savagefb_set_par_int()
1380 vga_out8(0x3d5, reg->CR69, par); in savagefb_set_par_int()
1382 vga_out8(0x3d5, reg->CR6F, par); in savagefb_set_par_int()
1385 vga_out8(0x3d5, reg->CR33, par); in savagefb_set_par_int()
1387 vga_out8(0x3d5, reg->CR86, par); in savagefb_set_par_int()
1389 vga_out8(0x3d5, reg->CR88, par); in savagefb_set_par_int()
1391 vga_out8(0x3d5, reg->CR90, par); in savagefb_set_par_int()
1393 vga_out8(0x3d5, reg->CR91, par); in savagefb_set_par_int()
1395 if (par->chip == S3_SAVAGE4) { in savagefb_set_par_int()
1397 vga_out8(0x3d5, reg->CRB0, par); in savagefb_set_par_int()
1401 vga_out8(0x3d5, reg->CR32, par); in savagefb_set_par_int()
1410 if (reg->SR10 != 255) { in savagefb_set_par_int()
1412 vga_out8(0x3c5, reg->SR10, par); in savagefb_set_par_int()
1414 vga_out8(0x3c5, reg->SR11, par); in savagefb_set_par_int()
1419 vga_out8(0x3c5, reg->SR0E, par); in savagefb_set_par_int()
1421 vga_out8(0x3c5, reg->SR0F, par); in savagefb_set_par_int()
1423 vga_out8(0x3c5, reg->SR12, par); in savagefb_set_par_int()
1425 vga_out8(0x3c5, reg->SR13, par); in savagefb_set_par_int()
1427 vga_out8(0x3c5, reg->SR29, par); in savagefb_set_par_int()
1429 vga_out8(0x3c5, reg->SR18, par); in savagefb_set_par_int()
1438 vga_out8(0x3c5, reg->SR15, par); in savagefb_set_par_int()
1442 vga_out8(0x3c5, reg->SR30, par); in savagefb_set_par_int()
1444 vga_out8(0x3c5, reg->SR08, par); in savagefb_set_par_int()
1449 vga_out8(0x3d5, reg->CR67, par); in savagefb_set_par_int()
1458 if (par->chip != S3_SAVAGE_MX) { in savagefb_set_par_int()
1460 savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par); in savagefb_set_par_int()
1461 par->SavageWaitIdle(par); in savagefb_set_par_int()
1462 savage_out32(MIU_CONTROL_REG, reg->MMPR1, par); in savagefb_set_par_int()
1463 par->SavageWaitIdle(par); in savagefb_set_par_int()
1464 savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par); in savagefb_set_par_int()
1465 par->SavageWaitIdle(par); in savagefb_set_par_int()
1466 savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par); in savagefb_set_par_int()
1490 info->fix.line_length = info->var.xres_virtual * in savagefb_set_fix()
1491 info->var.bits_per_pixel / 8; in savagefb_set_fix()
1493 if (info->var.bits_per_pixel == 8) { in savagefb_set_fix()
1494 info->fix.visual = FB_VISUAL_PSEUDOCOLOR; in savagefb_set_fix()
1495 info->fix.xpanstep = 4; in savagefb_set_fix()
1497 info->fix.visual = FB_VISUAL_TRUECOLOR; in savagefb_set_fix()
1498 info->fix.xpanstep = 2; in savagefb_set_fix()
1505 struct savagefb_par *par = info->par; in savagefb_set_par()
1506 struct fb_var_screeninfo *var = &info->var; in savagefb_set_par()
1510 err = savagefb_decode_var(var, par, &par->state); in savagefb_set_par()
1514 if (par->dacSpeedBpp <= 0) { in savagefb_set_par()
1515 if (var->bits_per_pixel > 24) in savagefb_set_par()
1516 par->dacSpeedBpp = par->clock[3]; in savagefb_set_par()
1517 else if (var->bits_per_pixel >= 24) in savagefb_set_par()
1518 par->dacSpeedBpp = par->clock[2]; in savagefb_set_par()
1519 else if ((var->bits_per_pixel > 8) && (var->bits_per_pixel < 24)) in savagefb_set_par()
1520 par->dacSpeedBpp = par->clock[1]; in savagefb_set_par()
1521 else if (var->bits_per_pixel <= 8) in savagefb_set_par()
1522 par->dacSpeedBpp = par->clock[0]; in savagefb_set_par()
1526 par->maxClock = par->dacSpeedBpp; in savagefb_set_par()
1527 par->minClock = 10000; in savagefb_set_par()
1529 savagefb_set_par_int(par, &par->state); in savagefb_set_par()
1530 fb_set_cmap(&info->cmap, info); in savagefb_set_par()
1544 struct savagefb_par *par = info->par; in savagefb_pan_display()
1547 base = (var->yoffset * info->fix.line_length in savagefb_pan_display()
1548 + (var->xoffset & ~1) * ((info->var.bits_per_pixel+7) / 8)) >> 2; in savagefb_pan_display()
1556 struct savagefb_par *par = info->par; in savagefb_blank()
1559 if (par->display_type == DISP_CRT) { in savagefb_blank()
1587 if (par->display_type == DISP_LCD || in savagefb_blank()
1588 par->display_type == DISP_DFP) { in savagefb_blank()
1592 vga_out8(0x3c4, 0x31, par); /* SR31 bit 4 - FP enable */ in savagefb_blank()
1598 vga_out8(0x3c4, 0x31, par); /* SR31 bit 4 - FP enable */ in savagefb_blank()
1609 struct savagefb_par *par = info->par; in savagefb_open()
1611 mutex_lock(&par->open_lock); in savagefb_open()
1613 if (!par->open_count) { in savagefb_open()
1614 memset(&par->vgastate, 0, sizeof(par->vgastate)); in savagefb_open()
1615 par->vgastate.flags = VGA_SAVE_CMAP | VGA_SAVE_FONTS | in savagefb_open()
1617 par->vgastate.vgabase = par->mmio.vbase + 0x8000; in savagefb_open()
1618 save_vga(&par->vgastate); in savagefb_open()
1619 savage_get_default_par(par, &par->initial); in savagefb_open()
1622 par->open_count++; in savagefb_open()
1623 mutex_unlock(&par->open_lock); in savagefb_open()
1629 struct savagefb_par *par = info->par; in savagefb_release()
1631 mutex_lock(&par->open_lock); in savagefb_release()
1633 if (par->open_count == 1) { in savagefb_release()
1634 savage_set_default_par(par, &par->initial); in savagefb_release()
1635 restore_vga(&par->vgastate); in savagefb_release()
1638 par->open_count--; in savagefb_release()
1639 mutex_unlock(&par->open_lock); in savagefb_release()
1664 /* --------------------------------------------------------------------- */
1695 if (par->chip >= S3_SAVAGE4) { in savage_enable_mmio()
1709 if (par->chip >= S3_SAVAGE4) { in savage_disable_mmio()
1719 struct savagefb_par *par = info->par; in savage_map_mmio()
1722 if (S3_SAVAGE3D_SERIES(par->chip)) in savage_map_mmio()
1723 par->mmio.pbase = pci_resource_start(par->pcidev, 0) + in savage_map_mmio()
1726 par->mmio.pbase = pci_resource_start(par->pcidev, 0) + in savage_map_mmio()
1729 par->mmio.len = SAVAGE_NEWMMIO_REGSIZE; in savage_map_mmio()
1731 par->mmio.vbase = ioremap(par->mmio.pbase, par->mmio.len); in savage_map_mmio()
1732 if (!par->mmio.vbase) { in savage_map_mmio()
1734 return -ENOMEM; in savage_map_mmio()
1737 par->mmio.vbase); in savage_map_mmio()
1739 info->fix.mmio_start = par->mmio.pbase; in savage_map_mmio()
1740 info->fix.mmio_len = par->mmio.len; in savage_map_mmio()
1742 par->bci_base = (u32 __iomem *)(par->mmio.vbase + BCI_BUFFER_OFFSET); in savage_map_mmio()
1743 par->bci_ptr = 0; in savage_map_mmio()
1752 struct savagefb_par *par = info->par; in savage_unmap_mmio()
1757 if (par->mmio.vbase) { in savage_unmap_mmio()
1758 iounmap(par->mmio.vbase); in savage_unmap_mmio()
1759 par->mmio.vbase = NULL; in savage_unmap_mmio()
1765 struct savagefb_par *par = info->par; in savage_map_video()
1770 if (S3_SAVAGE3D_SERIES(par->chip)) in savage_map_video()
1775 par->video.pbase = pci_resource_start(par->pcidev, resource); in savage_map_video()
1776 par->video.len = video_len; in savage_map_video()
1777 par->video.vbase = ioremap_wc(par->video.pbase, par->video.len); in savage_map_video()
1779 if (!par->video.vbase) { in savage_map_video()
1781 return -ENOMEM; in savage_map_video()
1784 "pbase == %x\n", par->video.vbase, par->video.pbase); in savage_map_video()
1786 info->fix.smem_start = par->video.pbase; in savage_map_video()
1787 info->fix.smem_len = par->video.len - par->cob_size; in savage_map_video()
1788 info->screen_base = par->video.vbase; in savage_map_video()
1789 par->video.wc_cookie = arch_phys_wc_add(par->video.pbase, video_len); in savage_map_video()
1792 memset_io(par->video.vbase, 0, par->video.len); in savage_map_video()
1799 struct savagefb_par *par = info->par; in savage_unmap_video()
1803 if (par->video.vbase) { in savage_unmap_video()
1804 arch_phys_wc_del(par->video.wc_cookie); in savage_unmap_video()
1805 iounmap(par->video.vbase); in savage_unmap_video()
1806 par->video.vbase = NULL; in savage_unmap_video()
1807 info->screen_base = NULL; in savage_unmap_video()
1823 /* unprotect CRTC[0-7] */ in savage_init_hw()
1851 switch (par->chip) { in savage_init_hw()
1918 par->numClocks = 4; in savage_init_hw()
1919 par->clock[0] = 250000; in savage_init_hw()
1920 par->clock[1] = 250000; in savage_init_hw()
1921 par->clock[2] = 220000; in savage_init_hw()
1922 par->clock[3] = 220000; in savage_init_hw()
1937 par->MCLK = ((1431818 * (m+2)) / (n1+2) / (1 << n2) + 50) / 100; in savage_init_hw()
1939 par->MCLK); in savage_init_hw()
1944 if (par->chip == S3_SAVAGE4) { in savage_init_hw()
1957 if ((S3_SAVAGE_MOBILE_SERIES(par->chip) || in savage_init_hw()
1958 S3_MOBILE_TWISTER_SERIES(par->chip)) && !par->crtonly) in savage_init_hw()
1959 par->display_type = DISP_LCD; in savage_init_hw()
1960 else if (dvi || (par->chip == S3_SAVAGE4 && par->dvi)) in savage_init_hw()
1961 par->display_type = DISP_DFP; in savage_init_hw()
1963 par->display_type = DISP_CRT; in savage_init_hw()
1967 if (par->display_type == DISP_LCD) { in savage_init_hw()
2016 par->SavagePanelWidth = panelX; in savage_init_hw()
2017 par->SavagePanelHeight = panelY; in savage_init_hw()
2020 par->display_type = DISP_CRT; in savage_init_hw()
2023 savage_get_default_par(par, &par->state); in savage_init_hw()
2024 par->save = par->state; in savage_init_hw()
2026 if (S3_SAVAGE4_SERIES(par->chip)) { in savage_init_hw()
2031 par->cob_index = 2; in savage_init_hw()
2032 par->cob_size = 0x8000 << par->cob_index; in savage_init_hw()
2033 par->cob_offset = videoRambytes; in savage_init_hw()
2037 par->cob_index = 7; in savage_init_hw()
2038 par->cob_size = 0x400 << par->cob_index; in savage_init_hw()
2039 par->cob_offset = videoRambytes - par->cob_size; in savage_init_hw()
2048 struct savagefb_par *par = info->par; in savage_init_fb_info()
2051 par->pcidev = dev; in savage_init_fb_info()
2053 info->fix.type = FB_TYPE_PACKED_PIXELS; in savage_init_fb_info()
2054 info->fix.type_aux = 0; in savage_init_fb_info()
2055 info->fix.ypanstep = 1; in savage_init_fb_info()
2056 info->fix.ywrapstep = 0; in savage_init_fb_info()
2057 info->fix.accel = id->driver_data; in savage_init_fb_info()
2059 switch (info->fix.accel) { in savage_init_fb_info()
2061 par->chip = S3_SUPERSAVAGE; in savage_init_fb_info()
2062 snprintf(info->fix.id, 16, "SuperSavage"); in savage_init_fb_info()
2065 par->chip = S3_SAVAGE4; in savage_init_fb_info()
2066 snprintf(info->fix.id, 16, "Savage4"); in savage_init_fb_info()
2069 par->chip = S3_SAVAGE3D; in savage_init_fb_info()
2070 snprintf(info->fix.id, 16, "Savage3D"); in savage_init_fb_info()
2073 par->chip = S3_SAVAGE3D; in savage_init_fb_info()
2074 snprintf(info->fix.id, 16, "Savage3D-MV"); in savage_init_fb_info()
2077 par->chip = S3_SAVAGE2000; in savage_init_fb_info()
2078 snprintf(info->fix.id, 16, "Savage2000"); in savage_init_fb_info()
2081 par->chip = S3_SAVAGE_MX; in savage_init_fb_info()
2082 snprintf(info->fix.id, 16, "Savage/MX-MV"); in savage_init_fb_info()
2085 par->chip = S3_SAVAGE_MX; in savage_init_fb_info()
2086 snprintf(info->fix.id, 16, "Savage/MX"); in savage_init_fb_info()
2089 par->chip = S3_SAVAGE_MX; in savage_init_fb_info()
2090 snprintf(info->fix.id, 16, "Savage/IX-MV"); in savage_init_fb_info()
2093 par->chip = S3_SAVAGE_MX; in savage_init_fb_info()
2094 snprintf(info->fix.id, 16, "Savage/IX"); in savage_init_fb_info()
2097 par->chip = S3_PROSAVAGE; in savage_init_fb_info()
2098 snprintf(info->fix.id, 16, "ProSavagePM"); in savage_init_fb_info()
2101 par->chip = S3_PROSAVAGE; in savage_init_fb_info()
2102 snprintf(info->fix.id, 16, "ProSavageKM"); in savage_init_fb_info()
2105 par->chip = S3_TWISTER; in savage_init_fb_info()
2106 snprintf(info->fix.id, 16, "TwisterP"); in savage_init_fb_info()
2109 par->chip = S3_TWISTER; in savage_init_fb_info()
2110 snprintf(info->fix.id, 16, "TwisterK"); in savage_init_fb_info()
2113 par->chip = S3_PROSAVAGEDDR; in savage_init_fb_info()
2114 snprintf(info->fix.id, 16, "ProSavageDDR"); in savage_init_fb_info()
2117 par->chip = S3_PROSAVAGEDDR; in savage_init_fb_info()
2118 snprintf(info->fix.id, 16, "ProSavage8"); in savage_init_fb_info()
2122 if (S3_SAVAGE3D_SERIES(par->chip)) { in savage_init_fb_info()
2123 par->SavageWaitIdle = savage3D_waitidle; in savage_init_fb_info()
2124 par->SavageWaitFifo = savage3D_waitfifo; in savage_init_fb_info()
2125 } else if (S3_SAVAGE4_SERIES(par->chip) || in savage_init_fb_info()
2126 S3_SUPERSAVAGE == par->chip) { in savage_init_fb_info()
2127 par->SavageWaitIdle = savage4_waitidle; in savage_init_fb_info()
2128 par->SavageWaitFifo = savage4_waitfifo; in savage_init_fb_info()
2130 par->SavageWaitIdle = savage2000_waitidle; in savage_init_fb_info()
2131 par->SavageWaitFifo = savage2000_waitfifo; in savage_init_fb_info()
2134 info->var.nonstd = 0; in savage_init_fb_info()
2135 info->var.activate = FB_ACTIVATE_NOW; in savage_init_fb_info()
2136 info->var.width = -1; in savage_init_fb_info()
2137 info->var.height = -1; in savage_init_fb_info()
2138 info->var.accel_flags = 0; in savage_init_fb_info()
2140 info->fbops = &savagefb_ops; in savage_init_fb_info()
2141 info->flags = FBINFO_HWACCEL_YPAN | in savage_init_fb_info()
2144 info->pseudo_palette = par->pseudo_palette; in savage_init_fb_info()
2148 info->pixmap.addr = kcalloc(8, 1024, GFP_KERNEL); in savage_init_fb_info()
2150 err = -ENOMEM; in savage_init_fb_info()
2151 if (info->pixmap.addr) { in savage_init_fb_info()
2152 info->pixmap.size = 8*1024; in savage_init_fb_info()
2153 info->pixmap.scan_align = 4; in savage_init_fb_info()
2154 info->pixmap.buf_align = 4; in savage_init_fb_info()
2155 info->pixmap.access_align = 32; in savage_init_fb_info()
2157 err = fb_alloc_cmap(&info->cmap, NR_PALETTE, 0); in savage_init_fb_info()
2159 info->flags |= FBINFO_HWACCEL_COPYAREA | in savage_init_fb_info()
2163 kfree(info->pixmap.addr); in savage_init_fb_info()
2169 /* --------------------------------------------------------------------- */
2186 info = framebuffer_alloc(sizeof(struct savagefb_par), &dev->dev); in savagefb_probe()
2188 return -ENOMEM; in savagefb_probe()
2189 par = info->par; in savagefb_probe()
2190 mutex_init(&par->open_lock); in savagefb_probe()
2200 err = -ENOMEM; in savagefb_probe()
2220 INIT_LIST_HEAD(&info->modelist); in savagefb_probe()
2224 fb_edid_to_monspecs(edid, &info->monspecs); in savagefb_probe()
2226 fb_videomode_to_modelist(info->monspecs.modedb, in savagefb_probe()
2227 info->monspecs.modedb_len, in savagefb_probe()
2228 &info->modelist); in savagefb_probe()
2230 info->var = savagefb_var800x600x8; in savagefb_probe()
2232 if (par->SavagePanelWidth) { in savagefb_probe()
2236 cvt_mode.xres = par->SavagePanelWidth; in savagefb_probe()
2237 cvt_mode.yres = par->SavagePanelHeight; in savagefb_probe()
2243 else if (fb_find_mode(&info->var, info, NULL, NULL, 0, in savagefb_probe()
2245 info->var = savagefb_var800x600x8; in savagefb_probe()
2249 fb_find_mode(&info->var, info, mode_option, in savagefb_probe()
2250 info->monspecs.modedb, info->monspecs.modedb_len, in savagefb_probe()
2252 } else if (info->monspecs.modedb != NULL) { in savagefb_probe()
2255 mode = fb_find_best_display(&info->monspecs, &info->modelist); in savagefb_probe()
2256 savage_update_var(&info->var, mode); in savagefb_probe()
2260 lpitch = info->var.xres_virtual*((info->var.bits_per_pixel + 7) >> 3); in savagefb_probe()
2261 info->var.yres_virtual = info->fix.smem_len/lpitch; in savagefb_probe()
2263 if (info->var.yres_virtual < info->var.yres) { in savagefb_probe()
2264 err = -ENOMEM; in savagefb_probe()
2273 if (info->var.yres_virtual > 0x1000) in savagefb_probe()
2274 info->var.yres_virtual = 0x1000; in savagefb_probe()
2276 if (info->var.xres_virtual > 0x1000) in savagefb_probe()
2277 info->var.xres_virtual = 0x1000; in savagefb_probe()
2279 err = savagefb_check_var(&info->var, info); in savagefb_probe()
2288 * the precision and fit the results into 32-bit registers. in savagefb_probe()
2291 h_sync = 1953125000 / info->var.pixclock; in savagefb_probe()
2292 h_sync = h_sync * 512 / (info->var.xres + info->var.left_margin + in savagefb_probe()
2293 info->var.right_margin + in savagefb_probe()
2294 info->var.hsync_len); in savagefb_probe()
2295 v_sync = h_sync / (info->var.yres + info->var.upper_margin + in savagefb_probe()
2296 info->var.lower_margin + info->var.vsync_len); in savagefb_probe()
2300 info->fix.smem_len >> 10, in savagefb_probe()
2301 info->var.xres, info->var.yres, in savagefb_probe()
2305 fb_destroy_modedb(info->monspecs.modedb); in savagefb_probe()
2306 info->monspecs.modedb = NULL; in savagefb_probe()
2313 info->fix.id); in savagefb_probe()
2326 fb_alloc_cmap(&info->cmap, 0, 0); in savagefb_probe()
2331 kfree(info->pixmap.addr); in savagefb_probe()
2352 fb_alloc_cmap(&info->cmap, 0, 0); in savagefb_remove()
2355 kfree(info->pixmap.addr); in savagefb_remove()
2364 struct savagefb_par *par = info->par; in savagefb_suspend_late()
2370 par->pm_state = mesg.event; in savagefb_suspend_late()
2371 dev->power.power_state = mesg; in savagefb_suspend_late()
2383 if (info->fbops->fb_sync) in savagefb_suspend_late()
2384 info->fbops->fb_sync(info); in savagefb_suspend_late()
2387 savage_set_default_par(par, &par->save); in savagefb_suspend_late()
2412 struct savagefb_par *par = info->par; in savagefb_resume()
2413 int cur_state = par->pm_state; in savagefb_resume()
2417 par->pm_state = PM_EVENT_ON; in savagefb_resume()
2532 /* **************************** exit-time only **************************** */
2541 /* ************************* init in-kernel code ************************** */
2565 return -ENODEV; in savagefb_init()
2568 return -ENODEV; in savagefb_init()