Lines Matching +full:1 +full:- +full:1024
3 * Copyright 1996-1997 David J. McKay
25 * GPL licensing note -- nVidia is allowing a liberal interpretation of
28 * from this source. -- Jeff Garzik <[email protected]>, 01/Nov/99
48 return (VGA_RD08(par->riva.PVIO, 0x3cc)); in MISCin()
54 volatile U032 __iomem *PRAMDAC = par->riva.PRAMDAC0; in riva_is_connected()
66 mdelay(1); in riva_is_connected()
67 NV_WR32(PRAMDAC, 0x052C, NV_RD32(PRAMDAC, 0x052C) | 1); in riva_is_connected()
69 NV_WR32(par->riva.PRAMDAC0, 0x0610, 0x94050140); in riva_is_connected()
70 NV_WR32(par->riva.PRAMDAC0, 0x0608, 0x00001000); in riva_is_connected()
72 mdelay(1); in riva_is_connected()
74 present = (NV_RD32(PRAMDAC, 0x0608) & (1 << 28)) ? TRUE : FALSE; in riva_is_connected()
76 NV_WR32(par->riva.PRAMDAC0, 0x0608, in riva_is_connected()
77 NV_RD32(par->riva.PRAMDAC0, 0x0608) & 0x0000EFFF); in riva_is_connected()
90 par->SecondCRTC ? 1 : 0); in riva_override_CRTC()
92 if(par->forceCRTC != -1) { in riva_override_CRTC()
94 "Forcing usage of CRTC %i\n", par->forceCRTC); in riva_override_CRTC()
95 par->SecondCRTC = par->forceCRTC; in riva_override_CRTC()
102 if (par->FlatPanel == 1) { in riva_is_second()
103 switch(par->Chipset & 0xffff) { in riva_is_second()
130 par->SecondCRTC = TRUE; in riva_is_second()
133 par->SecondCRTC = FALSE; in riva_is_second()
139 if (NV_RD32(par->riva.PRAMDAC0, 0x0000052C) & 0x100) in riva_is_second()
140 par->SecondCRTC = TRUE; in riva_is_second()
142 par->SecondCRTC = FALSE; in riva_is_second()
144 if (riva_is_connected(par, 1)) { in riva_is_second()
145 if(NV_RD32(par->riva.PRAMDAC0, 0x0000252C) & 0x100) in riva_is_second()
146 par->SecondCRTC = TRUE; in riva_is_second()
148 par->SecondCRTC = FALSE; in riva_is_second()
150 par->SecondCRTC = FALSE; in riva_is_second()
157 RIVA_HW_INST *chip = &par->riva; in riva_get_memlen()
159 unsigned int chipset = par->Chipset; in riva_get_memlen()
162 int domain = pci_domain_nr(par->pdev->bus); in riva_get_memlen()
164 switch (chip->Architecture) { in riva_get_memlen()
166 if (NV_RD32(chip->PFB, 0x00000000) & 0x00000020) { in riva_get_memlen()
167 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20) in riva_get_memlen()
168 && ((NV_RD32(chip->PMC, 0x00000000)&0x0F)>=0x02)) { in riva_get_memlen()
172 switch (NV_RD32(chip->PFB,0x00000000) & 0x03) { in riva_get_memlen()
174 memlen = 1024 * 4; in riva_get_memlen()
176 case 1: in riva_get_memlen()
177 memlen = 1024 * 2; in riva_get_memlen()
180 memlen = 1024 * 8; in riva_get_memlen()
184 memlen = 1024 * 8; in riva_get_memlen()
190 switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) { in riva_get_memlen()
192 memlen = 1024 * 8; in riva_get_memlen()
195 memlen = 1024 * 4; in riva_get_memlen()
198 memlen = 1024 * 2; in riva_get_memlen()
204 if (NV_RD32(chip->PFB, 0x00000000) & 0x00000100) { in riva_get_memlen()
205 memlen = ((NV_RD32(chip->PFB, 0x00000000)>>12)&0x0F) * in riva_get_memlen()
206 1024 * 2 + 1024 * 2; in riva_get_memlen()
208 switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) { in riva_get_memlen()
210 memlen = 1024 * 32; in riva_get_memlen()
212 case 1: in riva_get_memlen()
213 memlen = 1024 * 4; in riva_get_memlen()
216 memlen = 1024 * 8; in riva_get_memlen()
220 memlen = 1024 * 16; in riva_get_memlen()
230 dev = pci_get_domain_bus_and_slot(domain, 0, 1); in riva_get_memlen()
233 memlen = (((amt >> 6) & 31) + 1) * 1024; in riva_get_memlen()
235 dev = pci_get_domain_bus_and_slot(domain, 0, 1); in riva_get_memlen()
238 memlen = (((amt >> 4) & 127) + 1) * 1024; in riva_get_memlen()
240 switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) & in riva_get_memlen()
243 memlen = 1024 * 2; in riva_get_memlen()
246 memlen = 1024 * 4; in riva_get_memlen()
249 memlen = 1024 * 8; in riva_get_memlen()
252 memlen = 1024 * 16; in riva_get_memlen()
255 memlen = 1024 * 32; in riva_get_memlen()
258 memlen = 1024 * 64; in riva_get_memlen()
261 memlen = 1024 * 128; in riva_get_memlen()
264 memlen = 1024 * 16; in riva_get_memlen()
275 RIVA_HW_INST *chip = &par->riva; in riva_get_maxdclk()
278 switch (chip->Architecture) { in riva_get_maxdclk()
280 if (NV_RD32(chip->PFB, 0x00000000) & 0x00000020) { in riva_get_maxdclk()
281 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20) in riva_get_maxdclk()
282 && ((NV_RD32(chip->PMC,0x00000000)&0x0F) >= 0x02)) { in riva_get_maxdclk()
301 switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003) { in riva_get_maxdclk()
317 par->riva.EnableIRQ = 0; in riva_common_setup()
318 par->riva.PRAMDAC0 = in riva_common_setup()
319 (volatile U032 __iomem *)(par->ctrl_base + 0x00680000); in riva_common_setup()
320 par->riva.PFB = in riva_common_setup()
321 (volatile U032 __iomem *)(par->ctrl_base + 0x00100000); in riva_common_setup()
322 par->riva.PFIFO = in riva_common_setup()
323 (volatile U032 __iomem *)(par->ctrl_base + 0x00002000); in riva_common_setup()
324 par->riva.PGRAPH = in riva_common_setup()
325 (volatile U032 __iomem *)(par->ctrl_base + 0x00400000); in riva_common_setup()
326 par->riva.PEXTDEV = in riva_common_setup()
327 (volatile U032 __iomem *)(par->ctrl_base + 0x00101000); in riva_common_setup()
328 par->riva.PTIMER = in riva_common_setup()
329 (volatile U032 __iomem *)(par->ctrl_base + 0x00009000); in riva_common_setup()
330 par->riva.PMC = in riva_common_setup()
331 (volatile U032 __iomem *)(par->ctrl_base + 0x00000000); in riva_common_setup()
332 par->riva.FIFO = in riva_common_setup()
333 (volatile U032 __iomem *)(par->ctrl_base + 0x00800000); in riva_common_setup()
334 par->riva.PCIO0 = par->ctrl_base + 0x00601000; in riva_common_setup()
335 par->riva.PDIO0 = par->ctrl_base + 0x00681000; in riva_common_setup()
336 par->riva.PVIO = par->ctrl_base + 0x000C0000; in riva_common_setup()
338 par->riva.IO = (MISCin(par) & 0x01) ? 0x3D0 : 0x3B0; in riva_common_setup()
340 if (par->FlatPanel == -1) { in riva_common_setup()
341 switch (par->Chipset & 0xffff) { in riva_common_setup()
370 par->FlatPanel = 1; in riva_common_setup()
377 switch (par->Chipset & 0x0ff0) { in riva_common_setup()
379 if (par->Chipset == NV_CHIP_GEFORCE2_GO) in riva_common_setup()
380 par->SecondCRTC = TRUE; in riva_common_setup()
382 if (par->FlatPanel == 1) in riva_common_setup()
383 par->SecondCRTC = TRUE; in riva_common_setup()
403 if (par->SecondCRTC) { in riva_common_setup()
404 par->riva.PCIO = par->riva.PCIO0 + 0x2000; in riva_common_setup()
405 par->riva.PCRTC = par->riva.PCRTC0 + 0x800; in riva_common_setup()
406 par->riva.PRAMDAC = par->riva.PRAMDAC0 + 0x800; in riva_common_setup()
407 par->riva.PDIO = par->riva.PDIO0 + 0x2000; in riva_common_setup()
409 par->riva.PCIO = par->riva.PCIO0; in riva_common_setup()
410 par->riva.PCRTC = par->riva.PCRTC0; in riva_common_setup()
411 par->riva.PRAMDAC = par->riva.PRAMDAC0; in riva_common_setup()
412 par->riva.PDIO = par->riva.PDIO0; in riva_common_setup()
415 if (par->FlatPanel == -1) { in riva_common_setup()
417 par->FlatPanel = 0; in riva_common_setup()
419 par->riva.flatPanel = (par->FlatPanel > 0) ? TRUE : FALSE; in riva_common_setup()
421 RivaGetConfig(&par->riva, par->pdev, par->Chipset); in riva_common_setup()