Lines Matching +full:irq +full:- +full:mirror
1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/dma-mapping.h>
104 int irq; member
112 /* maps which plane is using a fifo. fifo-id -> plane-id */
522 r = pm_runtime_resume_and_get(&dispc.pdev->dev); in dispc_runtime_get()
535 r = pm_runtime_put_sync(&dispc.pdev->dev); in dispc_runtime_put()
536 WARN_ON(r < 0 && r != -ENOSYS); in dispc_runtime_put()
548 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv) in dispc_mgr_get_framedone_irq()
666 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry)); in dispc_ovl_write_color_conv_coef()
667 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb)); in dispc_ovl_write_color_conv_coef()
668 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr)); in dispc_ovl_write_color_conv_coef()
669 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by)); in dispc_ovl_write_color_conv_coef()
670 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb)); in dispc_ovl_write_color_conv_coef()
672 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11); in dispc_ovl_write_color_conv_coef()
682 /* YUV -> RGB */ in dispc_setup_color_conv_coef()
683 298, 409, 0, 298, -208, -100, 298, 0, 517, 0, in dispc_setup_color_conv_coef()
686 /* RGB -> YUV */ in dispc_setup_color_conv_coef()
687 66, 129, 25, 112, -94, -18, -38, -74, 112, 0, in dispc_setup_color_conv_coef()
693 if (dispc.feat->has_writeback) in dispc_setup_color_conv_coef()
733 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); in dispc_ovl_set_input_size()
748 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); in dispc_ovl_set_output_size()
1021 if (dispc.feat->has_writeback) in dispc_configure_burst_sizes()
1062 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) | in dispc_mgr_set_cpr_coef()
1063 FLD_VAL(coefs->rb, 9, 0); in dispc_mgr_set_cpr_coef()
1064 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) | in dispc_mgr_set_cpr_coef()
1065 FLD_VAL(coefs->gb, 9, 0); in dispc_mgr_set_cpr_coef()
1066 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) | in dispc_mgr_set_cpr_coef()
1067 FLD_VAL(coefs->bb, 9, 0); in dispc_mgr_set_cpr_coef()
1103 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) | in dispc_mgr_set_size()
1104 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0); in dispc_mgr_set_size()
1121 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) { in dispc_init_fifos()
1140 if (dispc.feat->gfx_fifo_workaround) { in dispc_init_fifos()
1170 if (dispc.feat->has_writeback) { in dispc_init_fifos()
1187 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) { in dispc_ovl_get_fifo_size()
1228 if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload && in dispc_ovl_set_fifo_threshold()
1258 * We use the same low threshold for both fifomerge and non-fifomerge in dispc_ovl_compute_fifo_thresholds()
1264 *fifo_low = ovl_fifo_size - burst_size * 2; in dispc_ovl_compute_fifo_thresholds()
1265 *fifo_high = total_fifo_size - burst_size; in dispc_ovl_compute_fifo_thresholds()
1275 *fifo_low = ovl_fifo_size - burst_size; in dispc_ovl_compute_fifo_thresholds()
1276 *fifo_high = total_fifo_size - buf_unit; in dispc_ovl_compute_fifo_thresholds()
1311 * As a work-around, set force MFLAG to always on. in dispc_init_mflag()
1336 if (dispc.feat->has_writeback) { in dispc_init_mflag()
1461 { 0, 1, 0, 1 , -1, 2, 0, 1 }, in dispc_ovl_set_accu_uv()
1462 { 1, 2, -3, 4 , 0, 1, 0, 1 }, in dispc_ovl_set_accu_uv()
1463 { -1, 1, 0, 1 , -1, 2, 0, 1 }, in dispc_ovl_set_accu_uv()
1464 { -1, 2, -1, 2 , -1, 1, 0, 1 }, in dispc_ovl_set_accu_uv()
1468 { 0, 1, 0, 1 , -3, 4, -1, 4 }, in dispc_ovl_set_accu_uv()
1469 { -1, 4, -3, 4 , 0, 1, 0, 1 }, in dispc_ovl_set_accu_uv()
1470 { -1, 1, 0, 1 , -1, 4, -3, 4 }, in dispc_ovl_set_accu_uv()
1471 { -3, 4, -3, 4 , -1, 1, 0, 1 }, in dispc_ovl_set_accu_uv()
1477 { -1, 1, 0, 1, 0, 1, 0, 1 }, in dispc_ovl_set_accu_uv()
1478 { 0, 1, 0, 1, -1, 1, 0, 1 }, in dispc_ovl_set_accu_uv()
1520 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024; in dispc_ovl_set_accu_uv()
1521 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024; in dispc_ovl_set_accu_uv()
1522 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024; in dispc_ovl_set_accu_uv()
1523 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024; in dispc_ovl_set_accu_uv()
1575 accu0 -= accu1; in dispc_ovl_set_scaling_common()
1799 return 1 + (pixels - 1) * ps; in pixinc()
1801 return 1 - (-pixels + 1) * ps; in pixinc()
1807 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror, in calc_vrfb_rotation_offset() argument
1841 switch (rotation + mirror * 4) { in calc_vrfb_rotation_offset()
1861 (y_predecim * screen_width - x_predecim * width) + in calc_vrfb_rotation_offset()
1882 *row_inc = pixinc(1 - in calc_vrfb_rotation_offset()
1883 (y_predecim * screen_width + x_predecim * width) - in calc_vrfb_rotation_offset()
1894 static void calc_dma_rotation_offset(u8 rotation, bool mirror, in calc_dma_rotation_offset() argument
1935 switch (rotation + mirror * 4) { in calc_dma_rotation_offset()
1943 (y_predecim * screen_width - fbw * x_predecim) + in calc_dma_rotation_offset()
1952 *offset1 = screen_width * (fbh - 1) * ps; in calc_dma_rotation_offset()
1957 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) + in calc_dma_rotation_offset()
1959 *pix_inc = pixinc(-x_predecim * screen_width, ps); in calc_dma_rotation_offset()
1962 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps; in calc_dma_rotation_offset()
1964 *offset0 = *offset1 - field_offset * screen_width * ps; in calc_dma_rotation_offset()
1967 *row_inc = pixinc(-1 - in calc_dma_rotation_offset()
1968 (y_predecim * screen_width - fbw * x_predecim) - in calc_dma_rotation_offset()
1972 *pix_inc = pixinc(-x_predecim, 2 * ps); in calc_dma_rotation_offset()
1974 *pix_inc = pixinc(-x_predecim, ps); in calc_dma_rotation_offset()
1977 *offset1 = (fbw - 1) * ps; in calc_dma_rotation_offset()
1979 *offset0 = *offset1 - field_offset * ps; in calc_dma_rotation_offset()
1982 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) - in calc_dma_rotation_offset()
1983 y_predecim - (fieldmode ? 1 : 0), ps); in calc_dma_rotation_offset()
1989 *offset1 = (fbw - 1) * ps; in calc_dma_rotation_offset()
1994 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 + in calc_dma_rotation_offset()
1999 *pix_inc = pixinc(-x_predecim, 2 * ps); in calc_dma_rotation_offset()
2001 *pix_inc = pixinc(-x_predecim, ps); in calc_dma_rotation_offset()
2010 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) + in calc_dma_rotation_offset()
2017 *offset1 = screen_width * (fbh - 1) * ps; in calc_dma_rotation_offset()
2019 *offset0 = *offset1 - field_offset * screen_width * ps; in calc_dma_rotation_offset()
2022 *row_inc = pixinc(1 - y_predecim * screen_width * 2 - in calc_dma_rotation_offset()
2033 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps; in calc_dma_rotation_offset()
2035 *offset0 = *offset1 - field_offset * ps; in calc_dma_rotation_offset()
2038 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) - in calc_dma_rotation_offset()
2039 y_predecim - (fieldmode ? 1 : 0), in calc_dma_rotation_offset()
2041 *pix_inc = pixinc(-x_predecim * screen_width, ps); in calc_dma_rotation_offset()
2080 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) + in calc_tiler_rotation_offset()
2104 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width; in check_horiz_timing_omap3()
2111 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk); in check_horiz_timing_omap3()
2114 return -EINVAL; in check_horiz_timing_omap3()
2116 /* FIXME add checks for 3-tap filter once the limitations are known */ in check_horiz_timing_omap3()
2122 * So, atleast DS-2 lines must have already been fetched by DISPC in check_horiz_timing_omap3()
2123 * during nonactive - pos_x period. in check_horiz_timing_omap3()
2125 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk); in check_horiz_timing_omap3()
2126 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n", in check_horiz_timing_omap3()
2127 val, max(0, ds - 2) * width); in check_horiz_timing_omap3()
2128 if (val < max(0, ds - 2) * width) in check_horiz_timing_omap3()
2129 return -EINVAL; in check_horiz_timing_omap3()
2134 * DS - 1 lines should be loaded during nonactive period. in check_horiz_timing_omap3()
2137 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n", in check_horiz_timing_omap3()
2138 val, max(0, ds - 1) * width); in check_horiz_timing_omap3()
2139 if (val < max(0, ds - 1) * width) in check_horiz_timing_omap3()
2140 return -EINVAL; in check_horiz_timing_omap3()
2157 unsigned int ppl = mgr_timings->x_res; in calc_core_clk_five_taps()
2167 tmp = (u64)pclk * (height - 2 * out_height) * out_width; in calc_core_clk_five_taps()
2168 do_div(tmp, 2 * out_height * (ppl - out_width)); in calc_core_clk_five_taps()
2256 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in dispc_ovl_calc_scaling_24xx()
2274 return -EINVAL; in dispc_ovl_calc_scaling_24xx()
2279 return -EINVAL; in dispc_ovl_calc_scaling_24xx()
2311 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in dispc_ovl_calc_scaling_34xx()
2347 return -EINVAL; in dispc_ovl_calc_scaling_34xx()
2353 return -EINVAL; in dispc_ovl_calc_scaling_34xx()
2359 return -EINVAL; in dispc_ovl_calc_scaling_34xx()
2364 return -EINVAL; in dispc_ovl_calc_scaling_34xx()
2394 return -EINVAL; in dispc_ovl_calc_scaling_44xx()
2403 return -EINVAL; in dispc_ovl_calc_scaling_44xx()
2406 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height, in dispc_ovl_calc_scaling_44xx()
2412 ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100))
2430 if (!mem_to_mem && (pclk == 0 || mgr_timings->pixelclock == 0)) { in dispc_ovl_calc_scaling()
2432 return -EINVAL; in dispc_ovl_calc_scaling()
2436 return -EINVAL; in dispc_ovl_calc_scaling()
2461 return -EINVAL; in dispc_ovl_calc_scaling()
2464 return -EINVAL; in dispc_ovl_calc_scaling()
2466 ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height, in dispc_ovl_calc_scaling()
2473 …DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req cl… in dispc_ovl_calc_scaling()
2492 return -EINVAL; in dispc_ovl_calc_scaling()
2508 u16 in_height = oi->height; in dispc_ovl_check()
2509 u16 in_width = oi->width; in dispc_ovl_check()
2510 bool ilace = timings->interlace; in dispc_ovl_check()
2512 int pos_x = oi->pos_x; in dispc_ovl_check()
2516 out_width = oi->out_width == 0 ? oi->width : oi->out_width; in dispc_ovl_check()
2517 out_height = oi->out_height == 0 ? oi->height : oi->out_height; in dispc_ovl_check()
2519 if (ilace && oi->height == out_height) in dispc_ovl_check()
2531 if (!dss_feat_color_mode_supported(plane, oi->color_mode)) in dispc_ovl_check()
2532 return -EINVAL; in dispc_ovl_check()
2535 in_height, out_width, out_height, oi->color_mode, in dispc_ovl_check()
2537 oi->rotation_type, false); in dispc_ovl_check()
2545 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha, in dispc_ovl_setup_common() argument
2561 bool ilace = mgr_timings->interlace; in dispc_ovl_setup_common()
2566 return -EINVAL; in dispc_ovl_setup_common()
2575 return -EINVAL; in dispc_ovl_setup_common()
2601 return -EINVAL; in dispc_ovl_setup_common()
2623 DSSDBG("adjusting input width %d -> %d\n", in dispc_ovl_setup_common()
2676 calc_dma_rotation_offset(rotation, mirror, screen_width, in dispc_ovl_setup_common()
2682 calc_vrfb_rotation_offset(rotation, mirror, in dispc_ovl_setup_common()
2703 if (dispc.feat->last_pixel_inc_missing) in dispc_ovl_setup_common()
2704 row_inc += pix_inc - 1; in dispc_ovl_setup_common()
2709 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width, in dispc_ovl_setup_common()
2724 dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror, in dispc_ovl_setup_common()
2745 return -EINVAL; in dispc_ovl_setup()
2750 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->" in dispc_ovl_setup()
2752 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x, in dispc_ovl_setup()
2753 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height, in dispc_ovl_setup()
2754 oi->color_mode, oi->rotation, oi->mirror, channel, replication); in dispc_ovl_setup()
2756 r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr, in dispc_ovl_setup()
2757 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height, in dispc_ovl_setup()
2758 oi->out_width, oi->out_height, oi->color_mode, oi->rotation, in dispc_ovl_setup()
2759 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha, in dispc_ovl_setup()
2760 oi->rotation_type, replication, mgr_timings, mem_to_mem); in dispc_ovl_setup()
2871 dispc_mgr_set_default_color(channel, info->default_color); in dispc_mgr_setup()
2872 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key); in dispc_mgr_setup()
2873 dispc_mgr_enable_trans_key(channel, info->trans_enabled); in dispc_mgr_setup()
2875 info->partial_alpha_enabled); in dispc_mgr_setup()
2877 dispc_mgr_enable_cpr(channel, info->cpr_enable); in dispc_mgr_setup()
2878 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs); in dispc_mgr_setup()
2945 dispc_mgr_set_io_pad_mode(config->io_pad_mode); in dispc_mgr_set_lcd_config()
2947 dispc_mgr_enable_stallmode(channel, config->stallmode); in dispc_mgr_set_lcd_config()
2948 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck); in dispc_mgr_set_lcd_config()
2950 dispc_mgr_set_clock_div(channel, &config->clock_info); in dispc_mgr_set_lcd_config()
2952 dispc_mgr_set_tft_data_lines(channel, config->video_port_width); in dispc_mgr_set_lcd_config()
2954 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity); in dispc_mgr_set_lcd_config()
2962 return width <= dispc.feat->mgr_width_max && in _dispc_mgr_size_ok()
2963 height <= dispc.feat->mgr_height_max; in _dispc_mgr_size_ok()
2969 if (hsw < 1 || hsw > dispc.feat->sw_max || in _dispc_lcd_timings_ok()
2970 hfp < 1 || hfp > dispc.feat->hp_max || in _dispc_lcd_timings_ok()
2971 hbp < 1 || hbp > dispc.feat->hp_max || in _dispc_lcd_timings_ok()
2972 vsw < 1 || vsw > dispc.feat->sw_max || in _dispc_lcd_timings_ok()
2973 vfp < 0 || vfp > dispc.feat->vp_max || in _dispc_lcd_timings_ok()
2974 vbp < 0 || vbp > dispc.feat->vp_max) in _dispc_lcd_timings_ok()
2983 return pclk <= dispc.feat->max_lcd_pclk; in _dispc_mgr_pclk_ok()
2985 return pclk <= dispc.feat->max_tv_pclk; in _dispc_mgr_pclk_ok()
2991 if (!_dispc_mgr_size_ok(timings->x_res, timings->y_res)) in dispc_mgr_timings_ok()
2994 if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock)) in dispc_mgr_timings_ok()
2999 if (timings->interlace) in dispc_mgr_timings_ok()
3002 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp, in dispc_mgr_timings_ok()
3003 timings->hbp, timings->vsw, timings->vfp, in dispc_mgr_timings_ok()
3004 timings->vbp)) in dispc_mgr_timings_ok()
3023 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) | in _dispc_mgr_set_lcd_timings()
3024 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) | in _dispc_mgr_set_lcd_timings()
3025 FLD_VAL(hbp-1, dispc.feat->bp_start, 20); in _dispc_mgr_set_lcd_timings()
3026 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) | in _dispc_mgr_set_lcd_timings()
3027 FLD_VAL(vfp, dispc.feat->fp_start, 8) | in _dispc_mgr_set_lcd_timings()
3028 FLD_VAL(vbp, dispc.feat->bp_start, 20); in _dispc_mgr_set_lcd_timings()
3099 if (dispc.feat->supports_sync_align) in _dispc_mgr_set_lcd_timings()
3147 ht = timings->pixelclock / xtot; in dispc_mgr_set_timings()
3148 vt = timings->pixelclock / xtot / ytot; in dispc_mgr_set_timings()
3150 DSSDBG("pck %u\n", timings->pixelclock); in dispc_mgr_set_timings()
3204 r = pll->cinfo.clkout[0]; in dispc_fclk_rate()
3211 r = pll->cinfo.clkout[0]; in dispc_fclk_rate()
3242 r = pll->cinfo.clkout[0]; in dispc_mgr_lclk_rate()
3249 r = pll->cinfo.clkout[0]; in dispc_mgr_lclk_rate()
3321 seq_printf(s, "- %s -\n", mgr_desc[channel].name); in dispc_dump_clocks_channel()
3331 seq_printf(s, "lck\t\t%-16lulck div\t%u\n", in dispc_dump_clocks_channel()
3333 seq_printf(s, "pck\t\t%-16lupck div\t%u\n", in dispc_dump_clocks_channel()
3346 seq_printf(s, "- DISPC -\n"); in dispc_dump_clocks()
3352 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate()); in dispc_dump_clocks()
3355 seq_printf(s, "- DISPC-CORE-CLK -\n"); in dispc_dump_clocks()
3359 seq_printf(s, "lck\t\t%-16lulck div\t%u\n", in dispc_dump_clocks()
3391 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r)) in dispc_dump_regs()
3425 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \ in dispc_dump_regs()
3494 if (dispc.feat->has_writeback) { in dispc_dump_regs()
3529 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \ in dispc_dump_regs()
3572 if (cinfo->lck_div > 255 || cinfo->lck_div == 0) in dispc_calc_clock_rates()
3573 return -EINVAL; in dispc_calc_clock_rates()
3574 if (cinfo->pck_div < 1 || cinfo->pck_div > 255) in dispc_calc_clock_rates()
3575 return -EINVAL; in dispc_calc_clock_rates()
3577 cinfo->lck = dispc_fclk_rate / cinfo->lck_div; in dispc_calc_clock_rates()
3578 cinfo->pck = cinfo->lck / cinfo->pck_div; in dispc_calc_clock_rates()
3646 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div); in dispc_mgr_set_clock_div()
3647 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div); in dispc_mgr_set_clock_div()
3649 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div); in dispc_mgr_set_clock_div()
3720 if (dispc.feat->mstandby_workaround) in _omap_dispc_initial_config()
3863 static irqreturn_t dispc_irq_handler(int irq, void *arg) in dispc_irq_handler() argument
3868 return dispc.user_handler(irq, dispc.user_data); in dispc_irq_handler()
3876 return -EBUSY; in dispc_request_irq()
3884 r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler, in dispc_request_irq()
3897 devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc); in dispc_free_irq()
3911 struct device_node *np = pdev->dev.of_node; in dispc_bind()
3919 return -ENODEV; in dispc_bind()
3924 return -EINVAL; in dispc_bind()
3927 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start, in dispc_bind()
3931 return -ENOMEM; in dispc_bind()
3934 dispc.irq = platform_get_irq(dispc.pdev, 0); in dispc_bind()
3935 if (dispc.irq < 0) { in dispc_bind()
3937 return -ENODEV; in dispc_bind()
3940 if (np && of_property_present(np, "syscon-pol")) { in dispc_bind()
3941 dispc.syscon_pol = syscon_regmap_lookup_by_phandle_args(np, "syscon-pol", in dispc_bind()
3944 dev_err(&pdev->dev, "failed to get syscon-pol regmap\n"); in dispc_bind()
3949 pm_runtime_enable(&pdev->dev); in dispc_bind()
3958 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n", in dispc_bind()
3970 pm_runtime_disable(&pdev->dev); in dispc_bind()
3989 return component_add(&pdev->dev, &dispc_component_ops); in dispc_probe()
3994 component_del(&pdev->dev, &dispc_component_ops); in dispc_remove()
4003 synchronize_irq(dispc.irq); in dispc_runtime_suspend()
4037 { .compatible = "ti,omap2-dispc", },
4038 { .compatible = "ti,omap3-dispc", },
4039 { .compatible = "ti,omap4-dispc", },
4040 { .compatible = "ti,omap5-dispc", },
4041 { .compatible = "ti,dra7-dispc", },