Lines Matching +full:0 +full:x14011000
37 #define NVTRACE if (0) printk
61 PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0},
62 { 0, }
70 static int hwcur = 0;
71 static int noaccel = 0;
72 static int noscale = 0;
73 static int paneltweak = 0;
74 static int vram = 0;
94 .red = {0, 8, 0},
95 .green = {0, 8, 0},
96 .blue = {0, 8, 0},
97 .transp = {0, 0, 0},
115 int i, j, k = 0; in nvidiafb_load_cursor_image()
120 for (i = 0; i < h; i++) { in nvidiafb_load_cursor_image()
124 for (j = 0; j < w / 2; j++) { in nvidiafb_load_cursor_image()
125 tmp = 0; in nvidiafb_load_cursor_image()
137 NV_WR32(&par->CURSOR[k++], 0, tmp); in nvidiafb_load_cursor_image()
146 NVWriteDacMask(par, 0xff); in nvidia_write_clut()
156 NVWriteDacMask(par, 0xff); in nvidia_read_clut()
166 int tweak = 0; in nvidia_panel_tweak()
177 if (((par->Chipset & 0xffff) == 0x0328) && (state->bpp == 32)) { in nvidia_panel_tweak()
182 if ((par->Chipset & 0xfff0) == 0x0310) in nvidia_panel_tweak()
198 tmp = NVReadSeq(par, 0x01); in nvidia_screen_off()
200 NVWriteSeq(par, 0x00, 0x01); /* Synchronous Reset */ in nvidia_screen_off()
201 NVWriteSeq(par, 0x01, tmp | 0x20); /* disable the display */ in nvidia_screen_off()
207 tmp = NVReadSeq(par, 0x01); in nvidia_screen_off()
209 NVWriteSeq(par, 0x01, tmp & ~0x20); /* reenable display */ in nvidia_screen_off()
210 NVWriteSeq(par, 0x00, 0x03); /* End Reset */ in nvidia_screen_off()
220 NVLockUnlock(par, 0); in nvidia_save_vga()
226 for (i = 0; i < NUM_CRT_REGS; i++) in nvidia_save_vga()
229 for (i = 0; i < NUM_ATC_REGS; i++) in nvidia_save_vga()
232 for (i = 0; i < NUM_GRC_REGS; i++) in nvidia_save_vga()
235 for (i = 0; i < NUM_SEQ_REGS; i++) in nvidia_save_vga()
260 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */ in nvidia_write_regs()
261 NVWriteCrtc(par, 0x11, state->crtc[0x11] & ~0x80); in nvidia_write_regs()
263 for (i = 0; i < NUM_CRT_REGS; i++) { in nvidia_write_regs()
265 case 0x19: in nvidia_write_regs()
266 case 0x20 ... 0x40: in nvidia_write_regs()
276 for (i = 0; i < NUM_GRC_REGS; i++) { in nvidia_write_regs()
283 for (i = 0; i < NUM_ATC_REGS; i++) { in nvidia_write_regs()
331 state->crtc[0x0] = Set8Bits(h_total); in nvidia_calc_regs()
332 state->crtc[0x1] = Set8Bits(h_display); in nvidia_calc_regs()
333 state->crtc[0x2] = Set8Bits(h_blank_s); in nvidia_calc_regs()
334 state->crtc[0x3] = SetBitField(h_blank_e, 4: 0, 4:0) in nvidia_calc_regs()
336 state->crtc[0x4] = Set8Bits(h_start); in nvidia_calc_regs()
337 state->crtc[0x5] = SetBitField(h_blank_e, 5: 5, 7:7) in nvidia_calc_regs()
338 | SetBitField(h_end, 4: 0, 4:0); in nvidia_calc_regs()
339 state->crtc[0x6] = SetBitField(v_total, 7: 0, 7:0); in nvidia_calc_regs()
340 state->crtc[0x7] = SetBitField(v_total, 8: 8, 0:0) in nvidia_calc_regs()
348 state->crtc[0x9] = SetBitField(v_blank_s, 9: 9, 5:5) in nvidia_calc_regs()
350 | ((info->var.vmode & FB_VMODE_DOUBLE) ? 0x80 : 0x00); in nvidia_calc_regs()
351 state->crtc[0x10] = Set8Bits(v_start); in nvidia_calc_regs()
352 state->crtc[0x11] = SetBitField(v_end, 3: 0, 3:0) | SetBit(5); in nvidia_calc_regs()
353 state->crtc[0x12] = Set8Bits(v_display); in nvidia_calc_regs()
354 state->crtc[0x13] = ((info->var.xres_virtual / 8) * in nvidia_calc_regs()
356 state->crtc[0x15] = Set8Bits(v_blank_s); in nvidia_calc_regs()
357 state->crtc[0x16] = Set8Bits(v_blank_e); in nvidia_calc_regs()
359 state->attr[0x10] = 0x01; in nvidia_calc_regs()
362 state->attr[0x11] = 0x00; in nvidia_calc_regs()
368 | SetBitField(v_total, 10: 10, 0:0); in nvidia_calc_regs()
370 state->horiz = SetBitField(h_total, 8: 8, 0:0) in nvidia_calc_regs()
375 state->extra = SetBitField(v_total, 11: 11, 0:0) in nvidia_calc_regs()
385 state->interlace = 0xff; /* interlace off */ in nvidia_calc_regs()
402 state->misc_output &= ~0x40; in nvidia_calc_regs()
404 state->misc_output |= 0x40; in nvidia_calc_regs()
406 state->misc_output &= ~0x80; in nvidia_calc_regs()
408 state->misc_output |= 0x80; in nvidia_calc_regs()
414 state->scale = NV_RD32(par->PRAMDAC, 0x00000848) & 0xfff000ff; in nvidia_calc_regs()
424 state->crtcSync = NV_RD32(par->PRAMDAC, 0x0828); in nvidia_calc_regs()
436 VGA_WR08(par->PCIO, 0x03D4, 0x1C); in nvidia_calc_regs()
437 state->fifo = VGA_RD08(par->PCIO, 0x03D5) & ~(1<<5); in nvidia_calc_regs()
440 state->head = NV_RD32(par->PCRTC0, 0x00000860) & ~0x00001000; in nvidia_calc_regs()
441 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) | 0x00001000; in nvidia_calc_regs()
443 state->pllsel |= 0x20000800; in nvidia_calc_regs()
444 state->vpll = NV_RD32(par->PRAMDAC0, 0x00000508); in nvidia_calc_regs()
446 state->vpllB = NV_RD32(par->PRAMDAC0, 0x00000578); in nvidia_calc_regs()
448 state->head = NV_RD32(par->PCRTC0, 0x00000860) | 0x00001000; in nvidia_calc_regs()
449 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) & ~0x00001000; in nvidia_calc_regs()
450 state->crtcOwner = 0; in nvidia_calc_regs()
451 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520); in nvidia_calc_regs()
453 state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C); in nvidia_calc_regs()
456 state->cursorConfig = 0x00000100; in nvidia_calc_regs()
462 if ((par->Chipset & 0x0ff0) != 0x0110) in nvidia_calc_regs()
463 state->cursorConfig |= 0x04011000; in nvidia_calc_regs()
465 state->cursorConfig |= 0x14011000; in nvidia_calc_regs()
468 state->cursorConfig |= 0x02000000; in nvidia_calc_regs()
471 if ((par->Chipset & 0x0ff0) == 0x0110) { in nvidia_calc_regs()
472 state->dither = NV_RD32(par->PRAMDAC, 0x0528) & in nvidia_calc_regs()
473 ~0x00010000; in nvidia_calc_regs()
475 state->dither |= 0x00010000; in nvidia_calc_regs()
477 state->dither = NV_RD32(par->PRAMDAC, 0x083C) & ~1; in nvidia_calc_regs()
483 state->timingH = 0; in nvidia_calc_regs()
484 state->timingV = 0; in nvidia_calc_regs()
487 return 0; in nvidia_calc_regs()
496 for (i = 0; i < 0x10; i++) in nvidia_init_vga()
498 state->attr[0x10] = 0x41; in nvidia_init_vga()
499 state->attr[0x11] = 0xff; in nvidia_init_vga()
500 state->attr[0x12] = 0x0f; in nvidia_init_vga()
501 state->attr[0x13] = 0x00; in nvidia_init_vga()
502 state->attr[0x14] = 0x00; in nvidia_init_vga()
504 memset(state->crtc, 0x00, NUM_CRT_REGS); in nvidia_init_vga()
505 state->crtc[0x0a] = 0x20; in nvidia_init_vga()
506 state->crtc[0x17] = 0xe3; in nvidia_init_vga()
507 state->crtc[0x18] = 0xff; in nvidia_init_vga()
508 state->crtc[0x28] = 0x40; in nvidia_init_vga()
510 memset(state->gra, 0x00, NUM_GRC_REGS); in nvidia_init_vga()
511 state->gra[0x05] = 0x40; in nvidia_init_vga()
512 state->gra[0x06] = 0x05; in nvidia_init_vga()
513 state->gra[0x07] = 0x0f; in nvidia_init_vga()
514 state->gra[0x08] = 0xff; in nvidia_init_vga()
516 state->seq[0x00] = 0x03; in nvidia_init_vga()
517 state->seq[0x01] = 0x01; in nvidia_init_vga()
518 state->seq[0x02] = 0x0f; in nvidia_init_vga()
519 state->seq[0x03] = 0x00; in nvidia_init_vga()
520 state->seq[0x04] = 0x0e; in nvidia_init_vga()
522 state->misc_output = 0xeb; in nvidia_init_vga()
535 NVShowHideCursor(par, 0); in nvidiafb_cursor()
539 par->cursor_reset = 0; in nvidiafb_cursor()
543 memset_io(par->CURSOR, 0, MAX_CURS * MAX_CURS * 2); in nvidiafb_cursor()
550 temp = xx & 0xFFFF; in nvidiafb_cursor()
553 NV_WR32(par->PRAMDAC, 0x0000300, temp); in nvidiafb_cursor()
570 for (i = 0; i < s_pitch * cursor->image.height; i++) in nvidiafb_cursor()
575 for (i = 0; i < s_pitch * cursor->image.height; i++) in nvidiafb_cursor()
583 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) | in nvidiafb_cursor()
584 ((info->cmap.green[bg_idx] & 0xf8) << 2) | in nvidiafb_cursor()
585 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1 << 15; in nvidiafb_cursor()
587 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) | in nvidiafb_cursor()
588 ((info->cmap.green[fg_idx] & 0xf8) << 2) | in nvidiafb_cursor()
589 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15; in nvidiafb_cursor()
591 NVLockUnlock(par, 0); in nvidiafb_cursor()
603 return 0; in nvidiafb_cursor()
616 par->FPDither = 0; in nvidiafb_set_par()
618 if (par->FPDither < 0) { in nvidiafb_set_par()
619 if ((par->Chipset & 0x0ff0) == 0x0110) in nvidiafb_set_par()
620 par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x0528) in nvidiafb_set_par()
621 & 0x00010000); in nvidiafb_set_par()
623 par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x083C) & 1); in nvidiafb_set_par()
634 NVLockUnlock(par, 0); in nvidiafb_set_par()
636 VGA_WR08(par->PCIO, 0x03D4, 0x44); in nvidiafb_set_par()
637 VGA_WR08(par->PCIO, 0x03D5, par->ModeReg.crtcOwner); in nvidiafb_set_par()
638 NVLockUnlock(par, 0); in nvidiafb_set_par()
644 NVSetStartAddress(par, 0); in nvidiafb_set_par()
651 VGA_WR08(par->PCIO, 0x3d4, 0x46); in nvidiafb_set_par()
652 tmp = VGA_RD08(par->PCIO, 0x3d5); in nvidiafb_set_par()
654 VGA_WR08(par->PCIO, 0x3d5, tmp); in nvidiafb_set_par()
681 nvidia_screen_off(par, 0); in nvidiafb_set_par()
690 NVLockUnlock(par, 0); in nvidiafb_set_par()
692 return 0; in nvidiafb_set_par()
725 for (i = 0; i < 8; i++) { in nvidiafb_setcolreg()
733 for (i = 0; i < 8; i++) { in nvidiafb_setcolreg()
742 for (i = 0; i < 4; i++) in nvidiafb_setcolreg()
756 return 0; in nvidiafb_setcolreg()
763 int memlen, vramlen, mode_valid = 0; in nvidiafb_check_var()
764 int pitch, err = 0; in nvidiafb_check_var()
770 var->transp.offset = 0; in nvidiafb_check_var()
771 var->transp.length = 0; in nvidiafb_check_var()
784 var->red.offset = 0; in nvidiafb_check_var()
786 var->green.offset = 0; in nvidiafb_check_var()
788 var->blue.offset = 0; in nvidiafb_check_var()
790 var->transp.offset = 0; in nvidiafb_check_var()
791 var->transp.length = 0; in nvidiafb_check_var()
798 var->blue.offset = 0; in nvidiafb_check_var()
808 var->blue.offset = 0; in nvidiafb_check_var()
815 var->red.msb_right = 0; in nvidiafb_check_var()
816 var->green.msb_right = 0; in nvidiafb_check_var()
817 var->blue.msb_right = 0; in nvidiafb_check_var()
818 var->transp.msb_right = 0; in nvidiafb_check_var()
826 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info)) in nvidiafb_check_var()
901 if (var->yres_virtual > 0x7fff) in nvidiafb_check_var()
902 var->yres_virtual = 0x7fff; in nvidiafb_check_var()
903 if (var->xres_virtual > 0x7fff) in nvidiafb_check_var()
904 var->xres_virtual = 0x7fff; in nvidiafb_check_var()
924 return 0; in nvidiafb_pan_display()
932 tmp = NVReadSeq(par, 0x01) & ~0x20; /* screen on/off */ in nvidiafb_blank()
933 vesa = NVReadCrtc(par, 0x1a) & ~0xc0; /* sync on/off */ in nvidiafb_blank()
938 tmp |= 0x20; in nvidiafb_blank()
945 vesa |= 0x80; in nvidiafb_blank()
948 vesa |= 0x40; in nvidiafb_blank()
951 vesa |= 0xc0; in nvidiafb_blank()
955 NVWriteSeq(par, 0x01, tmp); in nvidiafb_blank()
956 NVWriteCrtc(par, 0x1a, vesa); in nvidiafb_blank()
960 return 0; in nvidiafb_blank()
975 memset(&par->vgastate, 0, sizeof(par->vgastate)); in save_vga_x86()
990 #define save_vga_x86(x) do {} while (0)
991 #define restore_vga_x86(x) do {} while (0)
1004 return 0; in nvidiafb_open()
1010 int err = 0; in nvidiafb_release()
1063 return 0; in nvidiafb_suspend_late()
1090 fb_set_suspend (info, 0); in nvidiafb_resume()
1094 return 0; in nvidiafb_resume()
1127 case 0 ... 8: in nvidia_set_fbinfo()
1147 memset(buf, 0, 16); in nvidia_set_fbinfo()
1161 fb_alloc_cmap(&info->cmap, 256, 0); in nvidia_set_fbinfo()
1211 if ((id & 0xfff0) == 0x00f0 || in nvidia_get_chipset()
1212 (id & 0xfff0) == 0x02e0) { in nvidia_get_chipset()
1214 id = NV_RD32(REGS, 0x1800); in nvidia_get_chipset()
1216 if ((id & 0x0000ffff) == 0x000010DE) in nvidia_get_chipset()
1217 id = 0x10DE0000 | (id >> 16); in nvidia_get_chipset()
1218 else if ((id & 0xffff0000) == 0xDE100000) /* wrong endian */ in nvidia_get_chipset()
1219 id = 0x10DE0000 | ((id << 8) & 0x0000ff00) | in nvidia_get_chipset()
1220 ((id >> 8) & 0x000000ff); in nvidia_get_chipset()
1229 u32 arch = 0; in nvidia_get_arch()
1231 switch (Chipset & 0x0ff0) { in nvidia_get_arch()
1232 case 0x0100: /* GeForce 256 */ in nvidia_get_arch()
1233 case 0x0110: /* GeForce2 MX */ in nvidia_get_arch()
1234 case 0x0150: /* GeForce2 */ in nvidia_get_arch()
1235 case 0x0170: /* GeForce4 MX */ in nvidia_get_arch()
1236 case 0x0180: /* GeForce4 MX (8x AGP) */ in nvidia_get_arch()
1237 case 0x01A0: /* nForce */ in nvidia_get_arch()
1238 case 0x01F0: /* nForce2 */ in nvidia_get_arch()
1241 case 0x0200: /* GeForce3 */ in nvidia_get_arch()
1242 case 0x0250: /* GeForce4 Ti */ in nvidia_get_arch()
1243 case 0x0280: /* GeForce4 Ti (8x AGP) */ in nvidia_get_arch()
1246 case 0x0300: /* GeForceFX 5800 */ in nvidia_get_arch()
1247 case 0x0310: /* GeForceFX 5600 */ in nvidia_get_arch()
1248 case 0x0320: /* GeForceFX 5200 */ in nvidia_get_arch()
1249 case 0x0330: /* GeForceFX 5900 */ in nvidia_get_arch()
1250 case 0x0340: /* GeForceFX 5700 */ in nvidia_get_arch()
1253 case 0x0040: /* GeForce 6800 */ in nvidia_get_arch()
1254 case 0x00C0: /* GeForce 6800 */ in nvidia_get_arch()
1255 case 0x0120: /* GeForce 6800 */ in nvidia_get_arch()
1256 case 0x0140: /* GeForce 6600 */ in nvidia_get_arch()
1257 case 0x0160: /* GeForce 6200 */ in nvidia_get_arch()
1258 case 0x01D0: /* GeForce 7200, 7300, 7400 */ in nvidia_get_arch()
1259 case 0x0090: /* GeForce 7800 */ in nvidia_get_arch()
1260 case 0x0210: /* GeForce 6800 */ in nvidia_get_arch()
1261 case 0x0220: /* GeForce 6200 */ in nvidia_get_arch()
1262 case 0x0240: /* GeForce 6100 */ in nvidia_get_arch()
1263 case 0x0290: /* GeForce 7900 */ in nvidia_get_arch()
1264 case 0x0390: /* GeForce 7600 */ in nvidia_get_arch()
1265 case 0x03D0: in nvidia_get_arch()
1268 case 0x0020: /* TNT, TNT2 */ in nvidia_get_arch()
1301 nvidiafb_fix.mmio_start = pci_resource_start(pd, 0); in nvidiafb_probe()
1302 nvidiafb_fix.mmio_len = pci_resource_len(pd, 0); in nvidiafb_probe()
1312 if (Architecture == 0) { in nvidiafb_probe()
1354 sprintf(nvidiafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4); in nvidiafb_probe()
1396 if (nvidia_set_fbinfo(info) < 0) { in nvidiafb_probe()
1405 if (register_framebuffer(info) < 0) { in nvidiafb_probe()
1414 "PCI nVidia %s framebuffer (%dMB @ 0x%lX)\n", in nvidiafb_probe()
1419 return 0; in nvidiafb_probe()
1471 return 0; in nvidiafb_setup()
1480 forceCRTC = *p - '0'; in nvidiafb_setup()
1481 if (forceCRTC < 0 || forceCRTC > 1) in nvidiafb_setup()
1494 paneltweak = simple_strtoul(this_opt+11, NULL, 0); in nvidiafb_setup()
1496 vram = simple_strtoul(this_opt+5, NULL, 0); in nvidiafb_setup()
1498 backlight = simple_strtoul(this_opt+10, NULL, 0); in nvidiafb_setup()
1502 fpdither = simple_strtol(this_opt+9, NULL, 0); in nvidiafb_setup()
1504 bpp = simple_strtoul(this_opt+4, NULL, 0); in nvidiafb_setup()
1509 return 0; in nvidiafb_setup()
1553 module_param(flatpanel, int, 0);
1556 "(0=disabled, 1=enabled, -1=autodetect) (default=-1)");
1557 module_param(fpdither, int, 0);
1560 "(0=disabled, 1=enabled, -1=autodetect) (default=-1)");
1561 module_param(hwcur, int, 0);
1563 "Enables hardware cursor implementation. (0 or 1=enabled) "
1564 "(default=0)");
1565 module_param(noaccel, int, 0);
1567 "Disables hardware acceleration. (0 or 1=disable) "
1568 "(default=0)");
1569 module_param(noscale, int, 0);
1571 "Disables screen scaling. (0 or 1=disable) "
1572 "(default=0, do scaling)");
1573 module_param(paneltweak, int, 0);
1576 "(default=0, no tweaks)");
1577 module_param(forceCRTC, int, 0);
1580 "fails. (0 or 1) (default=autodetect)");
1581 module_param(vram, int, 0);
1584 "(default=0 - remap entire memory)");
1585 module_param(mode_option, charp, 0);
1587 module_param(bpp, int, 0);
1590 module_param(reverse_i2c, int, 0);
1593 MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) "
1594 "(default=0)");