Lines Matching +full:dphy +full:- +full:rx
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 /* ------------< LCD register >------------ */
150 #define LCD_SCLK(path) ((PATH_PN == path->id) ? LCD_CFG_SCLK_DIV :\
151 ((PATH_TV == path->id) ? LCD_TCLK_DIV : LCD_PN2_SCLK_DIV))
386 #define CFG_RXBITS(rx) (((rx) - 1)<<16) /* 0x1F~0x1 */ argument
388 #define CFG_TXBITS(tx) (((tx) - 1)<<8) /* 0x1F~0x1 */
394 #define CFG_RXBITSTO0(rx) ((rx)<<5) argument
411 1. Smart Pannel 8-bit Bus Control Register.
685 /* FIXME - JUST GUESS */
811 /* read-only */
1016 /* DSI1 - 4 Lane Controller base */
1018 /* DSI2 - 3 Lane Controller base */
1087 /* Rx Packet Header - data from slave device */
1100 #define DSI_PHY_CTRL_3 0x08C /* DPHY Control Register 3 */
1108 #define DSI_PHY_RCOMP_0 0x0B0 /* DPHY Rcomp Control Register */
1111 #define DSI_PHY_TIME_0 0x0C0 /* DPHY Timing Control Register 0 */
1112 #define DSI_PHY_TIME_1 0x0C4 /* DPHY Timing Control Register 1 */
1113 #define DSI_PHY_TIME_2 0x0C8 /* DPHY Timing Control Register 2 */
1114 #define DSI_PHY_TIME_3 0x0CC /* DPHY Timing Control Register 3 */
1115 #define DSI_PHY_TIME_4 0x0D0 /* DPHY Timing Control Register 4 */
1116 #define DSI_PHY_TIME_5 0x0D4 /* DPHY Timing Control Register 5 */
1208 /* DSI_PHY_CTRL_2 0x0088 DPHY Control Register 2 */
1210 /* DPHY LP Receiver Enable */
1213 /* DPHY Data Lane Enable */
1216 /* DPHY Bus Turn Around */
1232 /* DSI_PHY_TIME_0 0x00c0 DPHY Timing Control Register 0 */
1236 /* DPHY HS Trail Period Length */
1239 /* DPHY HS Zero State Length */
1242 /* DPHY HS Prepare State Length */
1246 /* DSI_PHY_TIME_1 0x00c4 DPHY Timing Control Register 1 */
1247 /* Time to Drive LP-00 by New Transmitter */
1250 /* Time to Drive LP-00 after Turn Request */
1253 /* DPHY HS Wakeup Period Length */
1257 /* DSI_PHY_TIME_2 0x00c8 DPHY Timing Control Register 2 */
1258 /* DPHY CLK Exit Period Length */
1261 /* DPHY CLK Trail Period Length */
1264 /* DPHY CLK Zero State Length */
1267 /* DPHY CLK LP Length */
1271 /* DSI_PHY_TIME_3 0x00cc DPHY Timing Control Register 3 */
1273 /* DPHY LP Length */
1276 /* DPHY HS req to rdy Length */
1414 return overlay->dmafetch_id & 1; in overlay_is_vid()
1419 return (struct mmphw_path_plat *)path->plat_data; in path_to_path_plat()
1424 return path_to_path_plat(path)->ctrl; in path_to_ctrl()
1429 return path_to_ctrl(overlay->path); in overlay_to_ctrl()
1434 return path_to_ctrl(path)->reg_base; in ctrl_regs()
1440 if (path->id == PATH_PN) in path_regs()
1442 else if (path->id == PATH_TV) in path_regs()
1444 else if (path->id == PATH_P2) in path_regs()
1447 dev_err(path->dev, "path id %d invalid\n", path->id); in path_regs()