Lines Matching +full:0 +full:x1c80
92 #define PCI_SS_VENDOR_ID_SIEMENS_NIXDORF 0x110A
99 #define PCI_SS_ID_MATROX_GENERIC 0xFF00
100 #define PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP 0xFF01
101 #define PCI_SS_ID_MATROX_MYSTIQUE_G200_AGP 0xFF02
102 #define PCI_SS_ID_MATROX_MILLENIUM_G200_AGP 0xFF03
103 #define PCI_SS_ID_MATROX_MARVEL_G200_AGP 0xFF04
104 #define PCI_SS_ID_MATROX_MGA_G100_PCI 0xFF05
105 #define PCI_SS_ID_MATROX_MGA_G100_AGP 0x1001
106 #define PCI_SS_ID_MATROX_MILLENNIUM_G400_MAX_AGP 0x2179
107 #define PCI_SS_ID_SIEMENS_MGA_G100_AGP 0x001E /* 30 */
108 #define PCI_SS_ID_SIEMENS_MGA_G200_AGP 0x0032 /* 50 */
115 #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
310 #define MATROXFB_SRC_NONE 0
452 /* 0 except for 6MB Millenium */
515 #define PCI_OPTION_REG 0x40
516 #define PCI_OPTION_ENABLE_ROM 0x40000000
518 #define PCI_MGA_INDEX 0x44
519 #define PCI_MGA_DATA 0x48
520 #define PCI_OPTION2_REG 0x50
521 #define PCI_OPTION3_REG 0x54
522 #define PCI_MEMMISC_REG 0x58
524 #define M_DWGCTL 0x1C00
525 #define M_MACCESS 0x1C04
526 #define M_CTLWTST 0x1C08
528 #define M_PLNWT 0x1C1C
530 #define M_BCOL 0x1C20
531 #define M_FCOL 0x1C24
533 #define M_SGN 0x1C58
534 #define M_LEN 0x1C5C
535 #define M_AR0 0x1C60
536 #define M_AR1 0x1C64
537 #define M_AR2 0x1C68
538 #define M_AR3 0x1C6C
539 #define M_AR4 0x1C70
540 #define M_AR5 0x1C74
541 #define M_AR6 0x1C78
543 #define M_CXBNDRY 0x1C80
544 #define M_FXBNDRY 0x1C84
545 #define M_YDSTLEN 0x1C88
546 #define M_PITCH 0x1C8C
547 #define M_YDST 0x1C90
548 #define M_YDSTORG 0x1C94
549 #define M_YTOP 0x1C98
550 #define M_YBOT 0x1C9C
553 #define M_CACHEFLUSH 0x1FFF
555 #define M_EXEC 0x0100
557 #define M_DWG_TRAP 0x04
558 #define M_DWG_BITBLT 0x08
559 #define M_DWG_ILOAD 0x09
561 #define M_DWG_LINEAR 0x0080
562 #define M_DWG_SOLID 0x0800
563 #define M_DWG_ARZERO 0x1000
564 #define M_DWG_SGNZERO 0x2000
565 #define M_DWG_SHIFTZERO 0x4000
567 #define M_DWG_REPLACE 0x000C0000
568 #define M_DWG_REPLACE2 (M_DWG_REPLACE | 0x40)
569 #define M_DWG_XOR 0x00060010
571 #define M_DWG_BFCOL 0x04000000
572 #define M_DWG_BMONOWF 0x08000000
574 #define M_DWG_TRANSC 0x40000000
576 #define M_FIFOSTATUS 0x1E10
577 #define M_STATUS 0x1E14
578 #define M_ICLEAR 0x1E18
579 #define M_IEN 0x1E1C
581 #define M_VCOUNT 0x1E20
583 #define M_RESET 0x1E40
584 #define M_MEMRDBK 0x1E44
586 #define M_AGP2PLL 0x1E4C
588 #define M_OPMODE 0x1E54
589 #define M_OPMODE_DMA_GEN_WRITE 0x00
590 #define M_OPMODE_DMA_BLIT 0x04
591 #define M_OPMODE_DMA_VECTOR_WRITE 0x08
592 #define M_OPMODE_DMA_LE 0x0000 /* little endian - no transformation */
593 #define M_OPMODE_DMA_BE_8BPP 0x0000
594 #define M_OPMODE_DMA_BE_16BPP 0x0100
595 #define M_OPMODE_DMA_BE_32BPP 0x0200
596 #define M_OPMODE_DIR_LE 0x000000 /* little endian - no transformation */
597 #define M_OPMODE_DIR_BE_8BPP 0x000000
598 #define M_OPMODE_DIR_BE_16BPP 0x010000
599 #define M_OPMODE_DIR_BE_32BPP 0x020000
601 #define M_ATTR_INDEX 0x1FC0
602 #define M_ATTR_DATA 0x1FC1
604 #define M_MISC_REG 0x1FC2
605 #define M_3C2_RD 0x1FC2
607 #define M_SEQ_INDEX 0x1FC4
608 #define M_SEQ_DATA 0x1FC5
609 #define M_SEQ1 0x01
610 #define M_SEQ1_SCROFF 0x20
612 #define M_MISC_REG_READ 0x1FCC
614 #define M_GRAPHICS_INDEX 0x1FCE
615 #define M_GRAPHICS_DATA 0x1FCF
617 #define M_CRTC_INDEX 0x1FD4
619 #define M_ATTR_RESET 0x1FDA
620 #define M_3DA_WR 0x1FDA
621 #define M_INSTS1 0x1FDA
623 #define M_EXTVGA_INDEX 0x1FDE
624 #define M_EXTVGA_DATA 0x1FDF
627 #define M_SRCORG 0x2CB4
628 #define M_DSTORG 0x2CB8
630 #define M_RAMDAC_BASE 0x3C00
633 #define M_DAC_REG (M_RAMDAC_BASE+0)
637 #define M_X_INDEX 0x00
638 #define M_X_DATAREG 0x0A
640 #define DAC_XGENIOCTRL 0x2A
641 #define DAC_XGENIODATA 0x2B
643 #define M_C2CTL 0x3C10
645 #define MX_OPTION_BSWAP 0x00000000
673 #define mga_fifo(n) do {} while ((mga_inl(M_FIFOSTATUS) & 0xFF) < (n))
675 …efine WaitTillIdle() do { mga_inl(M_STATUS); do {} while (mga_inl(M_STATUS) & 0x10000); } while (0)
683 #define isInterleave(x) (0)
684 #define isMillenium(x) (0)
685 #define isMilleniumII(x) (0)