30 	outb(CONFIG_CCR3, 0x22);  in gx1_read_conf_reg()
31 	ccr3 = inb(0x23);  in gx1_read_conf_reg()
32 	outb(CONFIG_CCR3, 0x22);  in gx1_read_conf_reg()
33 	outb(ccr3 | CONFIG_CCR3_MAPEN, 0x23);  in gx1_read_conf_reg()
34 	outb(reg, 0x22);  in gx1_read_conf_reg()
35 	val = inb(0x23);  in gx1_read_conf_reg()
36 	outb(CONFIG_CCR3, 0x22);  in gx1_read_conf_reg()
37 	outb(ccr3, 0x23);  in gx1_read_conf_reg()
46 	return (gx1_read_conf_reg(CONFIG_GCR) & 0x03) << 30;  in gx1_gx_base()
54 	unsigned dram_size = 0, fb_base;  in gx1_frame_buffer_size()
56 	mc_regs = ioremap(gx1_gx_base() + 0x8400, 0x100);  in gx1_frame_buffer_size()
64 	for (d = 0; d < 2; d++) {  in gx1_frame_buffer_size()
66 			dram_size += 0x400000 << ((bank_cfg & MC_BCFG_DIMM0_SZ_MASK) >> 8);  in gx1_frame_buffer_size()
131 	writel(0, par->dc_regs + DC_FB_ST_OFFSET);  in gx1_set_mode()
186 	writel(0, par->dc_regs + DC_UNLOCK);  in gx1_set_mode()
199 	val  = (red   <<  2) & 0x3f000;  in gx1_set_hw_palette_reg()
200 	val |= (green >>  4) & 0x00fc0;  in gx1_set_hw_palette_reg()
201 	val |= (blue  >> 10) & 0x0003f;  in gx1_set_hw_palette_reg()