49 #define mmio_base (p->screen_base + 0x400000)
53 } while (0)
57 	mm_write_ind(reg, data, 0x7ac, 0x7ad);  in mm_write_xr()
63 	mm_write_ind(reg, data, 0x7a0, 0x7a1);  in mm_write_fr()
69 	mm_write_ind(reg, data, 0x7a8, 0x7a9);  in mm_write_cr()
75 	mm_write_ind(reg, data, 0x79c, 0x79d);  in mm_write_gr()
81 	mm_write_ind(reg, data, 0x788, 0x789);  in mm_write_sr()
87 	readb(mmio_base + 0x7b4);  in mm_write_ar()
88 	mm_write_ind(reg, data, 0x780, 0x780);  in mm_write_ar()
114 	unsigned best_error = 0xffffffff;  in asiliant_calc_dclk2()
115 	unsigned best_m = 0xffffffff,  in asiliant_calc_dclk2()
116 	         best_n = 0xffffffff;  in asiliant_calc_dclk2()
119 	unsigned char divisor = 0;  in asiliant_calc_dclk2()
127 		divisor += 0x10;  in asiliant_calc_dclk2()
186 	  write_fr(0x01, 0x02);  /* LCD */  in asiliant_set_timing()
188 	  write_fr(0x01, 0x01);  /* CRT */  in asiliant_set_timing()
191 	write_cr(0x11, (ve - 1) & 0x0f);  in asiliant_set_timing()
192 	write_cr(0x00, (ht - 5) & 0xff);  in asiliant_set_timing()
193 	write_cr(0x01, hd - 1);  in asiliant_set_timing()
194 	write_cr(0x02, hd);  in asiliant_set_timing()
195 	write_cr(0x03, ((ht - 1) & 0x1f) | 0x80);  in asiliant_set_timing()
196 	write_cr(0x04, hs);  in asiliant_set_timing()
197 	write_cr(0x05, (((ht - 1) & 0x20) <<2) | (he & 0x1f));  in asiliant_set_timing()
198 	write_cr(0x3c, (ht - 1) & 0xc0);  in asiliant_set_timing()
199 	write_cr(0x06, (vt - 2) & 0xff);  in asiliant_set_timing()
200 	write_cr(0x30, (vt - 2) >> 8);  in asiliant_set_timing()
201 	write_cr(0x07, 0x00);  in asiliant_set_timing()
202 	write_cr(0x08, 0x00);  in asiliant_set_timing()
203 	write_cr(0x09, 0x00);  in asiliant_set_timing()
204 	write_cr(0x10, (vs - 1) & 0xff);  in asiliant_set_timing()
205 	write_cr(0x32, ((vs - 1) >> 8) & 0xf);  in asiliant_set_timing()
206 	write_cr(0x11, ((ve - 1) & 0x0f) | 0x80);  in asiliant_set_timing()
207 	write_cr(0x12, (vd - 1) & 0xff);  in asiliant_set_timing()
208 	write_cr(0x31, ((vd - 1) & 0xf00) >> 8);  in asiliant_set_timing()
209 	write_cr(0x13, wd & 0xff);  in asiliant_set_timing()
210 	write_cr(0x41, (wd & 0xf00) >> 8);  in asiliant_set_timing()
211 	write_cr(0x15, (vs - 1) & 0xff);  in asiliant_set_timing()
212 	write_cr(0x33, ((vs - 1) >> 8) & 0xf);  in asiliant_set_timing()
213 	write_cr(0x38, ((ht - 5) & 0x100) >> 8);  in asiliant_set_timing()
214 	write_cr(0x16, (vt - 1) & 0xff);  in asiliant_set_timing()
215 	write_cr(0x18, 0x00);  in asiliant_set_timing()
218 	  writeb(0xc7, mmio_base + 0x784);	/* set misc output reg */  in asiliant_set_timing()
220 	  writeb(0x07, mmio_base + 0x784);	/* set misc output reg */  in asiliant_set_timing()
248 		var->blue.offset = 0;  in asiliantfb_check_var()
262 		var->blue.offset = 0;  in asiliantfb_check_var()
265 		var->red.offset = var->green.offset = var->blue.offset = 0;  in asiliantfb_check_var()
268 	return 0;  in asiliantfb_check_var()
282 		write_xr(0x81, 0x16);	/* 24 bit packed color mode */  in asiliantfb_set_par()
283 		write_xr(0x82, 0x00);	/* Disable palettes */  in asiliantfb_set_par()
284 		write_xr(0x20, 0x20);	/* 24 bit blitter mode */  in asiliantfb_set_par()
287 			write_xr(0x81, 0x15);	/* 16 bit color mode */  in asiliantfb_set_par()
289 			write_xr(0x81, 0x14);	/* 15 bit color mode */  in asiliantfb_set_par()
290 		write_xr(0x82, 0x00);	/* Disable palettes */  in asiliantfb_set_par()
291 		write_xr(0x20, 0x10);	/* 16 bit blitter mode */  in asiliantfb_set_par()
293 		write_xr(0x0a, 0x02);	/* Linear */  in asiliantfb_set_par()
294 		write_xr(0x81, 0x12);	/* 8 bit color mode */  in asiliantfb_set_par()
295 		write_xr(0x82, 0x00);	/* Graphics gamma enable */  in asiliantfb_set_par()
296 		write_xr(0x20, 0x00);	/* 8 bit blitter mode */  in asiliantfb_set_par()
300 	write_xr(0xc4, dclk2_m);  in asiliantfb_set_par()
301 	write_xr(0xc5, dclk2_n);  in asiliantfb_set_par()
302 	write_xr(0xc7, dclk2_div);  in asiliantfb_set_par()
305 	return 0;  in asiliantfb_set_par()
318 	writeb(regno, mmio_base + 0x790);  in asiliantfb_setcolreg()
320 	writeb(red, mmio_base + 0x791);  in asiliantfb_setcolreg()
321 	writeb(green, mmio_base + 0x791);  in asiliantfb_setcolreg()
322 	writeb(blue, mmio_base + 0x791);  in asiliantfb_setcolreg()
328 				((red & 0xf8) << 7) |  in asiliantfb_setcolreg()
329 				((green & 0xf8) << 2) |  in asiliantfb_setcolreg()
330 				((blue & 0xf8) >> 3);  in asiliantfb_setcolreg()
334 				((red & 0xf8) << 8) |  in asiliantfb_setcolreg()
335 				((green & 0xfc) << 3) |  in asiliantfb_setcolreg()
336 				((blue & 0xf8) >> 3);  in asiliantfb_setcolreg()
347 	return 0;  in asiliantfb_setcolreg()
357 	{0x00, 0x03},		/* Reset register */
358 	{0x01, 0x01},		/* Clocking mode */
359 	{0x02, 0x0f},		/* Plane mask */
360 	{0x04, 0x0e}		/* Memory mode */
365         {0x03, 0x00},		/* Data rotate */
366 	{0x05, 0x00},		/* Graphics mode */
367 	{0x06, 0x01},		/* Miscellaneous */
368 	{0x08, 0x00}		/* Bit mask */
373 	{0x10, 0x01},		/* Mode control */
374 	{0x11, 0x00},		/* Overscan */
375 	{0x12, 0x0f},		/* Memory plane enable */
376 	{0x13, 0x00}		/* Horizontal pixel panning */
381 	{0x0c, 0x00},		/* Start address high */
382 	{0x0d, 0x00},		/* Start address low */
383 	{0x40, 0x00},		/* Extended Start Address */
384 	{0x41, 0x00},		/* Extended Start Address */
385 	{0x14, 0x00},		/* Underline location */
386 	{0x17, 0xe3},		/* CRT mode control */
387 	{0x70, 0x00}		/* Interlace control */
393 	{0x01, 0x02},
394 	{0x03, 0x08},
395 	{0x08, 0xcc},
396 	{0x0a, 0x08},
397 	{0x18, 0x00},
398 	{0x1e, 0x80},
399 	{0x40, 0x83},
400 	{0x41, 0x00},
401 	{0x48, 0x13},
402 	{0x4d, 0x60},
403 	{0x4e, 0x0f},
405 	{0x0b, 0x01},
407 	{0x21, 0x51},
408 	{0x22, 0x1d},
409 	{0x23, 0x5f},
410 	{0x20, 0x4f},
411 	{0x34, 0x00},
412 	{0x24, 0x51},
413 	{0x25, 0x00},
414 	{0x27, 0x0b},
415 	{0x26, 0x00},
416 	{0x37, 0x80},
417 	{0x33, 0x0b},
418 	{0x35, 0x11},
419 	{0x36, 0x02},
420 	{0x31, 0xea},
421 	{0x32, 0x0c},
422 	{0x30, 0xdf},
423 	{0x10, 0x0c},
424 	{0x11, 0xe0},
425 	{0x12, 0x50},
426 	{0x13, 0x00},
427 	{0x16, 0x03},
428 	{0x17, 0xbd},
429 	{0x1a, 0x00},
435 	{0xce, 0x00},		/* set default memory clock */
436 	{0xcc, 200 },	        /* MCLK ratio M */
437 	{0xcd, 18  },	        /* MCLK ratio N */
438 	{0xce, 0x90},		/* MCLK divisor = 2 */
440 	{0xc4, 209 },
441 	{0xc5, 118 },
442 	{0xc7, 32  },
443 	{0xcf, 0x06},
444 	{0x09, 0x01},		/* IO Control - CRT controller extensions */
445 	{0x0a, 0x02},		/* Frame buffer mapping */
446 	{0x0b, 0x01},		/* PCI burst write */
447 	{0x40, 0x03},		/* Memory access control */
448 	{0x80, 0x82},		/* Pixel pipeline configuration 0 */
449 	{0x81, 0x12},		/* Pixel pipeline configuration 1 */
450 	{0x82, 0x08},		/* Pixel pipeline configuration 2 */
452 	{0xd0, 0x0f},
453 	{0xd1, 0x01},
460 	for (i = 0; i < ARRAY_SIZE(chips_init_xr); ++i)  in chips_hw_init()
462 	write_xr(0x81, 0x12);  in chips_hw_init()
463 	write_xr(0x82, 0x08);  in chips_hw_init()
464 	write_xr(0x20, 0x00);  in chips_hw_init()
465 	for (i = 0; i < ARRAY_SIZE(chips_init_sr); ++i)  in chips_hw_init()
467 	for (i = 0; i < ARRAY_SIZE(chips_init_gr); ++i)  in chips_hw_init()
469 	for (i = 0; i < ARRAY_SIZE(chips_init_ar); ++i)  in chips_hw_init()
472 	writeb(0x20, mmio_base + 0x780);  in chips_hw_init()
473 	for (i = 0; i < ARRAY_SIZE(chips_init_cr); ++i)  in chips_hw_init()
475 	for (i = 0; i < ARRAY_SIZE(chips_init_fr); ++i)  in chips_hw_init()
485 	.smem_len =	0x200000,	/* 2MB */
518 	err = fb_alloc_cmap(&p->cmap, 256, 0);  in init_asiliant()
525 	if (err < 0) {  in init_asiliant()
534 	writeb(0xff, mmio_base + 0x78c);  in init_asiliant()
536 	return 0;  in init_asiliant()
550 	if ((dp->resource[0].flags & IORESOURCE_MEM) == 0)  in asiliantfb_pci_init()
552 	addr = pci_resource_start(dp, 0);  in asiliantfb_pci_init()
553 	size = pci_resource_len(dp, 0);  in asiliantfb_pci_init()
554 	if (addr == 0)  in asiliantfb_pci_init()
567 	p->screen_base = ioremap(addr, 0x800000);  in asiliantfb_pci_init()
574 	pci_write_config_dword(dp, 4, 0x02800083);  in asiliantfb_pci_init()
575 	writeb(3, p->screen_base + 0x400784);  in asiliantfb_pci_init()
586 	return 0;  in asiliantfb_pci_init()
596 	release_mem_region(pci_resource_start(dp, 0), pci_resource_len(dp, 0));  in asiliantfb_remove()
602 	{ 0 }