Lines Matching full:csr
230 u16 fifo_count = 0, csr; in txstate() local
249 csr = musb_readw(epio, MUSB_TXCSR); in txstate()
255 if (csr & MUSB_TXCSR_TXPKTRDY) { in txstate()
257 musb_ep->end_point.name, csr); in txstate()
261 if (csr & MUSB_TXCSR_P_SENDSTALL) { in txstate()
263 musb_ep->end_point.name, csr); in txstate()
269 csr); in txstate()
276 /* setup DMA, then program endpoint CSR */ in txstate()
302 csr &= ~(MUSB_TXCSR_AUTOSET in txstate()
304 musb_writew(epio, MUSB_TXCSR, csr in txstate()
306 csr &= ~MUSB_TXCSR_DMAMODE; in txstate()
307 csr |= (MUSB_TXCSR_DMAENAB | in txstate()
311 csr |= (MUSB_TXCSR_DMAENAB in txstate()
326 csr |= MUSB_TXCSR_AUTOSET; in txstate()
328 csr &= ~MUSB_TXCSR_P_UNDERRUN; in txstate()
330 musb_writew(epio, MUSB_TXCSR, csr); in txstate()
335 /* program endpoint CSR first, then setup DMA */ in txstate()
336 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY); in txstate()
337 csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE | in txstate()
340 ~MUSB_TXCSR_P_UNDERRUN) | csr); in txstate()
343 csr = musb_readw(epio, MUSB_TXCSR); in txstate()
366 csr &= ~MUSB_TXCSR_DMAENAB; in txstate()
367 musb_writew(epio, MUSB_TXCSR, csr); in txstate()
389 csr |= MUSB_TXCSR_TXPKTRDY; in txstate()
390 csr &= ~MUSB_TXCSR_P_UNDERRUN; in txstate()
391 musb_writew(epio, MUSB_TXCSR, csr); in txstate()
409 u16 csr; in musb_g_tx() local
421 csr = musb_readw(epio, MUSB_TXCSR); in musb_g_tx()
422 musb_dbg(musb, "<== %s, txcsr %04x", musb_ep->end_point.name, csr); in musb_g_tx()
430 if (csr & MUSB_TXCSR_P_SENTSTALL) { in musb_g_tx()
431 csr |= MUSB_TXCSR_P_WZC_BITS; in musb_g_tx()
432 csr &= ~MUSB_TXCSR_P_SENTSTALL; in musb_g_tx()
433 musb_writew(epio, MUSB_TXCSR, csr); in musb_g_tx()
437 if (csr & MUSB_TXCSR_P_UNDERRUN) { in musb_g_tx()
439 csr |= MUSB_TXCSR_P_WZC_BITS; in musb_g_tx()
440 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY); in musb_g_tx()
441 musb_writew(epio, MUSB_TXCSR, csr); in musb_g_tx()
459 if (dma && (csr & MUSB_TXCSR_DMAENAB)) { in musb_g_tx()
460 csr |= MUSB_TXCSR_P_WZC_BITS; in musb_g_tx()
461 csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN | in musb_g_tx()
463 musb_writew(epio, MUSB_TXCSR, csr); in musb_g_tx()
465 csr = musb_readw(epio, MUSB_TXCSR); in musb_g_tx()
468 epnum, csr, musb_ep->dma->actual_len, request); in musb_g_tx()
483 if (csr & MUSB_TXCSR_TXPKTRDY) in musb_g_tx()
527 u16 csr = musb_readw(epio, MUSB_RXCSR); in rxstate() local
551 if (csr & MUSB_RXCSR_P_SENDSTALL) { in rxstate()
553 musb_ep->end_point.name, csr); in rxstate()
576 csr &= ~(MUSB_RXCSR_AUTOCLEAR in rxstate()
578 csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS; in rxstate()
579 musb_writew(epio, MUSB_RXCSR, csr); in rxstate()
584 if (csr & MUSB_RXCSR_RXPKTRDY) { in rxstate()
634 csr |= MUSB_RXCSR_AUTOCLEAR; in rxstate()
635 musb_writew(epio, MUSB_RXCSR, csr); in rxstate()
636 csr |= MUSB_RXCSR_DMAENAB; in rxstate()
637 musb_writew(epio, MUSB_RXCSR, csr); in rxstate()
645 csr | MUSB_RXCSR_DMAMODE); in rxstate()
646 musb_writew(epio, MUSB_RXCSR, csr); in rxstate()
656 csr |= MUSB_RXCSR_AUTOCLEAR; in rxstate()
657 csr |= MUSB_RXCSR_DMAENAB; in rxstate()
658 musb_writew(epio, MUSB_RXCSR, csr); in rxstate()
701 csr &= ~MUSB_RXCSR_DMAMODE; in rxstate()
702 csr |= (MUSB_RXCSR_DMAENAB | in rxstate()
705 musb_writew(epio, MUSB_RXCSR, csr); in rxstate()
712 csr |= MUSB_RXCSR_DMAMODE; in rxstate()
713 musb_writew(epio, MUSB_RXCSR, csr); in rxstate()
760 csr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_AUTOCLEAR); in rxstate()
761 musb_writew(epio, MUSB_RXCSR, csr); in rxstate()
776 csr |= MUSB_RXCSR_P_WZC_BITS; in rxstate()
777 csr &= ~MUSB_RXCSR_RXPKTRDY; in rxstate()
778 musb_writew(epio, MUSB_RXCSR, csr); in rxstate()
793 u16 csr; in musb_g_rx() local
816 csr = musb_readw(epio, MUSB_RXCSR); in musb_g_rx()
820 csr, dma ? " (dma)" : "", request); in musb_g_rx()
822 if (csr & MUSB_RXCSR_P_SENTSTALL) { in musb_g_rx()
823 csr |= MUSB_RXCSR_P_WZC_BITS; in musb_g_rx()
824 csr &= ~MUSB_RXCSR_P_SENTSTALL; in musb_g_rx()
825 musb_writew(epio, MUSB_RXCSR, csr); in musb_g_rx()
829 if (csr & MUSB_RXCSR_P_OVERRUN) { in musb_g_rx()
830 /* csr |= MUSB_RXCSR_P_WZC_BITS; */ in musb_g_rx()
831 csr &= ~MUSB_RXCSR_P_OVERRUN; in musb_g_rx()
832 musb_writew(epio, MUSB_RXCSR, csr); in musb_g_rx()
838 if (csr & MUSB_RXCSR_INCOMPRX) { in musb_g_rx()
845 musb_dbg(musb, "%s busy, csr %04x", in musb_g_rx()
846 musb_ep->end_point.name, csr); in musb_g_rx()
850 if (dma && (csr & MUSB_RXCSR_DMAENAB)) { in musb_g_rx()
851 csr &= ~(MUSB_RXCSR_AUTOCLEAR in musb_g_rx()
855 MUSB_RXCSR_P_WZC_BITS | csr); in musb_g_rx()
866 csr &= ~MUSB_RXCSR_RXPKTRDY; in musb_g_rx()
867 musb_writew(epio, MUSB_RXCSR, csr); in musb_g_rx()
877 csr = musb_readw(epio, MUSB_RXCSR); in musb_g_rx()
878 if ((csr & MUSB_RXCSR_RXPKTRDY) && in musb_g_rx()
919 u16 csr; in musb_gadget_enable() local
998 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG; in musb_gadget_enable()
1001 csr |= MUSB_TXCSR_FLUSHFIFO; in musb_gadget_enable()
1003 csr |= MUSB_TXCSR_P_ISO; in musb_gadget_enable()
1006 musb_writew(regs, MUSB_TXCSR, csr); in musb_gadget_enable()
1008 musb_writew(regs, MUSB_TXCSR, csr); in musb_gadget_enable()
1036 csr = musb_readw(regs, MUSB_TXCSR); in musb_gadget_enable()
1037 csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY); in musb_gadget_enable()
1038 musb_writew(regs, MUSB_TXCSR, csr); in musb_gadget_enable()
1041 csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG; in musb_gadget_enable()
1043 csr |= MUSB_RXCSR_P_ISO; in musb_gadget_enable()
1045 csr |= MUSB_RXCSR_DISNYET; in musb_gadget_enable()
1048 musb_writew(regs, MUSB_RXCSR, csr); in musb_gadget_enable()
1049 musb_writew(regs, MUSB_RXCSR, csr); in musb_gadget_enable()
1165 u16 csr; in musb_ep_restart() local
1173 csr = musb_readw(epio, MUSB_RXCSR); in musb_ep_restart()
1174 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS; in musb_ep_restart()
1175 musb_writew(epio, MUSB_RXCSR, csr); in musb_ep_restart()
1176 musb_writew(epio, MUSB_RXCSR, csr); in musb_ep_restart()
1335 u16 csr; in musb_gadget_set_halt() local
1362 csr = musb_readw(epio, MUSB_TXCSR); in musb_gadget_set_halt()
1363 if (csr & MUSB_TXCSR_FIFONOTEMPTY) { in musb_gadget_set_halt()
1376 csr = musb_readw(epio, MUSB_TXCSR); in musb_gadget_set_halt()
1377 csr |= MUSB_TXCSR_P_WZC_BITS in musb_gadget_set_halt()
1380 csr |= MUSB_TXCSR_P_SENDSTALL; in musb_gadget_set_halt()
1382 csr &= ~(MUSB_TXCSR_P_SENDSTALL in musb_gadget_set_halt()
1384 csr &= ~MUSB_TXCSR_TXPKTRDY; in musb_gadget_set_halt()
1385 musb_writew(epio, MUSB_TXCSR, csr); in musb_gadget_set_halt()
1387 csr = musb_readw(epio, MUSB_RXCSR); in musb_gadget_set_halt()
1388 csr |= MUSB_RXCSR_P_WZC_BITS in musb_gadget_set_halt()
1392 csr |= MUSB_RXCSR_P_SENDSTALL; in musb_gadget_set_halt()
1394 csr &= ~(MUSB_RXCSR_P_SENDSTALL in musb_gadget_set_halt()
1396 musb_writew(epio, MUSB_RXCSR, csr); in musb_gadget_set_halt()
1456 u16 csr; in musb_gadget_fifo_flush() local
1467 csr = musb_readw(epio, MUSB_TXCSR); in musb_gadget_fifo_flush()
1468 if (csr & MUSB_TXCSR_FIFONOTEMPTY) { in musb_gadget_fifo_flush()
1469 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS; in musb_gadget_fifo_flush()
1475 csr &= ~MUSB_TXCSR_TXPKTRDY; in musb_gadget_fifo_flush()
1476 musb_writew(epio, MUSB_TXCSR, csr); in musb_gadget_fifo_flush()
1478 musb_writew(epio, MUSB_TXCSR, csr); in musb_gadget_fifo_flush()
1481 csr = musb_readw(epio, MUSB_RXCSR); in musb_gadget_fifo_flush()
1482 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS; in musb_gadget_fifo_flush()
1483 musb_writew(epio, MUSB_RXCSR, csr); in musb_gadget_fifo_flush()
1484 musb_writew(epio, MUSB_RXCSR, csr); in musb_gadget_fifo_flush()