Lines Matching +full:ete +full:- +full:0
1 /* SPDX-License-Identifier: GPL-2.0 */
19 #include <linux/io-64-nonatomic-lo-hi.h>
20 #include <linux/io-64-nonatomic-hi-lo.h>
22 /* Code sharing between pci-quirks and xhci hcd */
23 #include "xhci-ext-caps.h"
24 #include "pci-quirks.h"
26 #include "xhci-port.h"
27 #include "xhci-caps.h"
33 #define XHCI_SBRN_OFFSET (0x60)
35 /* Max number of USB devices for any host controller - limit in section 6.1 */
37 /* Section 5.3.3 - MaxPorts */
47 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
49 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
50 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
51 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
52 * @hcc_params: HCCPARAMS - Capability Parameters
53 * @db_off: DBOFF - Doorbell array offset
54 * @run_regs_off: RTSOFF - Runtime register space offset
66 /* Reserved up to (CAPLENGTH - 0x1C) */
72 #define PORTSC 0
78 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
79 * @command: USBCMD - xHC command register
80 * @status: USBSTS - xHC status register
85 * @cmd_ring: CRP - 64-bit Command Ring Pointer
86 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
87 * @config_reg: CONFIG - Configure Register
88 * @port_status_base: PORTSCn - base address for Port Status and Control
93 * @port_power_base: PORTPMSCn - base address for
95 * @port_link_base: PORTLIn - base address for Port Link Info (current
107 /* rsvd: offset 0x20-2F */
111 /* rsvd: offset 0x3C-3FF */
118 /* registers for ports 2-255 */
122 /* USBCMD - USB command - command bitmasks */
123 /* start/stop HC execution - do not write unless HC is halted*/
125 /* Reset HC - resets internal HC state machine and all registers (except
130 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
132 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
135 /* light reset (port status stays unchanged) - reset completed when this is 0 */
140 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
142 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
143 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
144 * '0' means the xHC can power it off if all ports are in the disconnect,
145 * disabled, or powered-off state.
155 /* IMAN - Interrupt Management Register */
157 #define IMAN_IP (1 << 0)
159 /* USBSTS - USB status - status bitmasks */
160 /* HC not running - set to 1 when run/stop bit is cleared. */
164 /* event interrupt - clear this prior to clearing any IP flags in IR set*/
169 /* save state status - '1' means xHC is saving state */
171 /* restore state status - '1' means xHC is restoring state */
177 /* true: internal Host Controller Error - SW needs to reset and reinitialize */
182 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
186 #define DEV_NOTE_MASK (0xffff)
193 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
194 /* bit 0 is the command ring cycle state */
197 /* stop ring immediately - abort the currently executing command */
202 /* Command Ring pointer - bit mask for the lower 32 bits. */
203 #define CMD_RING_RSVD_BITS (0x3f)
205 /* CONFIG - Configure Register - config_reg bitmasks */
206 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
207 #define MAX_DEVS(p) ((p) & 0xff)
212 /* bits 10:31 - reserved and should be preserved */
215 * struct xhci_intr_reg - Interrupt Register Set
216 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
218 * @irq_control: IMOD - Interrupt Moderation Register.
224 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
241 #define ER_IRQ_PENDING(p) ((p) & 0x1)
243 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
244 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
245 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
246 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
253 #define ER_IRQ_INTERVAL_MASK (0xffff)
254 /* Counter used to count down the time to the next interrupt - HW use only */
255 #define ER_IRQ_COUNTER_MASK (0xffff << 16)
259 #define ERST_SIZE_MASK (0xffff << 16)
262 #define ERST_BASE_RSVDP (GENMASK_ULL(5, 0))
265 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
268 #define ERST_DESI_MASK (0x7)
269 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
278 * MFINDEX - current microframe number
293 * Bits 0 - 7: Endpoint target
294 * Bits 8 - 15: RsvdZ
295 * Bits 16 - 31: Stream ID
303 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
304 #define DB_VALUE_HOST 0x00000000
306 #define PLT_MASK (0x03 << 6)
307 #define PLT_SYM (0x00 << 6)
308 #define PLT_ASYM_RX (0x02 << 6)
309 #define PLT_ASYM_TX (0x03 << 6)
323 #define XHCI_CTX_TYPE_DEVICE 0x1
324 #define XHCI_CTX_TYPE_INPUT 0x2
339 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
340 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
348 /* offset 0x10 to 0x1f reserved for HC internal use */
353 /* Route String - 0:19 */
354 #define ROUTE_STRING_MASK (0xfffff)
355 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
356 #define DEV_SPEED (0xf << 20)
359 /* Is this LS/FS device connected through a HS hub? - bit 25 */
360 #define DEV_MTT (0x1 << 25)
361 /* Set if the device is a hub - bit 26 */
362 #define DEV_HUB (0x1 << 26)
363 /* Index of the last valid endpoint context in this device context - 27:31 */
364 #define LAST_CTX_MASK (0x1f << 27)
366 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
367 #define SLOT_FLAG (1 << 0)
371 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
372 #define MAX_EXIT (0xffff)
374 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
375 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
377 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
378 #define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24)
382 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
384 * this low or full-speed device. '0' if attached to root hub port.
386 #define TT_SLOT (0xff)
388 * The number of the downstream facing port of the high-speed hub
389 * '0' if the device is not low or full speed.
391 #define TT_PORT (0xff << 8)
392 #define TT_THINK_TIME(p) (((p) & 0x3) << 16)
393 #define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16)
396 /* USB device address - assigned by the HC */
397 #define DEV_ADDR_MASK (0xff)
400 #define SLOT_STATE (0x1f << 27)
401 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
403 #define SLOT_STATE_DISABLED 0
415 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
423 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
424 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
432 /* offset 0x14 - 0x1f reserved for HC internal use */
438 * Endpoint State - bits 0:2
439 * 0 - disabled
440 * 1 - running
441 * 2 - halted due to halt condition - ok to manipulate endpoint ring
442 * 3 - stopped
443 * 4 - TRB error
444 * 5-7 - reserved
446 #define EP_STATE_MASK (0x7)
447 #define EP_STATE_DISABLED 0
452 #define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
454 /* Mult - Max number of burtst within an interval, in EP companion desc. */
455 #define EP_MULT(p) (((p) & 0x3) << 8)
456 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
459 /* Interval - period between requests to an endpoint - 125u increments. */
460 #define EP_INTERVAL(p) (((p) & 0xff) << 16)
461 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
462 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
463 #define EP_MAXPSTREAMS_MASK (0x1f << 10)
469 #define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff)
473 * Force Event - generate transfer events for all TRBs for this endpoint
476 #define FORCE_EVENT (0x1)
477 #define ERROR_COUNT(p) (((p) & 0x3) << 1)
478 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
488 /* bit 7 is Host Initiate Disable - for disabling stream selection */
489 #define MAX_BURST(p) (((p)&0xff) << 8)
490 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
491 #define MAX_PACKET(p) (((p)&0xffff) << 16)
492 #define MAX_PACKET_MASK (0xffff << 16)
493 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
496 #define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff)
497 #define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16)
498 #define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24)
499 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
502 #define EP_CTX_CYCLE_MASK (1 << 0)
503 #define SCTX_DEQ_MASK (~0xfL)
520 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
522 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
525 * It's useful to pre-allocate these for commands that cannot fail due to
526 * out-of-memory errors, like freeing streams.
545 #define DROP_EP(x) (0x1 << x)
547 #define ADD_EP(x) (0x1 << x)
550 /* 64-bit stream ring address, cycle state, and stream type */
552 /* offset 0x14 - 0x1f reserved for HC internal use */
556 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
557 #define SCT_FOR_CTX(p) (((p) & 0x7) << 1)
558 #define CTX_TO_SCT(p) (((p) >> 1) & 0x7)
560 #define SCT_SEC_TR 0
574 /* Number of streams, including stream 0 (which drivers can't use) */
593 * multi-TT hub) as a separate bandwidth domain. The direct memory interface
597 /* ep_interval is zero-based */
599 /* mult and num_packets are one-based */
646 /* Percentage of bus bandwidth reserved for non-periodic transfers */
663 #define SET_DEQ_PENDING (1 << 0)
675 /* ---- Related to URB cancellation ---- */
703 LS_OVERHEAD_TYPE = 0,
756 #define VDEV_PORT_ERROR BIT(0) /* Port error, link inactive */
789 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
792 /* 64-bit device addresses; we only write 32-bit addresses */
797 /* TODO: write function to set the 64-bit device DMA address */
805 /* 64-bit buffer address, or immediate data */
813 #define TRB_TO_SLOT_ID(p) (((p) >> 24) & 0xff)
814 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
816 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) /* Endpoint ID 1 - 31 */
817 #define EP_ID_FOR_TRB(p) (((p) & 0x1f) << 16)
819 #define TRB_TO_EP_INDEX(p) (TRB_TO_EP_ID(p) - 1) /* Endpoint index 0 - 30 */
820 #define EP_INDEX_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
823 #define EVENT_TRB_LEN(p) ((p) & 0xffffff)
825 /* Completion Code - only applicable for some types of TRBs */
826 #define COMP_CODE_MASK (0xff << 24)
828 #define COMP_INVALID 0
923 return "Stopped - Length Invalid"; in xhci_trb_comp_code_string()
925 return "Stopped - Short Packet"; in xhci_trb_comp_code_string()
946 /* 64-bit segment pointer*/
953 #define LINK_TOGGLE (0x1<<1)
964 #define COMP_PARAM(p) ((p) & 0xffffff) /* Command Completion Parameter */
966 /* Address device - disable SetAddress */
969 /* Configure Endpoint - Deconfigure */
972 /* Stop Ring - Transfer State Preserve */
981 #define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22)
982 #define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16)
985 #define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16)
988 #define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16)
991 #define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f)
992 #define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24)
1002 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
1008 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1009 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1010 #define SCT_FOR_TRB(p) (((p) & 0x7) << 1)
1016 /* Port ID - bits 31:24 */
1017 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1022 /* transfer_len bitmasks - bits 0:16 */
1023 #define TRB_LEN(p) ((p) & 0x1ffff)
1026 #define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17)
1027 /* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */
1029 /* Interrupter Target - which MSI-X vector to target the completion event at */
1030 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1031 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
1033 /* Cycle bit - indicates TRB ownership by HC or HCD */
1034 #define TRB_CYCLE (1<<0)
1064 #define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20)
1065 #define GET_FRAME_ID(p) (((p) >> 20) & 0x7ff)
1066 /* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */
1067 #define TRB_TBC(p) (((p) & 0x3) << 7)
1068 #define GET_TBC(p) (((p) >> 7) & 0x3)
1069 #define TRB_TLBPC(p) (((p) & 0xf) << 16)
1070 #define GET_TLBPC(p) (((p) >> 16) & 0xf)
1088 #define TRB_TYPE_BITMASK (0xfc00)
1105 /* Transfer Ring No-op (not for the command ring) */
1134 /* Force Header Command - generate a transaction or link management packet */
1136 /* No-op Command - not for transfer rings */
1138 /* TRB IDs 24-31 reserved */
1152 /* Device Notification Event - device sent function wake notification */
1154 /* MFINDEX Wrap Event - microframe counter wrapped */
1156 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1158 /* Nec vendor-specific command completion event. */
1181 return "No-Op"; in xhci_trb_type_string()
1211 return "No-Op Command"; in xhci_trb_type_string()
1238 /* Above, but for __le32 types -- can avoid work by swapping constants: */
1244 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1245 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1249 * since the command ring is 64-byte aligned.
1254 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1261 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
1262 (addr & (TRB_MAX_BUFF_SIZE - 1)))
1272 for (seg = head; seg != NULL; seg = (seg->next != head ? seg->next : NULL))
1280 /* Max packet sized bounce buffer for td-fragmant alignment */
1288 TD_DIRTY = 0,
1324 TYPE_CTRL = 0,
1379 /* 64-bit event ring segment address */
1389 /* xhci->event_ring keeps track of segment dma addresses */
1431 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1503 /* Cached register copies of read-only HC data */
1521 /* MSI-X/MSI vectors */
1533 #define CMD_RING_STATE_RUNNING (1 << 0)
1563 /* Host controller is dying - not responding to commands. "I'm not dead yet!"
1566 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1569 * they see this status (any time they drop and re-acquire xhci->lock).
1575 #define XHCI_STATE_DYING (1 << 0)
1579 #define XHCI_LINK_TRB_QUIRK BIT_ULL(0)
1667 /* platform-specific data -- must come last */
1698 primary_hcd = hcd->primary_hcd; in hcd_to_xhci()
1700 return (struct xhci_hcd *) (primary_hcd->hcd_priv); in hcd_to_xhci()
1705 return xhci->main_hcd; in xhci_to_hcd()
1710 if (xhci->shared_hcd) in xhci_get_usb3_hcd()
1711 return xhci->shared_hcd; in xhci_get_usb3_hcd()
1713 if (!xhci->usb2_rhub.num_ports) in xhci_get_usb3_hcd()
1714 return xhci->main_hcd; in xhci_get_usb3_hcd()
1728 return xhci->allow_single_roothub && in xhci_has_one_roothub()
1729 (!xhci->usb2_rhub.num_ports || !xhci->usb3_rhub.num_ports); in xhci_has_one_roothub()
1733 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1735 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1737 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1739 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1744 * Some xHCI implementations may support 64-bit address pointers. Registers
1745 * with 64-bit address pointers should be written to with dword accesses by
1746 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1747 * xHCI implementations that do not support 64-bit address pointers will ignore
1774 return (xhci->quirks & XHCI_LINK_TRB_QUIRK) || in xhci_link_chain_quirk()
1775 (type == TYPE_ISOC && (xhci->quirks & (XHCI_AMD_0x96_HOST | XHCI_NEC_HOST))); in xhci_link_chain_quirk()
1979 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id, in xhci_urb_to_transfer_ring()
1980 xhci_get_endpoint_index(&urb->ep->desc), in xhci_urb_to_transfer_ring()
1981 urb->stream_id); in xhci_urb_to_transfer_ring()
1991 if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) && in xhci_urb_suitable_for_idt()
1992 usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE && in xhci_urb_suitable_for_idt()
1993 urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE && in xhci_urb_suitable_for_idt()
1994 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) && in xhci_urb_suitable_for_idt()
1995 !urb->num_sgs) in xhci_urb_suitable_for_idt()
2055 field0 & 0xff, in xhci_decode_trb()
2056 (field0 & 0xff00) >> 8, in xhci_decode_trb()
2057 (field0 & 0xff000000) >> 24, in xhci_decode_trb()
2058 (field0 & 0xff0000) >> 16, in xhci_decode_trb()
2059 (field1 & 0xff00) >> 8, in xhci_decode_trb()
2060 field1 & 0xff, in xhci_decode_trb()
2061 (field1 & 0xff000000) >> 16 | in xhci_decode_trb()
2062 (field1 & 0xff0000) >> 16, in xhci_decode_trb()
2237 field2, field1, field0 & 0xffffffe0, in xhci_decode_trb()
2244 "type '%s' -> raw %08x %08x %08x %08x", in xhci_decode_trb()
2256 int ret = 0; in xhci_decode_ctrl_ctx()
2258 str[0] = '\0'; in xhci_decode_ctrl_ctx()
2288 int ret = 0; in xhci_decode_slot_context()
2299 s = "full-speed"; in xhci_decode_slot_context()
2302 s = "low-speed"; in xhci_decode_slot_context()
2305 s = "high-speed"; in xhci_decode_slot_context()
2308 s = "super-speed"; in xhci_decode_slot_context()
2311 s = "super-speed plus"; in xhci_decode_slot_context()
2316 mtt ? " multi-TT" : "", in xhci_decode_slot_context()
2372 ret = sprintf(str, "0x%08x ", portsc); in xhci_decode_portsc()
2374 if (portsc == ~(u32)0) in xhci_decode_portsc()
2378 portsc & PORT_POWER ? "Powered" : "Powered-off", in xhci_decode_portsc()
2379 portsc & PORT_CONNECT ? "Connected" : "Not-connected", in xhci_decode_portsc()
2387 ret += sprintf(str + ret, "In-Reset "); in xhci_decode_portsc()
2420 int ret = 0; in xhci_decode_usbsts()
2422 ret = sprintf(str, " 0x%08x", usbsts); in xhci_decode_usbsts()
2424 if (usbsts == ~(u32)0) in xhci_decode_usbsts()
2455 ep = (doorbell & 0xff); in xhci_decode_doorbell()
2458 if (slot == 0) { in xhci_decode_doorbell()
2463 if (ep > 0 && ep < 32) in xhci_decode_doorbell()
2467 else if (ep == 0 || ep < 248) in xhci_decode_doorbell()