28 #define CTRL0_IP_SW_RST	BIT(0)
31 #define CTRL1_IP_HOST_PDN	BIT(0)
34 #define CTRL2_IP_DEV_PDN	BIT(0)
42 #define STS1_SYSPLL_STABLE	BIT(0)
45 #define CAP_U3_PORT_NUM(p)	((p) & 0xff)
46 #define CAP_U2_PORT_NUM(p)	(((p) >> 8) & 0xff)
51 #define CTRL_U3_PORT_DIS	BIT(0)
56 #define CTRL_U2_PORT_DIS	BIT(0)
62 #define LS_EOF_CFG		0x930
63 #define LSEOF_OFFSET		0x89
65 #define FS_EOF_CFG		0x934
66 #define FSEOF_OFFSET		0x2e
68 #define SS_GEN1_EOF_CFG		0x93c
69 #define SSG1EOF_OFFSET		0x78
71 #define HFCNTR_CFG		0x944
72 #define ITP_DELTA_CLK		(0xa << 1)
74 #define FRMCNT_LEV1_RANG	(0x12b << 8)
77 #define HSCH_CFG1		0x960
80 #define SS_GEN2_EOF_CFG		0x990
81 #define SSG2EOF_OFFSET		0x3c
83 #define XSEOF_OFFSET_MASK	GENMASK(11, 0)
88 #define PERI_WK_CTRL1	0x4
89 #define WC1_IS_C(x)	(((x) & 0xf) << 26)  /* cycle debounce */
94 #define PERI_WK_CTRL0	0x0
95 #define WC0_IS_C(x)	((u32)(((x) & 0xf) << 28))  /* cycle debounce */
104 #define PERI_WK_CTRL0_8195	0x04
106 #define WC0_IS_C_95(x)		((u32)(((x) & 0x7) << 27))
111 #define PERI_WK_CTRL1_8195	0x20
112 #define WC1_IS_C_95(x)		((u32)(((x) & 0xf) << 28))
117 #define PERI_SSUSB_SPM_CTRL	0x0
207 	int u3_ports_disabled = 0;  in xhci_mtk_host_enable()
212 		return 0;  in xhci_mtk_host_enable()
220 	for (i = 0; i < mtk->num_u3_ports; i++) {  in xhci_mtk_host_enable()
221 		if ((0x1 << i) & mtk->u3p_dis_msk) {  in xhci_mtk_host_enable()
233 	for (i = 0; i < mtk->num_u2_ports; i++) {  in xhci_mtk_host_enable()
256 		dev_err(mtk->dev, "clocks are not stable (0x%x)\n", value);  in xhci_mtk_host_enable()
260 	return 0;  in xhci_mtk_host_enable()
271 		return 0;  in xhci_mtk_host_disable()
274 	for (i = 0; i < mtk->num_u3_ports; i++) {  in xhci_mtk_host_disable()
275 		if ((0x1 << i) & mtk->u3p_dis_msk)  in xhci_mtk_host_disable()
284 	for (i = 0; i < mtk->num_u2_ports; i++) {  in xhci_mtk_host_disable()
315 		return 0;  in xhci_mtk_ssusb_config()
351 		msk = WC1_IS_EN | WC1_IS_C(0xf) | WC1_IS_P;  in usb_wakeup_ip_sleep_set()
352 		val = enable ? (WC1_IS_EN | WC1_IS_C(0x8)) : 0;  in usb_wakeup_ip_sleep_set()
356 		msk = WC0_IS_EN | WC0_IS_C(0xf) | WC0_IS_P;  in usb_wakeup_ip_sleep_set()
357 		val = enable ? (WC0_IS_EN | WC0_IS_C(0x1)) : 0;  in usb_wakeup_ip_sleep_set()
362 		val = enable ? msk : 0;  in usb_wakeup_ip_sleep_set()
366 		msk = WC1_IS_EN_P0_95 | WC1_IS_C_95(0xf) | WC1_IS_P_95;  in usb_wakeup_ip_sleep_set()
367 		val = enable ? (WC1_IS_EN_P0_95 | WC1_IS_C_95(0x1)) : 0;  in usb_wakeup_ip_sleep_set()
371 		msk = WC0_IS_EN_P1_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95;  in usb_wakeup_ip_sleep_set()
372 		val = enable ? (WC0_IS_EN_P1_95 | WC0_IS_C_95(0x1)) : 0;  in usb_wakeup_ip_sleep_set()
376 		msk = WC0_IS_EN_P2_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95;  in usb_wakeup_ip_sleep_set()
377 		val = enable ? (WC0_IS_EN_P2_95 | WC0_IS_C_95(0x1)) : 0;  in usb_wakeup_ip_sleep_set()
381 		msk = WC0_IS_EN_P3_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95;  in usb_wakeup_ip_sleep_set()
382 		val = enable ? (WC0_IS_EN_P3_95 | WC0_IS_C_95(0x1)) : 0;  in usb_wakeup_ip_sleep_set()
387 		val = enable ? msk : 0;  in usb_wakeup_ip_sleep_set()
404 		return 0;  in usb_wakeup_of_property_parse()
407 				"mediatek,syscon-wakeup", 2, 0, &args);  in usb_wakeup_of_property_parse()
411 	mtk->uwk_reg_base = args.args[0];  in usb_wakeup_of_property_parse()
415 	dev_info(mtk->dev, "uwk - reg:0x%x, version:%d\n",  in usb_wakeup_of_property_parse()
431 	clks[0].id = "sys_ck";  in xhci_mtk_clks_get()
445 	supplies[0].supply = "vbus";  in xhci_mtk_vregs_get()
471 	if (xhci->hci_version < 0x100 && HCC_MAX_PSA(xhci->hcc_params) == 4)  in xhci_mtk_quirks()
542 	if (irq < 0) {  in xhci_mtk_probe()
547 		irq = platform_get_irq(pdev, 0);  in xhci_mtk_probe()
548 		if (irq < 0)  in xhci_mtk_probe()
663 	if (wakeup_irq > 0) {  in xhci_mtk_probe()
677 	return 0;  in xhci_mtk_probe()
761 	return 0;  in xhci_mtk_suspend()
798 	return 0;  in xhci_mtk_resume()
811 	int ret = 0;  in xhci_mtk_runtime_suspend()
820 	return ret ? -EBUSY : 0;  in xhci_mtk_runtime_suspend()
827 	int ret = 0;  in xhci_mtk_runtime_resume()