Lines Matching full:temp
259 u16 temp; in xhci_common_hub_descriptor() local
264 temp = 0; in xhci_common_hub_descriptor()
267 temp |= HUB_CHAR_INDV_PORT_LPSM; in xhci_common_hub_descriptor()
269 temp |= HUB_CHAR_NO_LPSM; in xhci_common_hub_descriptor()
272 temp |= HUB_CHAR_INDV_PORT_OCPM; in xhci_common_hub_descriptor()
275 desc->wHubCharacteristics = cpu_to_le16(temp); in xhci_common_hub_descriptor()
283 u16 temp; in xhci_usb2_hub_descriptor() local
293 temp = 1 + (ports / 8); in xhci_usb2_hub_descriptor()
294 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp; in xhci_usb2_hub_descriptor()
650 u32 temp; in xhci_set_port_power() local
653 temp = readl(port->addr); in xhci_set_port_power()
656 hcd->self.busnum, port->hcd_portnum + 1, on ? "ON" : "OFF", temp); in xhci_set_port_power()
658 temp = xhci_port_state_to_neutral(temp); in xhci_set_port_power()
662 writel(temp | PORT_POWER, port->addr); in xhci_set_port_power()
666 writel(temp & ~PORT_POWER, port->addr); in xhci_set_port_power()
670 temp = usb_acpi_power_manageable(hcd->self.root_hub, in xhci_set_port_power()
672 if (temp) in xhci_set_port_power()
681 u32 temp; in xhci_port_set_test_mode() local
686 temp = readl(port->addr + PORTPMSC); in xhci_port_set_test_mode()
687 temp |= test_mode << PORT_TEST_MODE_SHIFT; in xhci_port_set_test_mode()
688 writel(temp, port->addr + PORTPMSC); in xhci_port_set_test_mode()
802 u32 temp; in xhci_set_link_state() local
806 temp = xhci_port_state_to_neutral(portsc); in xhci_set_link_state()
807 temp &= ~PORT_PLS_MASK; in xhci_set_link_state()
808 temp |= PORT_LINK_STROBE | link_state; in xhci_set_link_state()
809 writel(temp, port->addr); in xhci_set_link_state()
813 portsc, temp); in xhci_set_link_state()
819 u32 temp; in xhci_set_remote_wake_mask() local
821 temp = readl(port->addr); in xhci_set_remote_wake_mask()
822 temp = xhci_port_state_to_neutral(temp); in xhci_set_remote_wake_mask()
825 temp |= PORT_WKCONN_E; in xhci_set_remote_wake_mask()
827 temp &= ~PORT_WKCONN_E; in xhci_set_remote_wake_mask()
830 temp |= PORT_WKDISC_E; in xhci_set_remote_wake_mask()
832 temp &= ~PORT_WKDISC_E; in xhci_set_remote_wake_mask()
835 temp |= PORT_WKOC_E; in xhci_set_remote_wake_mask()
837 temp &= ~PORT_WKOC_E; in xhci_set_remote_wake_mask()
839 writel(temp, port->addr); in xhci_set_remote_wake_mask()
846 u32 temp; in xhci_test_and_clear_bit() local
848 temp = readl(port->addr); in xhci_test_and_clear_bit()
849 if (temp & port_bit) { in xhci_test_and_clear_bit()
850 temp = xhci_port_state_to_neutral(temp); in xhci_test_and_clear_bit()
851 temp |= port_bit; in xhci_test_and_clear_bit()
852 writel(temp, port->addr); in xhci_test_and_clear_bit()
1212 u32 temp, status; in xhci_hub_control() local
1267 temp = readl(port->addr); in xhci_hub_control()
1268 if (temp == ~(u32)0) { in xhci_hub_control()
1273 trace_xhci_get_port_status(port, temp); in xhci_hub_control()
1274 status = xhci_get_port_status(hcd, bus_state, wIndex, temp, in xhci_hub_control()
1280 hcd->self.busnum, portnum1, temp, status); in xhci_hub_control()
1293 status = xhci_get_ext_port_status(temp, port_li); in xhci_hub_control()
1313 temp = readl(port->addr); in xhci_hub_control()
1314 if (temp == ~(u32)0) { in xhci_hub_control()
1319 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
1323 temp = readl(port->addr); in xhci_hub_control()
1324 if ((temp & PORT_PLS_MASK) != XDEV_U0) { in xhci_hub_control()
1335 temp = readl(port->addr); in xhci_hub_control()
1336 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) in xhci_hub_control()
1337 || (temp & PORT_PLS_MASK) >= XDEV_U3) { in xhci_hub_control()
1358 temp = readl(port->addr); in xhci_hub_control()
1362 temp = readl(port->addr); in xhci_hub_control()
1367 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
1372 temp |= PORT_CSC | PORT_PEC | PORT_WRC | in xhci_hub_control()
1375 writel(temp | PORT_PE, port->addr); in xhci_hub_control()
1376 temp = readl(port->addr); in xhci_hub_control()
1385 temp = readl(port->addr); in xhci_hub_control()
1409 if ((temp & PORT_CONNECT)) { in xhci_hub_control()
1418 temp = readl(port->addr); in xhci_hub_control()
1422 if (!(temp & PORT_PE)) { in xhci_hub_control()
1441 u32 pls = temp & PORT_PLS_MASK; in xhci_hub_control()
1466 temp = readl(port->addr); in xhci_hub_control()
1484 temp = readl(port->addr); in xhci_hub_control()
1485 if ((temp & PORT_PLS_MASK) == XDEV_U3) in xhci_hub_control()
1489 temp = readl(port->addr); in xhci_hub_control()
1503 temp = (temp | PORT_RESET); in xhci_hub_control()
1504 writel(temp, port->addr); in xhci_hub_control()
1506 temp = readl(port->addr); in xhci_hub_control()
1508 hcd->self.busnum, portnum1, temp); in xhci_hub_control()
1512 temp = readl(port->addr); in xhci_hub_control()
1514 hcd->self.busnum, portnum1, temp); in xhci_hub_control()
1517 temp |= PORT_WR; in xhci_hub_control()
1518 writel(temp, port->addr); in xhci_hub_control()
1519 temp = readl(port->addr); in xhci_hub_control()
1524 temp = readl(port->addr + PORTPMSC); in xhci_hub_control()
1525 temp &= ~PORT_U1_TIMEOUT_MASK; in xhci_hub_control()
1526 temp |= PORT_U1_TIMEOUT(timeout); in xhci_hub_control()
1527 writel(temp, port->addr + PORTPMSC); in xhci_hub_control()
1532 temp = readl(port->addr + PORTPMSC); in xhci_hub_control()
1533 temp &= ~PORT_U2_TIMEOUT_MASK; in xhci_hub_control()
1534 temp |= PORT_U2_TIMEOUT(timeout); in xhci_hub_control()
1535 writel(temp, port->addr + PORTPMSC); in xhci_hub_control()
1551 temp = readl(port->addr); in xhci_hub_control()
1560 temp = readl(port->addr); in xhci_hub_control()
1561 if (temp == ~(u32)0) { in xhci_hub_control()
1567 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
1570 temp = readl(port->addr); in xhci_hub_control()
1572 xhci_dbg(xhci, "PORTSC %04x\n", temp); in xhci_hub_control()
1573 if (temp & PORT_RESET) in xhci_hub_control()
1575 if ((temp & PORT_PLS_MASK) == XDEV_U3) { in xhci_hub_control()
1576 if ((temp & PORT_PE) == 0) in xhci_hub_control()
1608 port->addr, temp); in xhci_hub_control()
1644 u32 temp, status; in xhci_hub_status_data() local
1686 temp = readl(ports[i]->addr); in xhci_hub_status_data()
1687 if (temp == ~(u32)0) { in xhci_hub_status_data()
1692 trace_xhci_hub_status_data(ports[i], temp); in xhci_hub_status_data()
1694 if ((temp & mask) != 0 || in xhci_hub_status_data()
1701 if ((temp & PORT_RC)) in xhci_hub_status_data()
1703 if (temp & PORT_OC) in xhci_hub_status_data()
1881 u32 temp, portsc; in xhci_bus_resume() local
1900 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()
1901 temp &= ~CMD_EIE; in xhci_bus_resume()
1902 writel(temp, &xhci->op_regs->command); in xhci_bus_resume()
1978 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()
1979 temp |= CMD_EIE; in xhci_bus_resume()
1980 writel(temp, &xhci->op_regs->command); in xhci_bus_resume()
1981 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()