Lines Matching +full:5 +full:gbps
26 0x00050034, /* USB 3.0 SS Gen1x1 id:4 symmetric rx 5Gbps */
27 0x000500b4, /* USB 3.0 SS Gen1x1 id:4 symmetric tx 5Gbps */
28 0x000a4035, /* USB 3.1 SSP Gen2x1 id:5 symmetric rx 10Gbps */
29 0x000a40b5, /* USB 3.1 SSP Gen2x1 id:5 symmetric tx 10Gbps */
30 0x00054036, /* USB 3.2 SSP Gen1x2 id:6 symmetric rx 5Gbps */
31 0x000540b6, /* USB 3.2 SSP Gen1x2 id:6 symmetric tx 5Gbps */
32 0x000a4037, /* USB 3.2 SSP Gen2x2 id:7 symmetric rx 10Gbps */
33 0x000a40b7, /* USB 3.2 SSP Gen2x2 id:7 symmetric tx 10Gbps */
170 /* Shift to Gbps and set SSP Link Protocol if 10Gpbs */ in xhci_create_usb3x_bos_desc()
187 * is 20Gbps, but the BOS descriptor lane speed mantissa is in xhci_create_usb3x_bos_desc()
188 * 10Gbps. Check and modify the mantissa value to match the in xhci_create_usb3x_bos_desc()
194 * values. But the lane speed for gen1x2 is 5Gbps while in xhci_create_usb3x_bos_desc()
195 * gen2x1 is 10Gbps. If the previous PSI dword SSID is in xhci_create_usb3x_bos_desc()
196 * 5 and the PSIE and PSIM match with SSID 6, let's in xhci_create_usb3x_bos_desc()
204 XHCI_EXT_PORT_PSIV(prev) == 5 && in xhci_create_usb3x_bos_desc()
208 lane_mantissa = 5; in xhci_create_usb3x_bos_desc()
273 /* Bits 6:5 - no TTs in root ports */ in xhci_common_hub_descriptor()
402 * bits 5:8, 9, 14:15, 25:27
405 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
1891 msleep(5); in xhci_bus_resume()
1976 bus_state->next_statechange = jiffies + msecs_to_jiffies(5); in xhci_bus_resume()