Lines Matching +full:data +full:- +full:enable +full:- +full:active
1 // SPDX-License-Identifier: GPL-2.0+
4 * Intel PXA27x on-chip full speed USB device controller
28 #define UDCOTGICR 0x0018 /* UDC On-The-Go interrupt control */
33 #define UDCDRn(x) (0x0300 + ((x)<<2)) /* UDC Data Register */
36 #define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
37 #define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation
39 #define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol
41 #define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol
42 Enable */
43 #define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */
44 #define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */
46 #define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */
48 #define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface
51 #define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active
56 #define UDCCR_UDA (1 << 1) /* UDC Active */
57 #define UDCCR_UDE (1 << 0) /* UDC Enable */
60 #define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */
61 #define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */
62 #define UDCICR1_IERU (1 << 29) /* IntEn - Resume */
63 #define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */
64 #define UDCICR1_IERS (1 << 27) /* IntEn - Reset */
70 #define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */
71 #define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */
72 #define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */
73 #define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */
74 #define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */
79 Rising Edge Interrupt Enable */
81 Falling Edge Interrupt Enable */
83 Interrupt Enable */
85 Interrupt Enable */
87 Interrupt Enable */
89 Interrupt Enable */
91 Interrupt Enable */
93 Interrupt Enable */
94 #define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising
95 Edge Interrupt Enable */
96 #define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling
97 Edge Interrupt Enable */
99 Interrupt Enable */
101 Interrupt Enable */
104 #define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */
105 #define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */
107 #define UP2OCR_DPPDE (1 << 2) /* D+ Pull Down Enable */
108 #define UP2OCR_DMPDE (1 << 3) /* D- Pull Down Enable */
109 #define UP2OCR_DPPUE (1 << 4) /* D+ Pull Up Enable */
110 #define UP2OCR_DMPUE (1 << 5) /* D- Pull Up Enable */
111 #define UP2OCR_DPPUBE (1 << 6) /* D+ Pull Up Bypass Enable */
112 #define UP2OCR_DMPUBE (1 << 7) /* D- Pull Up Bypass Enable */
114 #define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */
115 #define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */
117 #define UP2OCR_HXOE (1 << 17) /* Transceiver Output Enable */
118 #define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */
121 #define UDCCSR0_AREN (1 << 8) /* Ack Response Enable */
122 #define UDCCSR0_SA (1 << 7) /* Setup Active */
126 #define UDCCSR0_DME (1 << 3) /* DMA Enable */
131 #define UDCCSR_DPE (1 << 9) /* Data Packet Error */
138 #define UDCCSR_DME (1 << 3) /* DMA Enable */
160 #define UDCCONR_DE (1 << 1) /* Double Buffering Enable */
161 #define UDCCONR_EE (1 << 0) /* Endpoint Enable */
172 * UDCDR = UDC Endpoint Data Register (the fifo)
174 #define ofs_UDCCR(ep) (UDCCRn(ep->idx))
175 #define ofs_UDCCSR(ep) (UDCCSRn(ep->idx))
176 #define ofs_UDCBCR(ep) (UDCBCRn(ep->idx))
177 #define ofs_UDCDR(ep) (UDCDRn(ep->idx))
181 __raw_readl((ep)->dev->regs + ofs_##reg(ep))
183 __raw_writel((value), ep->dev->regs + ofs_##reg(ep))
185 __raw_readb((ep)->dev->regs + ofs_##reg(ep))
187 __raw_writeb((value), ep->dev->regs + ofs_##reg(ep))
189 __raw_readl((dev)->regs + (reg))
191 __raw_writel((value), (udc)->regs + (reg))
198 #define EPIDX(ep) (ep->idx)
199 #define EPADDR(ep) (ep->addr)
200 #define EPXFERTYPE(ep) (ep->type)
201 #define EPNAME(ep) (ep->name)
202 #define is_ep0(ep) (!ep->idx)
220 * - "ep1-in" matches pxa endpoint EPA (which is an IN ep at addr 1, when
222 * - "ep1-in" matches pxa endpoint EPB (which is an IN ep at addr 1, when
224 * - "ep1-in" matches pxa endpoint EPC (which is an IN ep at addr 1, when
250 #define USB_EP_IN_BULK(n) USB_EP_BULK(n, "ep" #n "in-bulk", 1, \
252 #define USB_EP_OUT_BULK(n) USB_EP_BULK(n, "ep" #n "out-bulk", 0, \
254 #define USB_EP_IN_ISO(n) USB_EP_ISO(n, "ep" #n "in-iso", 1, \
256 #define USB_EP_OUT_ISO(n) USB_EP_ISO(n, "ep" #n "out-iso", 0, \
258 #define USB_EP_IN_INT(n) USB_EP_INT(n, "ep" #n "in-int", 1, \
299 * struct udc_usb_ep - container of each usb_ep structure
313 * struct pxa_ep - pxa endpoint
316 * @lock: lock to pxa_ep data (queues and stats)
320 * irq->handle_ep()->req_done()->req.complete()->pxa_ep_queue()->handle_ep()
322 * pxa_ep_queue()->handle_ep()->req_done()->req.complete()->pxa_ep_queue()
327 * @config: configuration in which this endpoint is active
328 * @interface: interface in which this endpoint is active
329 * @alternate: altsetting in which this endpoint is active
357 * Specific pxa endpoint data, needed for hardware initialization
375 * struct pxa27x_request - container of each usb_request structure
379 * @queue: linked list of requests, linked on pxa_ep->queue
404 #define EP0_STNAME(udc) ep0_state_name[(udc)->ep0state]
418 #define NR_USB_ENDPOINTS (1 + 5) /* ep0 + ep1in-bulk + .. + ep3in-iso */
422 * struct pxa_udc - udc structure
439 * @config: UDC active configuration
488 dev_dbg(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg)
490 dev_vdbg(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg)
492 dev_err(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg)
494 dev_info(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg)
496 dev_warn(ep->dev->dev, "%s:%s:" fmt, EPNAME(ep), __func__, ## arg)