34 #define UDC_DEVCTL_ADDR		0x404	/* Device control */  macro
505 	pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);  in pch_udc_rmt_wakeup()
507 	pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);  in pch_udc_rmt_wakeup()
545 	pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);  in pch_udc_set_disconnect()
555 	pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);  in pch_udc_clear_disconnect()
556 	pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);  in pch_udc_clear_disconnect()
559 	pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);  in pch_udc_clear_disconnect()
579 	pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);  in pch_udc_reconnect()
580 	pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);  in pch_udc_reconnect()
583 	pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);  in pch_udc_reconnect()
743 		pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE);  in pch_udc_set_dma()
745 		pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE);  in pch_udc_set_dma()
759 		pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE);  in pch_udc_clear_dma()
761 		pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE);  in pch_udc_clear_dma()
771 	pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_CSR_DONE);  in pch_udc_set_csr_done()
1071 	pch_udc_bit_set(dev, UDC_DEVCTL_ADDR,  in pch_udc_init()