Lines Matching +full:0 +full:xbfc
16 #define FUSB300_OFFSET_GCR 0x00
17 #define FUSB300_OFFSET_GTM 0x04
18 #define FUSB300_OFFSET_DAR 0x08
19 #define FUSB300_OFFSET_CSR 0x0C
20 #define FUSB300_OFFSET_CXPORT 0x10
21 #define FUSB300_OFFSET_EPSET0(n) (0x20 + (n - 1) * 0x30)
22 #define FUSB300_OFFSET_EPSET1(n) (0x24 + (n - 1) * 0x30)
23 #define FUSB300_OFFSET_EPSET2(n) (0x28 + (n - 1) * 0x30)
24 #define FUSB300_OFFSET_EPFFR(n) (0x2c + (n - 1) * 0x30)
25 #define FUSB300_OFFSET_EPSTRID(n) (0x40 + (n - 1) * 0x30)
26 #define FUSB300_OFFSET_HSPTM 0x300
27 #define FUSB300_OFFSET_HSCR 0x304
28 #define FUSB300_OFFSET_SSCR0 0x308
29 #define FUSB300_OFFSET_SSCR1 0x30C
30 #define FUSB300_OFFSET_TT 0x310
31 #define FUSB300_OFFSET_DEVNOTF 0x314
32 #define FUSB300_OFFSET_DNC1 0x318
33 #define FUSB300_OFFSET_CS 0x31C
34 #define FUSB300_OFFSET_SOF 0x324
35 #define FUSB300_OFFSET_EFCS 0x328
36 #define FUSB300_OFFSET_IGR0 0x400
37 #define FUSB300_OFFSET_IGR1 0x404
38 #define FUSB300_OFFSET_IGR2 0x408
39 #define FUSB300_OFFSET_IGR3 0x40C
40 #define FUSB300_OFFSET_IGR4 0x410
41 #define FUSB300_OFFSET_IGR5 0x414
42 #define FUSB300_OFFSET_IGER0 0x420
43 #define FUSB300_OFFSET_IGER1 0x424
44 #define FUSB300_OFFSET_IGER2 0x428
45 #define FUSB300_OFFSET_IGER3 0x42C
46 #define FUSB300_OFFSET_IGER4 0x430
47 #define FUSB300_OFFSET_IGER5 0x434
48 #define FUSB300_OFFSET_DMAHMER 0x500
49 #define FUSB300_OFFSET_EPPRDRDY 0x504
50 #define FUSB300_OFFSET_DMAEPMR 0x508
51 #define FUSB300_OFFSET_DMAENR 0x50C
52 #define FUSB300_OFFSET_DMAAPR 0x510
53 #define FUSB300_OFFSET_AHBCR 0x514
54 #define FUSB300_OFFSET_EPPRD_W0(n) (0x520 + (n - 1) * 0x10)
55 #define FUSB300_OFFSET_EPPRD_W1(n) (0x524 + (n - 1) * 0x10)
56 #define FUSB300_OFFSET_EPPRD_W2(n) (0x528 + (n - 1) * 0x10)
57 #define FUSB300_OFFSET_EPRD_PTR(n) (0x52C + (n - 1) * 0x10)
58 #define FUSB300_OFFSET_BUFDBG_START 0x800
59 #define FUSB300_OFFSET_BUFDBG_END 0xBFC
60 #define FUSB300_OFFSET_EPPORT(n) (0x1010 + (n - 1) * 0x10)
72 #define FUSB300_GCR_DEVEN_FS 0x3
73 #define FUSB300_GCR_DEVEN_HS 0x2
74 #define FUSB300_GCR_DEVEN_SS 0x1
75 #define FUSB300_GCR_DEVDIS 0x0
76 #define FUSB300_GCR_DEVEN_MSK 0x3
83 #define FUSB300_GTM_TST_CUR_EP_ENTRY(n) ((n & 0xF) << 12)
84 #define FUSB300_GTM_TST_EP_ENTRY(n) ((n & 0xF) << 8)
85 #define FUSB300_GTM_TST_EP_NUM(n) ((n & 0xF) << 4)
87 #define FUSB300_GTM_TSTMODE (1 << 0)
93 #define FUSB300_DAR_DRVADDR(x) (x & 0x7F)
94 #define FUSB300_DAR_DRVADDR_MSK 0x7F
100 #define FUSB300_CSR_LEN(x) ((x & 0xFFFF) << 8)
101 #define FUSB300_CSR_LEN_MSK (0xFFFF << 8)
106 #define FUSB300_CSR_DONE (1 << 0)
109 * * EPn Setting 0 (EPn_SET0, offset = 020H+(n-1)*30H, n=1~15 )
113 #define FUSB300_EPSET0_STL (1 << 0)
118 #define FUSB300_EPSET1_START_ENTRY(x) ((x & 0xFF) << 24)
119 #define FUSB300_EPSET1_START_ENTRY_MSK (0xFF << 24)
120 #define FUSB300_EPSET1_FIFOENTRY(x) ((x & 0x1F) << 12)
121 #define FUSB300_EPSET1_FIFOENTRY_MSK (0x1f << 12)
122 #define FUSB300_EPSET1_INTERVAL(x) ((x & 0x7) << 6)
123 #define FUSB300_EPSET1_BWNUM(x) ((x & 0x3) << 4)
127 #define FUSB300_EPSET1_TYPE(x) ((x & 0x3) << 2)
128 #define FUSB300_EPSET1_TYPE_MSK (0x3 << 2)
129 #define FUSB300_EPSET1_DIROUT (0 << 1)
131 #define FUSB300_EPSET1_DIR(x) ((x & 0x1) << 1)
133 #define FUSB300_EPSET1_DIR_MSK ((0x1) << 1)
134 #define FUSB300_EPSET1_ACTDIS 0
140 #define FUSB300_EPSET2_ADDROFS(x) ((x & 0x7FFF) << 16)
141 #define FUSB300_EPSET2_ADDROFS_MSK (0x7fff << 16)
142 #define FUSB300_EPSET2_MPS(x) (x & 0x7FF)
143 #define FUSB300_EPSET2_MPS_MSK 0x7FF
151 #define FUSB300_FFR_BYCNT 0x1FFFF
157 #define FUSB300_STRID_STRID(x) (x & 0xFFFF)
166 #define FUSB300_HSPTM_TSTJSTA (1 << 0)
177 #define FUSB300_HSCR_IDLECNT_0MS 0
187 * * SS Controller Register 0 (offset = 308H)
189 #define FUSB300_SSCR0_MAX_INTERVAL(x) ((x & 0x7) << 4)
191 #define FUSB300_SSCR0_U1_FUN_EN (1 << 0)
204 #define FUSB300_SSCR1_U1_ENTRY_EN (1 << 0)
211 #define FUSB300_SSCR2_U2_INACT_TIMEOUT(x) ((x & 0xFF) << 16)
212 #define FUSB300_SSCR2_U1TIMEOUT(x) ((x & 0xFF) << 8)
213 #define FUSB300_SSCR2_U2TIMEOUT(x) (x & 0xFF)
218 #define FUSB300_DEVNOTF_CONTEXT0(x) ((x & 0xFFFFFF) << 8)
219 #define FUSB300_DEVNOTF_TYPE_DIS 0
236 #define FUSB300_VSIC_VCTL(x) (x & 0x3F)
241 #define FUSB300_SOF_MASK_TIMER_HS 0x044c
242 #define FUSB300_SOF_MASK_TIMER_FS 0x2710
250 #define FUSB300_EFCS_PM_STATE_U0 0
253 * *Interrupt Group 0 Register (offset = 400H)
322 #define FUSB300_IGR1_INTGRP2 (1 << 0)
356 #define FUSB300_IGR2_EP1_STR_PRIME_INT (1 << 0)
396 #define FUSB300_IGR3_EP7_STR_PRIME_INT (1 << 0)
437 #define FUSB300_IGR4_EP13_STR_PRIME_INT (1 << 0)
451 * *Interrupt Enable Group 0 Register (offset = 420H)
520 #define FUSB300_IGER1_INTGRP2 (1 << 0)
574 #define FUSB300_AHBBCR_S1_1entry (0 << 12)
578 #define FUSB300_AHBBCR_S0_1entry (0 << 8)
582 #define FUSB300_AHBBCR_M1_BURST_SINGLE (0 << 4)
587 #define FUSB300_AHBBCR_M0_BURST_SINGLE 0
594 /* WORD 0 Data Structure of PRD Table */
604 #define FUSB300_EPPRD0_BTC(n) (n & 0xFFFFFF)
612 #define SS_CTL_MAX_PACKET_SIZE 0x200
613 #define SS_BULK_MAX_PACKET_SIZE 0x400
614 #define SS_INT_MAX_PACKET_SIZE 0x400
615 #define SS_ISO_MAX_PACKET_SIZE 0x400
617 #define HS_BULK_MAX_PACKET_SIZE 0x200
618 #define HS_CTL_MAX_PACKET_SIZE 0x40
619 #define HS_INT_MAX_PACKET_SIZE 0x400
620 #define HS_ISO_MAX_PACKET_SIZE 0x400
666 u8 ep0_dir; /* 0/0x80 out/in */