Lines Matching full:csr
112 u32 csr; in proc_ep_show() local
119 csr = __raw_readl(ep->creg); in proc_ep_show()
132 seq_printf(s, "csr %08x rxbytes=%d %s %s %s" EIGHTBITS "\n", in proc_ep_show()
133 csr, in proc_ep_show()
134 (csr & 0x07ff0000) >> 16, in proc_ep_show()
135 str_enabled_disabled(csr & (1 << 15)), in proc_ep_show()
136 (csr & (1 << 11)) ? "DATA1" : "DATA0", in proc_ep_show()
137 types[(csr & 0x700) >> 8], in proc_ep_show()
140 (!(csr & 0x700)) in proc_ep_show()
141 ? ((csr & (1 << 7)) ? " IN" : " OUT") in proc_ep_show()
143 (csr & (1 << 6)) ? " rxdatabk1" : "", in proc_ep_show()
144 (csr & (1 << 5)) ? " forcestall" : "", in proc_ep_show()
145 (csr & (1 << 4)) ? " txpktrdy" : "", in proc_ep_show()
147 (csr & (1 << 3)) ? " stallsent" : "", in proc_ep_show()
148 (csr & (1 << 2)) ? " rxsetup" : "", in proc_ep_show()
149 (csr & (1 << 1)) ? " rxdatabk0" : "", in proc_ep_show()
150 (csr & (1 << 0)) ? " txcomp" : ""); in proc_ep_show()
290 * Endpoint FIFO CSR bits have a mix of bits, making it unsafe to just write
315 u32 csr; in read_fifo() local
327 csr = __raw_readl(creg); in read_fifo()
328 if ((csr & RX_DATA_READY) == 0) in read_fifo()
331 count = (csr & AT91_UDP_RXBYTECNT) >> 16; in read_fifo()
342 csr |= CLR_FX; in read_fifo()
345 csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK0); in read_fifo()
348 csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK1); in read_fifo()
352 csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK0); in read_fifo()
353 __raw_writel(csr, creg); in read_fifo()
372 * CSR returns bad RXCOUNT when read too soon after updating in read_fifo()
375 csr = __raw_readl(creg); in read_fifo()
389 u32 csr = __raw_readl(creg); in write_fifo() local
406 if (unlikely(csr & (AT91_UDP_TXCOMP | AT91_UDP_TXPKTRDY))) { in write_fifo()
407 if (csr & AT91_UDP_TXCOMP) { in write_fifo()
408 csr |= CLR_FX; in write_fifo()
409 csr &= ~(SET_FX | AT91_UDP_TXCOMP); in write_fifo()
410 __raw_writel(csr, creg); in write_fifo()
411 csr = __raw_readl(creg); in write_fifo()
413 if (csr & AT91_UDP_TXPKTRDY) in write_fifo()
442 csr &= ~SET_FX; in write_fifo()
443 csr |= CLR_FX | AT91_UDP_TXPKTRDY; in write_fifo()
444 __raw_writel(csr, creg); in write_fifo()
742 u32 csr; in at91_ep_set_halt() local
752 csr = __raw_readl(creg); in at91_ep_set_halt()
759 if (ep->is_in && (!list_empty(&ep->queue) || (csr >> 16) != 0)) in at91_ep_set_halt()
762 csr |= CLR_FX; in at91_ep_set_halt()
763 csr &= ~SET_FX; in at91_ep_set_halt()
765 csr |= AT91_UDP_FORCESTALL; in at91_ep_set_halt()
770 csr &= ~AT91_UDP_FORCESTALL; in at91_ep_set_halt()
772 __raw_writel(csr, creg); in at91_ep_set_halt()
1010 u32 csr = __raw_readl(creg); in handle_ep() local
1019 if (csr & (AT91_UDP_STALLSENT | AT91_UDP_TXCOMP)) { in handle_ep()
1020 csr |= CLR_FX; in handle_ep()
1021 csr &= ~(SET_FX | AT91_UDP_STALLSENT | AT91_UDP_TXCOMP); in handle_ep()
1022 __raw_writel(csr, creg); in handle_ep()
1028 if (csr & AT91_UDP_STALLSENT) { in handle_ep()
1032 csr |= CLR_FX; in handle_ep()
1033 csr &= ~(SET_FX | AT91_UDP_STALLSENT); in handle_ep()
1034 __raw_writel(csr, creg); in handle_ep()
1035 csr = __raw_readl(creg); in handle_ep()
1037 if (req && (csr & RX_DATA_READY)) in handle_ep()
1048 static void handle_setup(struct at91_udc *udc, struct at91_ep *ep, u32 csr) in handle_setup() argument
1058 rxcount = (csr & AT91_UDP_RXBYTECNT) >> 16; in handle_setup()
1063 csr |= AT91_UDP_DIR; in handle_setup()
1066 csr &= ~AT91_UDP_DIR; in handle_setup()
1071 ERR("SETUP len %d, csr %08x\n", rxcount, csr); in handle_setup()
1074 csr |= CLR_FX; in handle_setup()
1075 csr &= ~(SET_FX | AT91_UDP_RXSETUP); in handle_setup()
1076 __raw_writel(csr, creg); in handle_setup()
1096 csr = __raw_readl(creg); in handle_setup()
1097 csr |= CLR_FX; in handle_setup()
1098 csr &= ~SET_FX; in handle_setup()
1103 __raw_writel(csr | AT91_UDP_TXPKTRDY, creg); in handle_setup()
1259 csr |= AT91_UDP_FORCESTALL; in handle_setup()
1260 __raw_writel(csr, creg); in handle_setup()
1269 csr |= AT91_UDP_TXPKTRDY; in handle_setup()
1270 __raw_writel(csr, creg); in handle_setup()
1278 u32 csr = __raw_readl(creg); in handle_ep0() local
1281 if (unlikely(csr & AT91_UDP_STALLSENT)) { in handle_ep0()
1284 csr |= CLR_FX; in handle_ep0()
1285 csr &= ~(SET_FX | AT91_UDP_STALLSENT | AT91_UDP_FORCESTALL); in handle_ep0()
1286 __raw_writel(csr, creg); in handle_ep0()
1288 csr = __raw_readl(creg); in handle_ep0()
1290 if (csr & AT91_UDP_RXSETUP) { in handle_ep0()
1293 handle_setup(udc, ep0, csr); in handle_ep0()
1303 if (csr & AT91_UDP_TXCOMP) { in handle_ep0()
1304 csr |= CLR_FX; in handle_ep0()
1305 csr &= ~(SET_FX | AT91_UDP_TXCOMP); in handle_ep0()
1322 __raw_writel(csr, creg); in handle_ep0()
1346 else if (csr & AT91_UDP_RX_DATA_BK0) { in handle_ep0()
1347 csr |= CLR_FX; in handle_ep0()
1348 csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK0); in handle_ep0()
1356 csr = __raw_readl(creg); in handle_ep0()
1357 csr &= ~SET_FX; in handle_ep0()
1358 csr |= CLR_FX | AT91_UDP_TXPKTRDY; in handle_ep0()
1359 __raw_writel(csr, creg); in handle_ep0()
1381 __raw_writel(csr | AT91_UDP_FORCESTALL, creg); in handle_ep0()
1388 __raw_writel(csr, creg); in handle_ep0()