Lines Matching +full:double +full:- +full:buffering

1 // SPDX-License-Identifier: GPL-2.0+
3  * amd5536.h -- header for AMD 5536 UDC high/full speed USB device controller
56 /* Global CSR's -------------------------------------------------------------*/
83 /* Device Config Register ---------------------------------------------------*/
106 /* Device Control Register --------------------------------------------------*/
130 /* Device Status Register ---------------------------------------------------*/
157 /* Device Interrupt Register ------------------------------------------------*/
169 /* Device Interrupt Mask Register -------------------------------------------*/
174 /* Endpoint Interrupt Register ----------------------------------------------*/
193 /* Endpoint Interrupt Mask Register -----------------------------------------*/
202 /* mask non-EP0 endpoints */
207 /* Endpoint-specific CSR's --------------------------------------------------*/
231 /* Endpoint Status Registers ------------------------------------------------*/
250 /* Endpoint Buffer Size IN/ Receive Packet Frame Number OUT Registers ------*/
264 /* EPin data fifo size = 1024 bytes DOUBLE BUFFERING */
269 /* EPin fullspeed data fifo size = 128 bytes DOUBLE BUFFERING */
275 /* Endpoint Buffer Size OUT/Max Packet Size Registers -----------------------*/
293  * Endpoint dma descriptors ------------------------------------------------
346 /* un-usable DMA address */
349 /* other Endpoint register addresses and values-----------------------------*/
361 /* UDC CSR regs are aligned but AHB regs not - offset for OUT EP's */
367 /* Rx fifo address and size = 1k -------------------------------------------*/
371 /* Tx fifo address and size = 1.5k -----------------------------------------*/
375 /* default data endpoints --------------------------------------------------*/
380 /* general constants -------------------------------------------------------*/
386 /*---------------------------------------------------------------------------*/
390 	/* sca - setup command address */
618  *---------------------------------------------------------------------------
633  * set bitfield value in zero-initialized u32 u32Val
646 /* SET and GET bits in u32 values ------------------------------------------*/
651 /* debug macros ------------------------------------------------------------*/
653 #define DBG(udc , args...)	dev_dbg(udc->dev, args)