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1 /* SPDX-License-Identifier: GPL-2.0 */
15 #include <linux/io-64-nonatomic-lo-hi.h>
19 /* Max number slots - only 1 is allowed. */
28 #define CDNSP_DEFAULT_BESL 0
43 * struct cdnsp_cap_regs - CDNSP Registers.
46 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
47 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
48 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
49 * @hcc_params: HCCPARAMS - Capability Parameters
50 * @db_off: DBOFF - Doorbell array offset
51 * @run_regs_off: RTSOFF - Runtime register space offset
63 /* Reserved up to (CAPLENGTH - 0x1C) */
67 /* bits 7:0 - how long is the Capabilities register. */
68 #define HC_LENGTH(p) (((p) >> 00) & GENMASK(7, 0))
72 /* HCSPARAMS1 - hcs_params1 - bitmasks */
73 /* bits 0:7, Max Device Endpoints */
74 #define HCS_ENDPOINTS_MASK GENMASK(7, 0)
75 #define HCS_ENDPOINTS(p) (((p) & HCS_ENDPOINTS_MASK) >> 0)
78 #define HCC_PARAMS_OFFSET 0x10
80 /* HCCPARAMS - hcc_params - bitmasks */
81 /* 1: device controller can use 64-bit address pointers. */
82 #define HCC_64BIT_ADDR(p) ((p) & BIT(0))
83 /* 1: device controller uses 64-byte Device Context structures. */
85 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15. */
86 #define HCC_MAX_PSA(p) ((((p) >> 12) & 0xf) + 1)
92 /* db_off bitmask - bits 0:1 reserved. */
95 /* run_regs_off bitmask - bits 0:4 reserved. */
99 * struct cdnsp_op_regs - Device Controller Operational Registers.
100 * @command: USBCMD - Controller command register.
101 * @status: USBSTS - Controller status register.
105 * @dnctrl: DNCTRL - Device notification control register.
106 * @cmd_ring: CRP - 64-bit Command Ring Pointer.
107 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer.
108 * @config_reg: CONFIG - Configure Register
109 * @port_reg_base: PORTSCn - base address for Port Status and Control
123 /* rsvd: offset 0x20-2F. */
127 /* rsvd: offset 0x3C-3FF. */
137 * struct cdnsp_port_regs - Port Registers.
138 * @portsc: PORTSC - Port Status and Control Register.
139 * @portpmsc: PORTPMSC - Port Power Managements Status and Control Register.
140 * @portli: PORTLI - Port Link Info register.
151 * registers: 0 (connect status) and 10:13 (port speed).
152 * These bits are also sticky - meaning they're in the AUX well and they aren't
158 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
164 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
170 /* USBCMD - USB command - bitmasks. */
171 /* Run/Stop, controller execution - do not write unless controller is halted.*/
172 #define CMD_R_S BIT(0)
174 * Reset device controller - resets internal controller state machine and all
178 /* Event Interrupt Enable - a '1' allows interrupts from the controller. */
181 * Device System Error Interrupt Enable - get out-of-band signal for
189 * Enable Wrap Event - '1' means device controller generates an event
200 /* USBSTS - USB status - bitmasks */
201 /* controller not running - set to 1 when run/stop bit is cleared. */
202 #define STS_HALT BIT(0)
208 /* event interrupt - clear this prior to clearing any IP flags in IR set.*/
212 /* save state status - '1' means device controller is saving state. */
214 /* restore state status - '1' means controllers is restoring state. */
223 /* CRCR - Command Ring Control Register - cmd_ring bitmasks. */
224 /* bit 0 is the command ring cycle state. */
225 #define CMD_RING_CS BIT(0)
226 /* stop ring immediately - abort the currently executing command. */
236 /* Command Ring pointer - bit mask for the lower 32 bits. */
237 #define CMD_RING_RSVD_BITS GENMASK(5, 0)
239 /* CONFIG - Configure Register - config_reg bitmasks. */
240 /* bits 0:7 - maximum number of device slots enabled. */
241 #define MAX_DEVS GENMASK(7, 0)
245 /* PORTSC - Port Status and Control Register - port_reg_base bitmasks */
247 #define PORT_CONNECT BIT(0)
253 * Port Link State - bits 5:8
258 #define XDEV_U0 (0x0 << 5)
259 #define XDEV_U1 (0x1 << 5)
260 #define XDEV_U2 (0x2 << 5)
261 #define XDEV_U3 (0x3 << 5)
262 #define XDEV_DISABLED (0x4 << 5)
263 #define XDEV_RXDETECT (0x5 << 5)
264 #define XDEV_INACTIVE (0x6 << 5)
265 #define XDEV_POLLING (0x7 << 5)
266 #define XDEV_RECOVERY (0x8 << 5)
267 #define XDEV_HOT_RESET (0x9 << 5)
268 #define XDEV_COMP_MODE (0xa << 5)
269 #define XDEV_TEST_MODE (0xb << 5)
270 #define XDEV_RESUME (0xf << 5)
275 * 0 - undefined speed - port hasn't be initialized by a reset yet
276 * 1 - full speed
277 * 2 - Reserved (Low Speed not supported
278 * 3 - high speed
279 * 4 - super speed
280 * 5 - super speed
281 * 6-15 reserved
284 #define XDEV_FS (0x1 << 10)
285 #define XDEV_HS (0x3 << 10)
286 #define XDEV_SS (0x4 << 10)
287 #define XDEV_SSP (0x5 << 10)
288 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0 << 10))
294 #define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f)
295 /* Port Link State Write Strobe - set this when changing link state */
301 /* 1: reset change - 1 to 0 transition of PORT_RESET */
304 * port link status change - set on some port link state transitions:
306 * ----------------------------------------------------------------------------
307 * - U3 to Resume Wakeup signaling from a device
308 * - Resume to Recovery to U0 USB 3.0 device resume
309 * - Resume to U0 USB 2.0 device resume
310 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
311 * - U3 to U0 Software resume of USB 2.0 device complete
312 * - U2 to U0 L1 resume of USB 2.1 device complete
313 * - U0 to U0 L1 entry rejection by USB 2.1 device
314 * - U0 to disabled L1 entry error with USB 2.1 device
315 * - Any state to inactive Error on USB 3.0 port
318 /* Port configure error change - port failed to configure its link partner. */
329 /* PORTPMSCUSB3 - Port Power Management Status and Control - bitmasks. */
331 #define PORT_U1_TIMEOUT_MASK GENMASK(7, 0)
337 /* PORTPMSCUSB2 - Port Power Management Status and Control - bitmasks. */
338 #define PORT_L1S_MASK GENMASK(2, 0)
357 * struct cdnsp_intr_reg - Interrupt Register Set.
358 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
360 * @irq_control: IMOD - Interrupt Moderation Register.
366 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
382 /* IMAN - Interrupt Management Register - irq_pending bitmasks l. */
384 #define IMAN_IP BIT(0)
389 /* IMOD - Interrupter Moderation Register - irq_control bitmasks. */
395 #define IMOD_INTERVAL_MASK GENMASK(15, 0)
396 /* Counter used to count down the time to the next interrupt - HW use only */
398 #define IMOD_DEFAULT_INTERVAL 0
406 * Dequeue ERST Segment Index (DESI) - Segment number (or alias)
409 #define ERST_DESI_MASK GENMASK(2, 0)
410 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced. */
412 #define ERST_PTR_MASK GENMASK(3, 0)
416 * @microframe_index: MFINDEX - current microframe number.
430 * USB2.0 Port Peripheral Configuration Registers.
450 #define EXT_CAPS_ID(p) (((p) >> 0) & GENMASK(7, 0))
451 #define EXT_CAPS_NEXT(p) (((p) >> 8) & GENMASK(7, 0))
452 /* Extended capability IDs - ID 0 reserved */
456 #define EXT_CAP_CFG_DEV_20PORT_CAP_ID 0xC1
459 * TRB prepared when USBSSP operates in USB2.0 mode.
463 * Setting this bit to '1' forces Full Speed when USBSSP operates in USB2.0
466 #define PORT_REG6_FORCE_FS BIT(0)
482 #define D_XEC_CFG_3XPORT_CAP 0xC0
484 #define CFG_3XPORT_U1_PIPE_CLK_GATE_EN BIT(0)
487 #define RTL_REV_CAP 0xC4
489 #define RTL_REV_CAP_RX_BUFF_SIZE BITMASK(15, 0)
491 #define RTL_REV_CAP_TX_BUFF_SIZE BITMASK(15, 0)
493 #define CDNSP_VER_1 0x00000000
494 #define CDNSP_VER_2 0x10000000
497 (readl(&(pdev)->rev_cap->ep_supported) & \
498 (BIT(ep_num) << ((dir) ? 0 : 16)))
501 * struct cdnsp_rev_cap - controller capabilities.
518 /* USB2.0 Port Peripheral Configuration Registers. */
519 #define D_XEC_PRE_REGS_CAP 0xC8
520 #define REG_CHICKEN_BITS_2_OFFSET 0x48
524 #define XBUF_CAP_ID 0xCB
525 #define XBUF_RX_TAG_MASK_0_OFFSET 0x1C
526 #define XBUF_RX_TAG_MASK_1_OFFSET 0x24
527 #define XBUF_TX_CMD_OFFSET 0x2C
533 * Bits 0 - 7: Endpoint target.
534 * Bits 8 - 15: RsvdZ.
535 * Bits 16 - 31: Stream ID.
542 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
543 #define DB_VALUE_EP0_OUT(ep, stream) ((ep) & 0xff)
544 #define DB_VALUE_CMD 0x00000000
550 * @ctx_size: context data structure size - 64 or 32 bits.
559 #define CDNSP_CTX_TYPE_DEVICE 0x1
560 #define CDNSP_CTX_TYPE_INPUT 0x2
574 * Slot Context - This assumes the controller uses 32-byte context
575 * structures. If the controller uses 64-byte contexts, there is an additional
583 /* offset 0x10 to 0x1f reserved for controller internal use. */
594 /* Device speed - values defined by PORTSC Device Speed field - 20:23. */
597 /* Index of the last valid endpoint context in this device context - 27:31. */
600 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
601 #define SLOT_FLAG BIT(0)
606 #define DEV_PORT(p) (((p) & 0xff) << 16)
609 /* USB device address - assigned by the controller. */
610 #define DEV_ADDR_MASK GENMASK(7, 0)
615 #define SLOT_STATE_DISABLED 0
627 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
634 * Endpoint Context - This assumes the controller uses 32-byte context
635 * structures. If the controller uses 64-byte contexts, there is an additional
644 /* offset 0x14 - 0x1f reserved for controller internal use. */
650 * Endpoint State - bits 0:2:
651 * 0 - disabled
652 * 1 - running
653 * 2 - halted due to halt condition
654 * 3 - stopped
655 * 4 - TRB error
656 * 5-7 - reserved
658 #define EP_STATE_MASK GENMASK(3, 0)
659 #define EP_STATE_DISABLED 0
664 #define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
666 /* Mult - Max number of burst within an interval, in EP companion desc. */
671 /* Interval - period between requests to an endpoint - 125u increments. */
682 #define ERROR_COUNT(p) (((p) & 0x3) << 1)
683 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
693 /* bit 7 is Device Initiate Disable - for disabling stream selection. */
701 #define EP_AVG_TRB_LENGTH(p) ((p) & GENMASK(15, 0))
708 #define EP_CTX_CYCLE_MASK BIT(0)
709 #define CTX_DEQ_MASK (~0xfL)
741 * @stream_ring: 64-bit stream ring address, cycle state, and stream type.
742 * @reserved: offset 0x14 - 0x1f reserved for controller internal use.
749 /* Stream Context Types - bits 3:1 of stream ctx deq ptr. */
752 #define SCT_SEC_TR 0
761 * @num_streams: Number of streams, including stream 0.
793 * struct cdnsp_ep - extended device side representation of USB endpoint.
797 * @number: Endpoint number (1 - 15).
802 * @buffering: Number of on-chip buffers related to endpoint.
803 * @buffering_period; Number of on-chip buffers related to periodic endpoint.
832 #define EP_ENABLED BIT(0)
848 * @dev_context_ptr: Array of 64-bit DMA addresses for device contexts.
858 * @buffer: 64-bit buffer address, or immediate data.
872 /* bits 0:23 */
873 #define EVENT_TRB_LEN(p) ((p) & GENMASK(23, 0))
874 /* Completion Code - only applicable for some types of TRBs */
875 #define COMP_CODE_MASK (0xff << 24)
877 #define COMP_INVALID 0
908 #define TRB_TO_DEV_STREAM(p) ((p) & GENMASK(16, 0))
909 #define TRB_TO_HOST_STREAM(p) ((p) & GENMASK(16, 0))
910 #define STREAM_PRIME_ACK 0xFFFE
911 #define STREAM_REJECTED 0xFFFF
918 * @segment_ptr: 64-bit segment pointer.
932 * struct cdnsp_event_cmd - Command completion event TRB.
945 /* Address device - disable SetAddress. */
948 /* Configure Endpoint - Deconfigure. */
952 #define TRB_FH_TO_PACKET_TYPE(p) ((p) & GENMASK(4, 0))
953 #define TRB_FH_TR_PACKET 0x4
955 #define TRB_FH_TR_PACKET_DEV_NOT 0x6
957 #define TRB_FH_TR_PACKET_FUNCTION_WAKE 0x1
969 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB. */
970 #define TRB_TO_EP_INDEX(p) (((p) >> 16) & 0x1f)
975 #define TRB_TO_SUSPEND_PORT(p) (((p) >> 23) & 0x1)
981 #define SCT_FOR_TRB(p) (((p) << 1) & 0x7)
987 /* Port ID - bits 31:24. */
993 /* transfer_len bitmasks - bits 0:16. */
994 #define TRB_LEN(p) ((p) & GENMASK(16, 0))
1000 * is enabled (ETE).
1003 /* Interrupter Target - which MSI-X vector to target the completion event at. */
1008 * enabled (ETE).
1010 #define TRB_TBC(p) (((p) & 0x3) << 7)
1011 #define TRB_TLBPC(p) (((p) & 0xf) << 16)
1013 /* Cycle bit - indicates TRB ownership by driver or driver.*/
1014 #define TRB_CYCLE BIT(0)
1030 /* 0 - NRDY during data stage, 1 - NRDY during status stage (only control). */
1043 #define TRB_SETUP_SPEEDID_USB3 0x1
1044 #define TRB_SETUP_SPEEDID_USB2 0x0
1047 #define TRB_SETUPSTAT_ACK 0x1
1048 #define TRB_SETUPSTAT_STALL 0x0
1085 /* Transfer Ring No-op (not for the command ring). */
1109 /* Force Header Command - generate a transaction or link management packet. */
1111 /* No-op Command - not for transfer rings. */
1113 /* TRB IDs 24-31 reserved. */
1124 /* MFINDEX Wrap Event - microframe counter wrapped. */
1126 /* TRB IDs 40-47 reserved. */
1129 /* TRB IDs 49-53 reserved. */
1143 * The command ring is 64-byte aligned, so it must also be greater than 16.
1154 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
1155 ((addr) & (TRB_MAX_BUFF_SIZE - 1)))
1158 * struct cdnsp_segment - segment related data.
1171 /* Max packet sized bounce buffer for td-fragmant alignment */
1179 * struct cdnsp_td - Transfer Descriptor object.
1180 * @td_list: Used for binding TD with ep_ring->td_list.
1187 * @drbl - TD has been added to HW scheduler - only for stream capable
1202 * struct cdnsp_dequeue_state - New dequeue pointer for Transfer Ring.
1216 TYPE_CTRL = 0,
1226 * struct cdnsp_ring - information describing transfer, command or event ring.
1239 * @stream_active: Stream is active - PRIME packet has been detected.
1245 * @type: Ring type - event, transfer, or command ring.
1246 * @last_td_was_short - TD is short TD.
1272 * struct cdnsp_erst_entry - even ring segment table entry object.
1273 * @seg_addr: 64-bit event ring segment address.
1284 * struct cdnsp_erst - even ring segment table for event ring.
1296 * struct cdnsp_request - extended device side representation of usb_request
1324 * struct cdnsp_port - holds information about detected ports.
1338 #define CDNSP_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
1339 #define CDNSP_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff)
1340 #define CDNSP_EXT_PORT_OFF(x) ((x) & 0xff)
1341 #define CDNSP_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
1344 * struct cdnsp_device - represent USB device.
1358 * @hcs_params1: Cached register copies of read-only HCSPARAMS1
1359 * @hcc_params: Cached register copies of read-only HCCPARAMS1
1366 * @setup_speed - Speed detected for current SETUP packet.
1377 * @slot_id: Current Slot ID. Should be 0 or 1.
1388 * @usb2_port - Port USB 2.0.
1389 * @usb3_port - Port USB 3.0.
1390 * @active_port - Current selected Port.
1410 /* Cached register copies of read-only CDNSP data */
1469 * Registers with 64-bit address pointers should be written to with
1470 * dword accesses by writing the low dword first (ptr[0]), then the high dword
1471 * (ptr[1]) second. controller implementations that do not support 64-bit
1581 * next_request - gets the next request on the given list