Lines Matching +full:p +full:- +full:state
1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2018-2019 Cadence.
6 * Copyright (C) 2017-2018 NXP
15 #include <linux/dma-direction.h>
18 * USBSS-DEV register interface.
23 * struct cdns3_usb_regs - device controller registers.
53 * @buf_addr: Address for On-chip Buffer operations.
54 * @buf_data: Data for On-chip Buffer operations.
55 * @buf_ctrl: On-chip Buffer Access Control.
123 /* USB_CONF - bitmasks */
132 /* Little Endian access - default */
146 /* DMA clock turn-off enable. */
148 /* DMA clock turn-off disable. */
158 /* L1 LPM state entry enable (used in HS/FS mode). */
160 /* L1 LPM state entry disable (used in HS/FS mode). */
166 /* L0 LPM state entry request (used in HS/FS mode). */
173 /* U1 state entry enable (used in SS mode). */
175 /* U1 state entry disable (used in SS mode). */
177 /* U2 state entry enable (used in SS mode). */
179 /* U2 state entry disable (used in SS mode). */
181 /* U0 state entry request (used in SS mode). */
183 /* U1 state entry request (used in SS mode). */
185 /* U2 state entry request (used in SS mode). */
187 /* SS.Inactive state entry request (used in SS mode) */
190 /* USB_STS - bitmasks */
193 * 1 - device is in the configured state.
194 * 0 - device is not configured.
197 #define USB_STS_CFGSTS(p) ((p) & USB_STS_CFGSTS_MASK) argument
199 * On-chip memory overflow.
200 * 0 - On-chip memory status OK.
201 * 1 - On-chip memory overflow.
204 #define USB_STS_OV(p) ((p) & USB_STS_OV_MASK) argument
207 * 0 - USB in SuperSpeed mode disconnected.
208 * 1 - USB in SuperSpeed mode connected.
211 #define USB_STS_USB3CONS(p) ((p) & USB_STS_USB3CONS_MASK) argument
214 * 0 - single request.
215 * 1 - multiple TRB chain
219 #define USB_STS_DTRANS(p) ((p) & USB_STS_DTRANS_MASK) argument
222 * 0 - Undefined (value after reset).
223 * 1 - Low speed
224 * 2 - Full speed
225 * 3 - High speed
226 * 4 - Super speed
229 #define USB_STS_USBSPEED(p) (((p) & USB_STS_USBSPEED_MASK) >> 4) argument
234 #define DEV_UNDEFSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == (0x0 << 4)) argument
235 #define DEV_LOWSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_LS) argument
236 #define DEV_FULLSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_FS) argument
237 #define DEV_HIGHSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_HS) argument
238 #define DEV_SUPERSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_SS) argument
241 * 0 - Little Endian order (default after hardware reset).
242 * 1 - Big Endian order
245 #define USB_STS_ENDIAN(p) ((p) & USB_STS_ENDIAN_MASK) argument
247 * HS/FS clock turn-off status.
248 * 0 - hsfs clock is always on.
249 * 1 - hsfs clock turn-off in L2 (HS/FS mode) is enabled
253 #define USB_STS_CLK2OFF(p) ((p) & USB_STS_CLK2OFF_MASK) argument
255 * PCLK clock turn-off status.
256 * 0 - pclk clock is always on.
257 * 1 - pclk clock turn-off in U3 (SS mode) is enabled
261 #define USB_STS_CLK3OFF(p) ((p) & USB_STS_CLK3OFF_MASK) argument
263 * Controller in reset state.
264 * 0 - Internal reset is active.
265 * 1 - Internal reset is not active and controller is fully operational.
268 #define USB_STS_IN_RST(p) ((p) & USB_STS_IN_RST_MASK) argument
271 * 0 - disabled
272 * 1 - enabled
278 * 0 - USB device is disabled (VBUS input is disconnected from internal logic).
279 * 1 - USB device is enabled (VBUS input is connected to the internal logic).
282 #define USB_STS_DEVS(p) ((p) & USB_STS_DEVS_MASK) argument
285 * 0 - USB device is default state.
286 * 1 - USB device is at least in address state.
289 #define USB_STS_ADDRESSED(p) ((p) & USB_STS_ADDRESSED_MASK) argument
291 * L1 LPM state enable status (used in HS/FS mode).
292 * 0 - Entering to L1 LPM state disabled.
293 * 1 - Entering to L1 LPM state enabled.
296 #define USB_STS_L1ENS(p) ((p) & USB_STS_L1ENS_MASK) argument
299 * 0 - internal VBUS is not detected.
300 * 1 - internal VBUS is detected.
303 #define USB_STS_VBUSS(p) ((p) & USB_STS_VBUSS_MASK) argument
305 * HS/FS LPM state (used in FS/HS mode).
306 * 0 - L0 State
307 * 1 - L1 State
308 * 2 - L2 State
309 * 3 - L3 State
312 #define DEV_L0_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x0 << 18)) argument
313 #define DEV_L1_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x1 << 18)) argument
314 #define DEV_L2_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x2 << 18)) argument
315 #define DEV_L3_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x3 << 18)) argument
318 * 0 - the disconnect bit for HS/FS mode is set .
319 * 1 - the disconnect bit for HS/FS mode is not set.
322 #define USB_STS_USB2CONS(p) ((p) & USB_STS_USB2CONS_MASK) argument
325 * 0 - High Speed operations in USB2.0 (FS/HS) mode not disabled.
326 * 1 - High Speed operations in USB2.0 (FS/HS).
329 #define USB_STS_DISABLE_HS(p) ((p) & USB_STS_DISABLE_HS_MASK) argument
331 * U1 state enable status (used in SS mode).
332 * 0 - Entering to U1 state disabled.
333 * 1 - Entering to U1 state enabled.
336 #define USB_STS_U1ENS(p) ((p) & USB_STS_U1ENS_MASK) argument
338 * U2 state enable status (used in SS mode).
339 * 0 - Entering to U2 state disabled.
340 * 1 - Entering to U2 state enabled.
343 #define USB_STS_U2ENS(p) ((p) & USB_STS_U2ENS_MASK) argument
345 * SuperSpeed Link LTSSM state. This field reflects USBSS-DEV current
346 * SuperSpeed link state
349 #define DEV_LST_U0 (((p) & USB_STS_LST_MASK) == (0x0 << 26))
350 #define DEV_LST_U1 (((p) & USB_STS_LST_MASK) == (0x1 << 26))
351 #define DEV_LST_U2 (((p) & USB_STS_LST_MASK) == (0x2 << 26))
352 #define DEV_LST_U3 (((p) & USB_STS_LST_MASK) == (0x3 << 26))
353 #define DEV_LST_DISABLED (((p) & USB_STS_LST_MASK) == (0x4 << 26))
354 #define DEV_LST_RXDETECT (((p) & USB_STS_LST_MASK) == (0x5 << 26))
355 #define DEV_LST_INACTIVE (((p) & USB_STS_LST_MASK) == (0x6 << 26))
356 #define DEV_LST_POLLING (((p) & USB_STS_LST_MASK) == (0x7 << 26))
357 #define DEV_LST_RECOVERY (((p) & USB_STS_LST_MASK) == (0x8 << 26))
358 #define DEV_LST_HOT_RESET (((p) & USB_STS_LST_MASK) == (0x9 << 26))
359 #define DEV_LST_COMP_MODE (((p) & USB_STS_LST_MASK) == (0xa << 26))
360 #define DEV_LST_LB_STATE (((p) & USB_STS_LST_MASK) == (0xb << 26))
362 * DMA clock turn-off status.
363 * 0 - DMA clock is always on (default after hardware reset).
364 * 1 - DMA clock turn-off in U1, U2 and U3 (SS mode) is enabled.
367 #define USB_STS_DMAOFF(p) ((p) & USB_STS_DMAOFF_MASK) argument
370 * 0 - Little Endian order (default after hardware reset).
371 * 1 - Big Endian order.
374 #define USB_STS_ENDIAN2(p) ((p) & USB_STS_ENDIAN2_MASK) argument
376 /* USB_CMD - bitmasks */
387 #define USB_CMD_FADDR(p) (((p) << 1) & USB_CMD_FADDR_MASK) argument
394 #define USB_STS_TMODE_SEL(p) (((p) << 10) & USB_STS_TMODE_SEL_MASK) argument
402 /*Device Notification 'Function Wake' - Interface value (only in SS mode. */
404 #define USB_STS_DNFW_INT(p) (((p) << 16) & USB_CMD_DNFW_INT_MASK) argument
406 * Device Notification 'Latency Tolerance Message' -373 BELT value [7:0]
410 #define USB_STS_DNLTM_BELT(p) (((p) << 16) & USB_CMD_DNLTM_BELT_MASK) argument
412 /* USB_ITPN - bitmasks */
419 #define USB_ITPN(p) ((p) & USB_ITPN_MASK) argument
421 /* USB_LPM - bitmasks */
424 #define USB_LPM_HIRD(p) ((p) & USB_LPM_HIRD_MASK) argument
428 /* USB_IEN - bitmasks */
437 /* SS link U3 state enter interrupt enable (suspend).*/
439 /* SS link U3 state exit interrupt enable (wakeup). */
441 /* SS link U2 state enter interrupt enable.*/
443 /* SS link U2 state exit interrupt enable.*/
445 /* SS link U1 state enter interrupt enable.*/
447 /* SS link U1 state exit interrupt enable.*/
461 /* LPM L2 state enter interrupt enable.*/
463 /* LPM L2 state exit interrupt enable.*/
465 /* LPM L1 state enter interrupt enable.*/
467 /* LPM L1 state exit interrupt enable.*/
481 /* USB_ISTS - bitmasks */
490 /* U3 link state enter detected (suspend).*/
492 /* U3 link state exit detected (wakeup). */
494 /* U2 link state enter detected.*/
496 /* U2 link state exit detected.*/
498 /* U1 link state enter detected.*/
500 /* U1 link state exit detected.*/
514 /* LPM L2 state enter detected.*/
516 /* LPM L2 state exit detected.*/
518 /* LPM L1 state enter detected.*/
520 /* LPM L1 state exit detected.*/
529 /* USB_SEL - bitmasks */
532 #define EP_SEL_EPNO(p) ((p) & EP_SEL_EPNO_MASK) argument
533 /* Endpoint direction bit - 0 - OUT, 1 - IN. */
536 #define select_ep_in(nr) (EP_SEL_EPNO(p) | EP_SEL_DIR)
537 #define select_ep_out (EP_SEL_EPNO(p))
539 /* EP_TRADDR - bitmasks */
541 #define EP_TRADDR_TRADDR(p) ((p)) argument
543 /* EP_CFG - bitmasks */
548 * 1 - isochronous
549 * 2 - bulk
550 * 3 - interrupt
553 #define EP_CFG_EPTYPE(p) (((p) << 1) & EP_CFG_EPTYPE_MASK) argument
564 #define EP_CFG_MAXBURST(p) (((p) << 8) & EP_CFG_MAXBURST_MASK) argument
568 #define EP_CFG_MULT(p) (((p) << 14) & EP_CFG_MULT_MASK) argument
572 #define EP_CFG_MAXPKTSIZE(p) (((p) << 16) & EP_CFG_MAXPKTSIZE_MASK) argument
575 #define EP_CFG_BUFFERING(p) (((p) << 27) & EP_CFG_BUFFERING_MASK) argument
578 /* EP_CMD - bitmasks */
604 #define EP_CMD_TDL_SET(p) (((p) << 9) & EP_CMD_TDL_MASK) argument
605 #define EP_CMD_TDL_GET(p) (((p) & EP_CMD_TDL_MASK) >> 9) argument
610 #define EP_CMD_ERDY_SID(p) (((p) << 16) & EP_CMD_ERDY_SID_MASK) argument
612 /* EP_STS - bitmasks */
616 #define EP_STS_STALL(p) ((p) & BIT(1)) argument
625 /* EXIT from MOVE DATA State (used only for stream transfers in SS mode). */
634 #define EP_STS_BUFFEMPTY(p) ((p) & BIT(10)) argument
636 #define EP_STS_CCS(p) ((p) & BIT(11)) argument
646 #define EP_STS_HOSTPP(p) ((p) & BIT(16)) argument
647 /* Stream Protocol State Machine State (only for Bulk stream endpoints). */
649 #define EP_STS_SPSMST_DISABLED(p) (((p) & EP_STS_SPSMST_MASK) >> 17) argument
650 #define EP_STS_SPSMST_IDLE(p) (((p) & EP_STS_SPSMST_MASK) >> 17) argument
651 #define EP_STS_SPSMST_START_STREAM(p) (((p) & EP_STS_SPSMST_MASK) >> 17) argument
652 #define EP_STS_SPSMST_MOVE_DATA(p) (((p) & EP_STS_SPSMST_MASK) >> 17) argument
657 #define EP_STS_OUTQ_NO(p) (((p) & EP_STS_OUTQ_NO_MASK) >> 24) argument
660 #define EP_STS_OUTQ_VAL(p) ((p) & EP_STS_OUTQ_VAL_MASK) argument
664 /* EP_STS_SID - bitmasks */
667 #define EP_STS_SID(p) ((p) & EP_STS_SID_MASK) argument
669 /* EP_STS_EN - bitmasks */
695 /* DRBL- bitmasks */
700 /* EP_IEN - bitmasks */
705 /* EP_ISTS - bitmasks */
710 /* USB_PWR- bitmasks */
716 * Enables turning-off Reference Clock.
731 /* USB_CONF2- bitmasks */
745 /* USB_CAP1- bitmasks */
749 * 0x0 - OCP
750 * 0x1 - AHB,
751 * 0x2 - PLB
752 * 0x3 - AXI
753 * 0x4-0xF - reserved
756 #define DEV_SFR_TYPE_OCP(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x0) argument
757 #define DEV_SFR_TYPE_AHB(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x1) argument
758 #define DEV_SFR_TYPE_PLB(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x2) argument
759 #define DEV_SFR_TYPE_AXI(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x3) argument
763 * 0x0 - 8 bit interface,
764 * 0x1 - 16 bit interface,
765 * 0x2 - 32 bit interface
766 * 0x3 - 64 bit interface
767 * 0x4-0xF - reserved
770 #define DEV_SFR_WIDTH_8(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x0 << 4)) argument
771 #define DEV_SFR_WIDTH_16(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x1 << 4)) argument
772 #define DEV_SFR_WIDTH_32(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x2 << 4)) argument
773 #define DEV_SFR_WIDTH_64(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x3 << 4)) argument
777 * 0x0 - OCP
778 * 0x1 - AHB,
779 * 0x2 - PLB
780 * 0x3 - AXI
781 * 0x4-0xF - reserved
784 #define DEV_DMA_TYPE_OCP(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x0 << 8)) argument
785 #define DEV_DMA_TYPE_AHB(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x1 << 8)) argument
786 #define DEV_DMA_TYPE_PLB(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x2 << 8)) argument
787 #define DEV_DMA_TYPE_AXI(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x3 << 8)) argument
791 * 0x0 - reserved,
792 * 0x1 - reserved,
793 * 0x2 - 32 bit interface
794 * 0x3 - 64 bit interface
795 * 0x4-0xF - reserved
798 #define DEV_DMA_WIDTH_32(p) (((p) & USB_CAP1_DMA_WIDTH_MASK) == (0x2 << 12)) argument
799 #define DEV_DMA_WIDTH_64(p) (((p) & USB_CAP1_DMA_WIDTH_MASK) == (0x3 << 12)) argument
803 * 0x0 - USB PIPE,
804 * 0x1 - RMMI,
805 * 0x2-0xF - reserved
808 #define DEV_U3PHY_PIPE(p) (((p) & USB_CAP1_U3PHY_TYPE_MASK) == (0x0 << 16)) argument
809 #define DEV_U3PHY_RMMI(p) (((p) & USB_CAP1_U3PHY_TYPE_MASK) == (0x1 << 16)) argument
813 * 0x0 - 8 bit PIPE interface,
814 * 0x1 - 16 bit PIPE interface,
815 * 0x2 - 32 bit PIPE interface,
816 * 0x3 - 64 bit PIPE interface
817 * 0x4-0xF - reserved
822 #define DEV_U3PHY_WIDTH_8(p) \ argument
823 (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x0 << 20))
824 #define DEV_U3PHY_WIDTH_16(p) \ argument
825 (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x1 << 16))
826 #define DEV_U3PHY_WIDTH_32(p) \ argument
827 (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x2 << 20))
828 #define DEV_U3PHY_WIDTH_64(p) \ argument
829 (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x3 << 16))
834 * 0x0 - interface NOT implemented,
835 * 0x1 - interface implemented
837 #define USB_CAP1_U2PHY_EN(p) ((p) & BIT(24)) argument
841 * 0x0 - UTMI,
842 * 0x1 - ULPI
844 #define DEV_U2PHY_ULPI(p) ((p) & BIT(25)) argument
848 * 0x0 - 8 bit interface,
849 * 0x1 - 16 bit interface,
852 #define DEV_U2PHY_WIDTH_16(p) ((p) & BIT(26)) argument
855 * 0x0 - pure device mode
856 * 0x1 - some features and ports for CDNS USB OTG controller are implemented.
858 #define USB_CAP1_OTG_READY(p) ((p) & BIT(27)) argument
865 #define USB_CAP1_TDL_FROM_TRB(p) ((p) & BIT(28)) argument
867 /* USB_CAP2- bitmasks */
869 * The actual size of the connected On-chip RAM memory in kB:
870 * - 0 means 256 kB (max supported mem size)
871 * - value other than 0 reflects the mem size in kB
873 #define USB_CAP2_ACTUAL_MEM_SIZE(p) ((p) & GENMASK(7, 0)) argument
876 * These field reflects width of on-chip RAM address bus width,
878 * 0x0-0x7 - reserved,
879 * 0x8 - support for 4kB mem,
880 * 0x9 - support for 8kB mem,
881 * 0xA - support for 16kB mem,
882 * 0xB - support for 32kB mem,
883 * 0xC - support for 64kB mem,
884 * 0xD - support for 128kB mem,
885 * 0xE - support for 256kB mem,
886 * 0xF - reserved
888 #define USB_CAP2_MAX_MEM_SIZE(p) ((p) & GENMASK(11, 8)) argument
890 /* USB_CAP3- bitmasks */
893 /* USB_CAP4- bitmasks */
896 /* USB_CAP5- bitmasks */
899 /* USB_CAP6- bitmasks */
900 /* The USBSS-DEV Controller Internal build number. */
901 #define GET_DEV_BASE_VERSION(p) ((p) & GENMASK(23, 0)) argument
902 /* The USBSS-DEV Controller version number. */
903 #define GET_DEV_CUSTOM_VERSION(p) ((p) & GENMASK(31, 24)) argument
910 /* DBG_LINK1- bitmasks */
915 #define DBG_LINK1_LFPS_MIN_DET_U1_EXIT(p) ((p) & GENMASK(7, 0)) argument
921 #define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT(p) (((p) << 8) & GENMASK(15, 8)) argument
923 * RXDET_BREAK_DIS value This parameter configures terminating the Far-end
927 * 1: USBSS_DEV will not terminate Far-end receiver termination
932 #define DBG_LINK1_LFPS_GEN_PING(p) (((p) << 17) & GENMASK(21, 17)) argument
958 /* DMA_AXI_CTRL- bitmasks */
960 #define DMA_AXI_CTRL_MARPROT(p) ((p) & GENMASK(2, 0)) argument
962 #define DMA_AXI_CTRL_MAWPROT(p) (((p) & GENMASK(2, 0)) << 16) argument
969 /*-------------------------------------------------------------------------*/
971 * USBSS-DEV DMA interface.
990 *Only for ISOC endpoints - maximum number of TRBs is calculated as
991 * pow(2, bInterval-1) * number of usb requests. It is limitation made by
1001 * struct cdns3_trb - represent Transfer Descriptor block.
1022 #define TRB_TYPE(p) ((p) << 10) argument
1023 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) argument
1031 /* Cycle bit - indicates TRB ownership by driver or hw*/
1047 * - Shall be set to 0 by Software when putting TRB on the Transfer Ring
1048 * - Shall be set to 1 by Controller when Short Packet condition for this TRB
1064 #define TRB_STREAM_ID(p) ((p) << 16) argument
1065 #define TRB_FIELD_TO_STREAMID(p) (((p) & TRB_STREAM_ID_BITMASK) >> 16) argument
1068 #define TRB_TDL_HS_SIZE(p) (((p) << 16) & GENMASK(31, 16)) argument
1069 #define TRB_TDL_HS_SIZE_GET(p) (((p) & GENMASK(31, 16)) >> 16) argument
1072 #define TRB_LEN(p) ((p) & GENMASK(16, 0)) argument
1075 #define TRB_TDL_SS_SIZE(p) (((p) << 17) & GENMASK(23, 17)) argument
1076 #define TRB_TDL_SS_SIZE_GET(p) (((p) & GENMASK(23, 17)) >> 17) argument
1078 /* transfer_len bitmasks - bits 31:24 */
1079 #define TRB_BURST_LEN(p) ((unsigned int)((p) << 24) & GENMASK(31, 24)) argument
1080 #define TRB_BURST_LEN_GET(p) (((p) & GENMASK(31, 24)) >> 24) argument
1083 #define TRB_BUFFER(p) ((p) & GENMASK(31, 0)) argument
1085 /*-------------------------------------------------------------------------*/
1103 /*-------------------------------------------------------------------------*/
1109 * struct cdns3_endpoint - extended device side representation of USB endpoint.
1114 * @trb_pool: transfer ring - array of transaction buffers
1118 * @flags: specify the current state of endpoint
1119 * @descmis_req: internal transfer object used for getting data from on-chip
1123 * @num: endpoint number (1 - 15)
1129 * @pcs: producer cycle state
1130 * @ccs: consumer cycle state
1200 * struct cdns3_aligned_buf - represent aligned buffer used for DMA transfer
1218 * struct cdns3_request - extended device side representation of usb_request
1258 * struct cdns3_device - represent USB device.
1268 * @zlp_buf - zlp buffer
1277 * @u1_allowed: allow device transition to u1 state
1278 * @u2_allowed: allow device transition to u2 state
1285 * @onchip_buffers: number of available on-chip buffers.
1286 * @onchip_used_size: actual size of on-chip memory assigned to endpoints.
1301 /* generic spin-lock for drivers */