Lines Matching +full:1 +full:- +full:bit +full:- +full:only
1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2018-2019 Cadence.
6 * Copyright (C) 2017-2018 NXP
15 #include <linux/dma-direction.h>
18 * USBSS-DEV register interface.
23 * struct cdns3_usb_regs - device controller registers.
43 * @usb_cap1: Capability 1.
49 * @usb_cpkt1: Custom Packet 1.
53 * @buf_addr: Address for On-chip Buffer operations.
54 * @buf_data: Data for On-chip Buffer operations.
55 * @buf_ctrl: On-chip Buffer Access Control.
69 * @dma_axi_ctrl1: AXI Control 1.
123 /* USB_CONF - bitmasks */
125 #define USB_CONF_CFGRST BIT(0)
127 #define USB_CONF_CFGSET BIT(1)
129 #define USB_CONF_USB3DIS BIT(3)
131 #define USB_CONF_USB2DIS BIT(4)
132 /* Little Endian access - default */
133 #define USB_CONF_LENDIAN BIT(5)
136 * SFRs access always is as Little Endian so this bit
139 #define USB_CONF_BENDIAN BIT(6)
141 #define USB_CONF_SWRST BIT(7)
142 /* Singular DMA transfer mode. Only for VER < DEV_VER_V3*/
143 #define USB_CONF_DSING BIT(8)
144 /* Multiple DMA transfers mode. Only for VER < DEV_VER_V3 */
145 #define USB_CONF_DMULT BIT(9)
146 /* DMA clock turn-off enable. */
147 #define USB_CONF_DMAOFFEN BIT(10)
148 /* DMA clock turn-off disable. */
149 #define USB_CONF_DMAOFFDS BIT(11)
151 #define USB_CONF_CFORCE_FS BIT(12)
153 #define USB_CONF_SFORCE_FS BIT(13)
155 #define USB_CONF_DEVEN BIT(14)
157 #define USB_CONF_DEVDS BIT(15)
159 #define USB_CONF_L1EN BIT(16)
161 #define USB_CONF_L1DS BIT(17)
163 #define USB_CONF_CLK2OFFEN BIT(18)
165 #define USB_CONF_CLK2OFFDS BIT(19)
167 #define USB_CONF_LGO_L0 BIT(20)
169 #define USB_CONF_CLK3OFFEN BIT(21)
171 #define USB_CONF_CLK3OFFDS BIT(22)
172 /* Bit 23 is reserved*/
174 #define USB_CONF_U1EN BIT(24)
176 #define USB_CONF_U1DS BIT(25)
178 #define USB_CONF_U2EN BIT(26)
180 #define USB_CONF_U2DS BIT(27)
182 #define USB_CONF_LGO_U0 BIT(28)
184 #define USB_CONF_LGO_U1 BIT(29)
186 #define USB_CONF_LGO_U2 BIT(30)
188 #define USB_CONF_LGO_SSINACT BIT(31)
190 /* USB_STS - bitmasks */
193 * 1 - device is in the configured state.
194 * 0 - device is not configured.
196 #define USB_STS_CFGSTS_MASK BIT(0)
199 * On-chip memory overflow.
200 * 0 - On-chip memory status OK.
201 * 1 - On-chip memory overflow.
203 #define USB_STS_OV_MASK BIT(1)
207 * 0 - USB in SuperSpeed mode disconnected.
208 * 1 - USB in SuperSpeed mode connected.
210 #define USB_STS_USB3CONS_MASK BIT(2)
214 * 0 - single request.
215 * 1 - multiple TRB chain
216 * Supported only for controller version < DEV_VER_V3
218 #define USB_STS_DTRANS_MASK BIT(3)
222 * 0 - Undefined (value after reset).
223 * 1 - Low speed
224 * 2 - Full speed
225 * 3 - High speed
226 * 4 - Super speed
241 * 0 - Little Endian order (default after hardware reset).
242 * 1 - Big Endian order
244 #define USB_STS_ENDIAN_MASK BIT(7)
247 * HS/FS clock turn-off status.
248 * 0 - hsfs clock is always on.
249 * 1 - hsfs clock turn-off in L2 (HS/FS mode) is enabled
252 #define USB_STS_CLK2OFF_MASK BIT(8)
255 * PCLK clock turn-off status.
256 * 0 - pclk clock is always on.
257 * 1 - pclk clock turn-off in U3 (SS mode) is enabled
260 #define USB_STS_CLK3OFF_MASK BIT(9)
264 * 0 - Internal reset is active.
265 * 1 - Internal reset is not active and controller is fully operational.
267 #define USB_STS_IN_RST_MASK BIT(10)
271 * 0 - disabled
272 * 1 - enabled
273 * Supported only for DEV_VER_V2 controller version.
275 #define USB_STS_TDL_TRB_ENABLED BIT(11)
278 * 0 - USB device is disabled (VBUS input is disconnected from internal logic).
279 * 1 - USB device is enabled (VBUS input is connected to the internal logic).
281 #define USB_STS_DEVS_MASK BIT(14)
285 * 0 - USB device is default state.
286 * 1 - USB device is at least in address state.
288 #define USB_STS_ADDRESSED_MASK BIT(15)
292 * 0 - Entering to L1 LPM state disabled.
293 * 1 - Entering to L1 LPM state enabled.
295 #define USB_STS_L1ENS_MASK BIT(16)
299 * 0 - internal VBUS is not detected.
300 * 1 - internal VBUS is detected.
302 #define USB_STS_VBUSS_MASK BIT(17)
306 * 0 - L0 State
307 * 1 - L1 State
308 * 2 - L2 State
309 * 3 - L3 State
318 * 0 - the disconnect bit for HS/FS mode is set .
319 * 1 - the disconnect bit for HS/FS mode is not set.
321 #define USB_STS_USB2CONS_MASK BIT(20)
325 * 0 - High Speed operations in USB2.0 (FS/HS) mode not disabled.
326 * 1 - High Speed operations in USB2.0 (FS/HS).
328 #define USB_STS_DISABLE_HS_MASK BIT(21)
332 * 0 - Entering to U1 state disabled.
333 * 1 - Entering to U1 state enabled.
335 #define USB_STS_U1ENS_MASK BIT(24)
339 * 0 - Entering to U2 state disabled.
340 * 1 - Entering to U2 state enabled.
342 #define USB_STS_U2ENS_MASK BIT(25)
345 * SuperSpeed Link LTSSM state. This field reflects USBSS-DEV current
362 * DMA clock turn-off status.
363 * 0 - DMA clock is always on (default after hardware reset).
364 * 1 - DMA clock turn-off in U1, U2 and U3 (SS mode) is enabled.
366 #define USB_STS_DMAOFF_MASK BIT(30)
370 * 0 - Little Endian order (default after hardware reset).
371 * 1 - Big Endian order.
373 #define USB_STS_ENDIAN2_MASK BIT(31)
376 /* USB_CMD - bitmasks */
378 #define USB_CMD_SET_ADDR BIT(0)
380 * Function Address This field is saved to the device only when the field
381 * SET_ADDR is set '1 ' during write to USB_CMD register.
386 #define USB_CMD_FADDR_MASK GENMASK(7, 1)
387 #define USB_CMD_FADDR(p) (((p) << 1) & USB_CMD_FADDR_MASK)
388 /* Send Function Wake Device Notification TP (used only in SS mode). */
389 #define USB_CMD_SDNFW BIT(8)
390 /* Set Test Mode (used only in HS/FS mode). */
391 #define USB_CMD_STMODE BIT(9)
392 /* Test mode selector (used only in HS/FS mode) */
396 * Send Latency Tolerance Message Device Notification TP (used only
399 #define USB_CMD_SDNLTM BIT(12)
400 /* Send Custom Transaction Packet (used only in SS mode) */
401 #define USB_CMD_SPKT BIT(13)
402 /*Device Notification 'Function Wake' - Interface value (only in SS mode. */
406 * Device Notification 'Latency Tolerance Message' -373 BELT value [7:0]
407 * (used only in SS mode).
412 /* USB_ITPN - bitmasks */
421 /* USB_LPM - bitmasks */
426 #define USB_LPM_BRW BIT(4)
428 /* USB_IEN - bitmasks */
430 #define USB_IEN_CONIEN BIT(0)
432 #define USB_IEN_DISIEN BIT(1)
434 #define USB_IEN_UWRESIEN BIT(2)
436 #define USB_IEN_UHRESIEN BIT(3)
438 #define USB_IEN_U3ENTIEN BIT(4)
440 #define USB_IEN_U3EXTIEN BIT(5)
442 #define USB_IEN_U2ENTIEN BIT(6)
444 #define USB_IEN_U2EXTIEN BIT(7)
446 #define USB_IEN_U1ENTIEN BIT(8)
448 #define USB_IEN_U1EXTIEN BIT(9)
450 #define USB_IEN_ITPIEN BIT(10)
452 #define USB_IEN_WAKEIEN BIT(11)
454 #define USB_IEN_SPKTIEN BIT(12)
456 #define USB_IEN_CON2IEN BIT(16)
458 #define USB_IEN_DIS2IEN BIT(17)
460 #define USB_IEN_U2RESIEN BIT(18)
462 #define USB_IEN_L2ENTIEN BIT(20)
464 #define USB_IEN_L2EXTIEN BIT(21)
466 #define USB_IEN_L1ENTIEN BIT(24)
468 #define USB_IEN_L1EXTIEN BIT(25)
470 #define USB_IEN_CFGRESIEN BIT(26)
472 #define USB_IEN_UWRESSIEN BIT(28)
474 #define USB_IEN_UWRESEIEN BIT(29)
481 /* USB_ISTS - bitmasks */
483 #define USB_ISTS_CONI BIT(0)
485 #define USB_ISTS_DISI BIT(1)
487 #define USB_ISTS_UWRESI BIT(2)
489 #define USB_ISTS_UHRESI BIT(3)
491 #define USB_ISTS_U3ENTI BIT(4)
493 #define USB_ISTS_U3EXTI BIT(5)
495 #define USB_ISTS_U2ENTI BIT(6)
497 #define USB_ISTS_U2EXTI BIT(7)
499 #define USB_ISTS_U1ENTI BIT(8)
501 #define USB_ISTS_U1EXTI BIT(9)
503 #define USB_ISTS_ITPI BIT(10)
505 #define USB_ISTS_WAKEI BIT(11)
507 #define USB_ISTS_SPKTI BIT(12)
509 #define USB_ISTS_CON2I BIT(16)
511 #define USB_ISTS_DIS2I BIT(17)
513 #define USB_ISTS_U2RESI BIT(18)
515 #define USB_ISTS_L2ENTI BIT(20)
517 #define USB_ISTS_L2EXTI BIT(21)
519 #define USB_ISTS_L1ENTI BIT(24)
521 #define USB_ISTS_L1EXTI BIT(25)
523 #define USB_ISTS_CFGRESI BIT(26)
525 #define USB_ISTS_UWRESSI BIT(28)
527 #define USB_ISTS_UWRESEI BIT(29)
529 /* USB_SEL - bitmasks */
533 /* Endpoint direction bit - 0 - OUT, 1 - IN. */
534 #define EP_SEL_DIR BIT(7)
539 /* EP_TRADDR - bitmasks */
543 /* EP_CFG - bitmasks */
545 #define EP_CFG_ENABLE BIT(0)
548 * 1 - isochronous
549 * 2 - bulk
550 * 3 - interrupt
552 #define EP_CFG_EPTYPE_MASK GENMASK(2, 1)
553 #define EP_CFG_EPTYPE(p) (((p) << 1) & EP_CFG_EPTYPE_MASK)
554 /* Stream support enable (only in SS mode). */
555 #define EP_CFG_STREAM_EN BIT(3)
556 /* TDL check (only in SS mode for BULK EP). */
557 #define EP_CFG_TDL_CHK BIT(4)
558 /* SID check (only in SS mode for BULK OUT EP). */
559 #define EP_CFG_SID_CHK BIT(5)
561 #define EP_CFG_EPENDIAN BIT(7)
562 /* Max burst size (used only in SS mode). */
578 /* EP_CMD - bitmasks */
580 #define EP_CMD_EPRST BIT(0)
582 #define EP_CMD_SSTALL BIT(1)
584 #define EP_CMD_CSTALL BIT(2)
586 #define EP_CMD_ERDY BIT(3)
588 #define EP_CMD_REQ_CMPL BIT(5)
590 #define EP_CMD_DRDY BIT(6)
592 #define EP_CMD_DFLUSH BIT(7)
594 * Transfer Descriptor Length write (used only for Bulk Stream capable
596 * Bit Removed from DEV_VER_V3 controller version.
598 #define EP_CMD_STDL BIT(8)
600 * Transfer Descriptor Length (used only in SS mode for bulk endpoints).
612 /* EP_STS - bitmasks */
614 #define EP_STS_SETUP BIT(0)
616 #define EP_STS_STALL(p) ((p) & BIT(1))
618 #define EP_STS_IOC BIT(2)
620 #define EP_STS_ISP BIT(3)
622 #define EP_STS_DESCMIS BIT(4)
623 /* Stream Rejected (used only in SS mode) */
624 #define EP_STS_STREAMR BIT(5)
625 /* EXIT from MOVE DATA State (used only for stream transfers in SS mode). */
626 #define EP_STS_MD_EXIT BIT(6)
628 #define EP_STS_TRBERR BIT(7)
629 /* Not ready (used only in SS mode). */
630 #define EP_STS_NRDY BIT(8)
631 /* DMA busy bit. */
632 #define EP_STS_DBUSY BIT(9)
634 #define EP_STS_BUFFEMPTY(p) ((p) & BIT(10))
636 #define EP_STS_CCS(p) ((p) & BIT(11))
637 /* Prime (used only in SS mode. */
638 #define EP_STS_PRIME BIT(12)
639 /* Stream error (used only in SS mode). */
640 #define EP_STS_SIDERR BIT(13)
642 #define EP_STS_OUTSMM BIT(14)
644 #define EP_STS_ISOERR BIT(15)
645 /* Host Packet Pending (only for SS mode). */
646 #define EP_STS_HOSTPP(p) ((p) & BIT(16))
647 /* Stream Protocol State Machine State (only for Bulk stream endpoints). */
654 #define EP_STS_IOT BIT(19)
659 #define EP_STS_OUTQ_VAL_MASK BIT(28)
662 #define EP_STS_STPWAIT BIT(31)
664 /* EP_STS_SID - bitmasks */
665 /* Stream ID (used only in SS mode). */
669 /* EP_STS_EN - bitmasks */
671 #define EP_STS_EN_SETUPEN BIT(0)
673 #define EP_STS_EN_DESCMISEN BIT(4)
675 #define EP_STS_EN_STREAMREN BIT(5)
677 #define EP_STS_EN_MD_EXITEN BIT(6)
679 #define EP_STS_EN_TRBERREN BIT(7)
681 #define EP_STS_EN_NRDYEN BIT(8)
683 #define EP_STS_EN_PRIMEEEN BIT(12)
685 #define EP_STS_EN_SIDERREN BIT(13)
687 #define EP_STS_EN_OUTSMMEN BIT(14)
689 #define EP_STS_EN_ISOERREN BIT(15)
691 #define EP_STS_EN_IOTEN BIT(19)
693 #define EP_STS_EN_STPWAITEN BIT(31)
695 /* DRBL- bitmasks */
696 #define DB_VALUE_BY_INDEX(index) (1 << (index))
697 #define DB_VALUE_EP0_OUT BIT(0)
698 #define DB_VALUE_EP0_IN BIT(16)
700 /* EP_IEN - bitmasks */
701 #define EP_IEN(index) (1 << (index))
702 #define EP_IEN_EP_OUT0 BIT(0)
703 #define EP_IEN_EP_IN0 BIT(16)
705 /* EP_ISTS - bitmasks */
706 #define EP_ISTS(index) (1 << (index))
707 #define EP_ISTS_EP_OUT0 BIT(0)
708 #define EP_ISTS_EP_IN0 BIT(16)
710 /* USB_PWR- bitmasks */
712 #define PUSB_PWR_PSO_EN BIT(0)
714 #define PUSB_PWR_PSO_DS BIT(1)
716 * Enables turning-off Reference Clock.
717 * This bit is optional and implemented only when support for OTG is
718 * implemented (indicated by OTG_READY bit set to '1').
720 #define PUSB_PWR_STB_CLK_SWITCH_EN BIT(8)
722 * Status bit indicating that operation required by STB_CLK_SWITCH_EN write
725 #define PUSB_PWR_STB_CLK_SWITCH_DONE BIT(9)
726 /* This bit informs if Fast Registers Access is enabled. */
727 #define PUSB_PWR_FST_REG_ACCESS_STAT BIT(30)
729 #define PUSB_PWR_FST_REG_ACCESS BIT(31)
731 /* USB_CONF2- bitmasks */
733 * Writing 1 disables TDL calculation basing on TRB feature in controller
735 * Bit supported only for DEV_VER_V2 version.
737 #define USB_CONF2_DIS_TDL_TRB BIT(1)
739 * Writing 1 enables TDL calculation basing on TRB feature in controller
741 * Bit supported only for DEV_VER_V2 version.
743 #define USB_CONF2_EN_TDL_TRB BIT(2)
745 /* USB_CAP1- bitmasks */
749 * 0x0 - OCP
750 * 0x1 - AHB,
751 * 0x2 - PLB
752 * 0x3 - AXI
753 * 0x4-0xF - reserved
763 * 0x0 - 8 bit interface,
764 * 0x1 - 16 bit interface,
765 * 0x2 - 32 bit interface
766 * 0x3 - 64 bit interface
767 * 0x4-0xF - reserved
777 * 0x0 - OCP
778 * 0x1 - AHB,
779 * 0x2 - PLB
780 * 0x3 - AXI
781 * 0x4-0xF - reserved
791 * 0x0 - reserved,
792 * 0x1 - reserved,
793 * 0x2 - 32 bit interface
794 * 0x3 - 64 bit interface
795 * 0x4-0xF - reserved
803 * 0x0 - USB PIPE,
804 * 0x1 - RMMI,
805 * 0x2-0xF - reserved
813 * 0x0 - 8 bit PIPE interface,
814 * 0x1 - 16 bit PIPE interface,
815 * 0x2 - 32 bit PIPE interface,
816 * 0x3 - 64 bit PIPE interface
817 * 0x4-0xF - reserved
819 * internal PIPE interface. The RMMI interface is always 20bit wide.
834 * 0x0 - interface NOT implemented,
835 * 0x1 - interface implemented
837 #define USB_CAP1_U2PHY_EN(p) ((p) & BIT(24))
841 * 0x0 - UTMI,
842 * 0x1 - ULPI
844 #define DEV_U2PHY_ULPI(p) ((p) & BIT(25))
848 * 0x0 - 8 bit interface,
849 * 0x1 - 16 bit interface,
850 * Note: The ULPI interface is always 8bit wide.
852 #define DEV_U2PHY_WIDTH_16(p) ((p) & BIT(26))
855 * 0x0 - pure device mode
856 * 0x1 - some features and ports for CDNS USB OTG controller are implemented.
858 #define USB_CAP1_OTG_READY(p) ((p) & BIT(27))
863 * Supported only for DEV_VER_V2 controller version.
865 #define USB_CAP1_TDL_FROM_TRB(p) ((p) & BIT(28))
867 /* USB_CAP2- bitmasks */
869 * The actual size of the connected On-chip RAM memory in kB:
870 * - 0 means 256 kB (max supported mem size)
871 * - value other than 0 reflects the mem size in kB
876 * These field reflects width of on-chip RAM address bus width,
878 * 0x0-0x7 - reserved,
879 * 0x8 - support for 4kB mem,
880 * 0x9 - support for 8kB mem,
881 * 0xA - support for 16kB mem,
882 * 0xB - support for 32kB mem,
883 * 0xC - support for 64kB mem,
884 * 0xD - support for 128kB mem,
885 * 0xE - support for 256kB mem,
886 * 0xF - reserved
890 /* USB_CAP3- bitmasks */
891 #define EP_IS_IMPLEMENTED(reg, index) ((reg) & (1 << (index)))
893 /* USB_CAP4- bitmasks */
894 #define EP_SUPPORT_ISO(reg, index) ((reg) & (1 << (index)))
896 /* USB_CAP5- bitmasks */
897 #define EP_SUPPORT_STREAM(reg, index) ((reg) & (1 << (index)))
899 /* USB_CAP6- bitmasks */
900 /* The USBSS-DEV Controller Internal build number. */
902 /* The USBSS-DEV Controller version number. */
910 /* DBG_LINK1- bitmasks */
923 * RXDET_BREAK_DIS value This parameter configures terminating the Far-end
927 * 1: USBSS_DEV will not terminate Far-end receiver termination
930 #define DBG_LINK1_RXDET_BREAK_DIS BIT(16)
934 * Set the LFPS_MIN_DET_U1_EXIT value Writing '1' to this bit writes the
935 * LFPS_MIN_DET_U1_EXIT field value to the device. This bit is automatically
938 #define DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SET BIT(24)
940 * Set the LFPS_MIN_GEN_U1_EXIT value. Writing '1' to this bit writes the
941 * LFPS_MIN_GEN_U1_EXIT field value to the device. This bit is automatically
944 #define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET BIT(25)
946 * Set the RXDET_BREAK_DIS value Writing '1' to this bit writes
947 * the RXDET_BREAK_DIS field value to the device. This bit is automatically
950 #define DBG_LINK1_RXDET_BREAK_DIS_SET BIT(26)
952 * Set the LFPS_GEN_PING_SET value Writing '1' to this bit writes
953 * the LFPS_GEN_PING field value to the device. This bit is automatically
956 #define DBG_LINK1_LFPS_GEN_PING_SET BIT(27)
958 /* DMA_AXI_CTRL- bitmasks */
969 /*-------------------------------------------------------------------------*/
971 * USBSS-DEV DMA interface.
977 #define MAX_TRB_LENGTH BIT(16)
990 *Only for ISOC endpoints - maximum number of TRBs is calculated as
991 * pow(2, bInterval-1) * number of usb requests. It is limitation made by
993 * if bInterval > 1. It's the reason why driver needs so many TRBs for
1001 * struct cdns3_trb - represent Transfer Descriptor block.
1020 /* TRB bit mask */
1027 #define TRB_NORMAL 1
1031 /* Cycle bit - indicates TRB ownership by driver or hw*/
1032 #define TRB_CYCLE BIT(0)
1034 * When set to '1', the device will toggle its interpretation of the Cycle bit
1036 #define TRB_TOGGLE BIT(1)
1039 * this bit is for normal TRB
1041 #define TRB_SMM BIT(1)
1044 * Short Packet (SP). OUT EPs at DMULT=1 only. Indicates if the TRB was
1047 * - Shall be set to 0 by Software when putting TRB on the Transfer Ring
1048 * - Shall be set to 1 by Controller when Short Packet condition for this TRB
1051 #define TRB_SP BIT(1)
1054 #define TRB_ISP BIT(2)
1055 /*Setting this bit enables FIFO DMA operation mode*/
1056 #define TRB_FIFO_MODE BIT(3)
1058 #define TRB_CHAIN BIT(4)
1060 #define TRB_IOC BIT(5)
1078 /* transfer_len bitmasks - bits 31:24 */
1085 /*-------------------------------------------------------------------------*/
1103 /*-------------------------------------------------------------------------*/
1109 * struct cdns3_endpoint - extended device side representation of USB endpoint.
1114 * @trb_pool: transfer ring - array of transaction buffers
1119 * @descmis_req: internal transfer object used for getting data from on-chip
1120 * buffer. It can happen only if function driver doesn't send usb_request
1123 * @num: endpoint number (1 - 15)
1148 #define EP_ENABLED BIT(0)
1149 #define EP_STALLED BIT(1)
1150 #define EP_STALL_PENDING BIT(2)
1151 #define EP_WEDGE BIT(3)
1152 #define EP_TRANSFER_STARTED BIT(4)
1153 #define EP_UPDATE_EP_TRBADDR BIT(5)
1154 #define EP_PENDING_REQUEST BIT(6)
1155 #define EP_RING_FULL BIT(7)
1156 #define EP_CLAIMED BIT(8)
1157 #define EP_DEFERRED_DRDY BIT(9)
1158 #define EP_QUIRK_ISO_OUT_EN BIT(10)
1159 #define EP_QUIRK_END_TRANSFER BIT(11)
1160 #define EP_QUIRK_EXTRA_BUF_DET BIT(12)
1161 #define EP_QUIRK_EXTRA_BUF_EN BIT(13)
1162 #define EP_TDLCHK_EN BIT(15)
1163 #define EP_CONFIGURED BIT(16)
1185 unsigned int wa1_set:1;
1188 unsigned int wa1_cycle_bit:1;
1191 unsigned int use_streams:1;
1192 unsigned int prime_flag:1;
1200 * struct cdns3_aligned_buf - represent aligned buffer used for DMA transfer
1213 unsigned in_use:1;
1218 * struct cdns3_request - extended device side representation of usb_request
1239 #define REQUEST_PENDING BIT(0)
1240 #define REQUEST_INTERNAL BIT(1)
1241 #define REQUEST_INTERNAL_CH BIT(2)
1242 #define REQUEST_ZLP BIT(3)
1243 #define REQUEST_UNALIGNED BIT(4)
1258 * struct cdns3_device - represent USB device.
1268 * @zlp_buf - zlp buffer
1274 * @selected_ep: actually selected endpoint. It's used only to improve
1276 * @isoch_delay: value from Set Isoch Delay request. Only valid on SS/SSP.
1285 * @onchip_buffers: number of available on-chip buffers.
1286 * @onchip_used_size: actual size of on-chip memory assigned to endpoints.
1301 /* generic spin-lock for drivers */
1322 unsigned wait_for_setup:1;
1323 unsigned u1_allowed:1;
1324 unsigned u2_allowed:1;
1325 unsigned is_selfpowered:1;
1326 unsigned setup_pending:1;
1327 unsigned hw_configured_flag:1;
1328 unsigned wake_up_flag:1;
1329 unsigned status_completion_no_call:1;
1330 unsigned using_streams:1;