Lines Matching +full:0 +full:x1900
13 #define MPHY_TX_FSM_STATE 0x41
14 #define TX_FSM_HIBERN8 0x1
22 #define UFS_HW_VER_STEP_MASK GENMASK(15, 0)
29 REG_UFS_SYS1CLK_1US = 0xC0,
30 REG_UFS_TX_SYMBOL_CLK_NS_US = 0xC4,
31 REG_UFS_LOCAL_PORT_ID_REG = 0xC8,
32 REG_UFS_PA_ERR_CODE = 0xCC,
34 REG_UFS_PARAM0 = 0xD0,
36 REG_UFS_CFG0 = 0xD8,
37 REG_UFS_CFG1 = 0xDC,
38 REG_UFS_CFG2 = 0xE0,
39 REG_UFS_HW_VERSION = 0xE4,
41 UFS_TEST_BUS = 0xE8,
42 UFS_TEST_BUS_CTRL_0 = 0xEC,
43 UFS_TEST_BUS_CTRL_1 = 0xF0,
44 UFS_TEST_BUS_CTRL_2 = 0xF4,
45 UFS_UNIPRO_CFG = 0xF8,
49 * added in HW Version 3.0.0
51 UFS_AH8_CFG = 0xFC,
53 REG_UFS_CFG3 = 0x271C,
55 REG_UFS_DEBUG_SPARE_CFG = 0x284C,
60 UFS_DBG_RD_REG_UAWM = 0x100,
61 UFS_DBG_RD_REG_UARM = 0x200,
62 UFS_DBG_RD_REG_TXUC = 0x300,
63 UFS_DBG_RD_REG_RXUC = 0x400,
64 UFS_DBG_RD_REG_DFC = 0x500,
65 UFS_DBG_RD_REG_TRLUT = 0x600,
66 UFS_DBG_RD_REG_TMRLUT = 0x700,
67 UFS_UFS_DBG_RD_REG_OCSC = 0x800,
69 UFS_UFS_DBG_RD_DESC_RAM = 0x1500,
70 UFS_UFS_DBG_RD_PRDT_RAM = 0x1700,
71 UFS_UFS_DBG_RD_RESP_RAM = 0x1800,
72 UFS_UFS_DBG_RD_EDTL_RAM = 0x1900,
76 UFS_MEM_CQIS_VS = 0x8,
79 #define UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(x) (0x000 + x)
80 #define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x) (0x400 + x)
86 #define QUNIPRO_SEL BIT(0)
94 #define UAWM_HW_CGC_EN BIT(0)
111 #define TEST_BUS_SUB_SEL_MASK GENMASK(4, 0) /* All XXX_SEL fields are 5 bits wide */
119 #define PA_VS_CONFIG_REG1 0x9000
120 #define DME_VS_CORE_CLK_CTRL 0xD002
123 #define CLK_1US_CYCLES_MASK GENMASK(7, 0)
125 #define PA_VS_CORE_CLK_40NS_CYCLES 0x9007
126 #define PA_VS_CORE_CLK_40NS_CYCLES_MASK GENMASK(6, 0)
162 ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, 0, REG_UFS_CFG1); in ufs_qcom_deassert_reset()
228 if (host->hw_ver.major <= 0x02) in ufs_qcom_get_debug_reg_offset()
237 #define ceil(freq, div) ((freq) % (div) == 0 ? ((freq)/(div)) : ((freq)/(div) + 1))