Lines Matching +full:cpu +full:- +full:ufs
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
16 #include <linux/reset-controller.h>
21 #include <ufs/ufshcd.h>
22 #include <ufs/ufshci.h>
23 #include <ufs/ufs_quirks.h>
24 #include <ufs/unipro.h>
25 #include "ufshcd-pltfrm.h"
26 #include "ufs-qcom.h"
111 if (host->hba->caps & UFSHCD_CAP_CRYPTO) in ufs_qcom_ice_enable()
112 qcom_ice_enable(host->ice); in ufs_qcom_ice_enable()
119 struct ufs_hba *hba = host->hba; in ufs_qcom_ice_init()
120 struct blk_crypto_profile *profile = &hba->crypto_profile; in ufs_qcom_ice_init()
121 struct device *dev = hba->dev; in ufs_qcom_ice_init()
129 if (ice == ERR_PTR(-EOPNOTSUPP)) { in ufs_qcom_ice_init()
137 host->ice = ice; in ufs_qcom_ice_init()
148 profile->ll_ops = ufs_qcom_crypto_ops; in ufs_qcom_ice_init()
149 profile->max_dun_bytes_supported = 8; in ufs_qcom_ice_init()
150 profile->dev = dev; in ufs_qcom_ice_init()
153 * Currently this driver only supports AES-256-XTS. All known versions in ufs_qcom_ice_init()
164 profile->modes_supported[BLK_ENCRYPTION_MODE_AES_256_XTS] |= in ufs_qcom_ice_init()
168 hba->caps |= UFSHCD_CAP_CRYPTO; in ufs_qcom_ice_init()
169 hba->quirks |= UFSHCD_QUIRK_CUSTOM_CRYPTO_PROFILE; in ufs_qcom_ice_init()
175 if (host->hba->caps & UFSHCD_CAP_CRYPTO) in ufs_qcom_ice_resume()
176 return qcom_ice_resume(host->ice); in ufs_qcom_ice_resume()
183 if (host->hba->caps & UFSHCD_CAP_CRYPTO) in ufs_qcom_ice_suspend()
184 return qcom_ice_suspend(host->ice); in ufs_qcom_ice_suspend()
197 /* Only AES-256-XTS has been tested so far. */ in ufs_qcom_ice_keyslot_program()
198 if (key->crypto_cfg.crypto_mode != BLK_ENCRYPTION_MODE_AES_256_XTS) in ufs_qcom_ice_keyslot_program()
199 return -EOPNOTSUPP; in ufs_qcom_ice_keyslot_program()
202 err = qcom_ice_program_key(host->ice, in ufs_qcom_ice_keyslot_program()
205 key->raw, in ufs_qcom_ice_keyslot_program()
206 key->crypto_cfg.data_unit_size / 512, in ufs_qcom_ice_keyslot_program()
221 err = qcom_ice_evict_key(host->ice, slot); in ufs_qcom_ice_keyslot_evict()
255 if (!host->is_lane_clks_enabled) in ufs_qcom_disable_lane_clks()
258 clk_bulk_disable_unprepare(host->num_clks, host->clks); in ufs_qcom_disable_lane_clks()
260 host->is_lane_clks_enabled = false; in ufs_qcom_disable_lane_clks()
267 err = clk_bulk_prepare_enable(host->num_clks, host->clks); in ufs_qcom_enable_lane_clks()
271 host->is_lane_clks_enabled = true; in ufs_qcom_enable_lane_clks()
279 struct device *dev = host->hba->dev; in ufs_qcom_init_lane_clks()
284 err = devm_clk_bulk_get_all(dev, &host->clks); in ufs_qcom_init_lane_clks()
288 host->num_clks = err; in ufs_qcom_init_lane_clks()
322 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n", in ufs_qcom_check_hibern8()
326 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n", in ufs_qcom_check_hibern8()
335 ufshcd_rmwl(host->hba, QUNIPRO_SEL, QUNIPRO_SEL, REG_UFS_CFG1); in ufs_qcom_select_unipro_mode()
337 if (host->hw_ver.major >= 0x05) in ufs_qcom_select_unipro_mode()
338 ufshcd_rmwl(host->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0); in ufs_qcom_select_unipro_mode()
342 * ufs_qcom_host_reset - reset host controller and PHY
350 if (!host->core_reset) in ufs_qcom_host_reset()
353 reenable_intr = hba->is_irq_enabled; in ufs_qcom_host_reset()
356 ret = reset_control_assert(host->core_reset); in ufs_qcom_host_reset()
358 dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n", in ufs_qcom_host_reset()
365 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to in ufs_qcom_host_reset()
370 ret = reset_control_deassert(host->core_reset); in ufs_qcom_host_reset()
372 dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n", in ufs_qcom_host_reset()
389 if (host->hw_ver.major >= 0x4) in ufs_qcom_get_hs_gear()
392 /* Default is HS-G3 */ in ufs_qcom_get_hs_gear()
399 struct ufs_host_params *host_params = &host->host_params; in ufs_qcom_power_up_sequence()
400 struct phy *phy = host->generic_phy; in ufs_qcom_power_up_sequence()
405 * HW ver 5 can only support up to HS-G5 Rate-A due to HW limitations. in ufs_qcom_power_up_sequence()
406 * If the HS-G5 PHY gear is used, update host_params->hs_rate to Rate-A, in ufs_qcom_power_up_sequence()
407 * so that the subsequent power mode change shall stick to Rate-A. in ufs_qcom_power_up_sequence()
409 if (host->hw_ver.major == 0x5) { in ufs_qcom_power_up_sequence()
410 if (host->phy_gear == UFS_HS_G5) in ufs_qcom_power_up_sequence()
411 host_params->hs_rate = PA_HS_MODE_A; in ufs_qcom_power_up_sequence()
413 host_params->hs_rate = PA_HS_MODE_B; in ufs_qcom_power_up_sequence()
416 mode = host_params->hs_rate == PA_HS_MODE_B ? PHY_MODE_UFS_HS_B : PHY_MODE_UFS_HS_A; in ufs_qcom_power_up_sequence()
418 /* Reset UFS Host Controller and PHY */ in ufs_qcom_power_up_sequence()
423 if (phy->power_count) { in ufs_qcom_power_up_sequence()
428 /* phy initialization - calibrate the phy */ in ufs_qcom_power_up_sequence()
431 dev_err(hba->dev, "%s: phy init failed, ret = %d\n", in ufs_qcom_power_up_sequence()
436 ret = phy_set_mode_ext(phy, mode, host->phy_gear); in ufs_qcom_power_up_sequence()
440 /* power on phy - start serdes and phy's power and clocks */ in ufs_qcom_power_up_sequence()
443 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n", in ufs_qcom_power_up_sequence()
460 * Internal hardware sub-modules within the UTP controller control the CGCs.
461 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
463 * this function enables them (after every UFS link startup) to save some power
495 /* check if UFS PHY moved from DISABLED to HIBERN8 */ in ufs_qcom_hce_enable_notify()
501 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status); in ufs_qcom_hce_enable_notify()
502 err = -EINVAL; in ufs_qcom_hce_enable_notify()
509 * ufs_qcom_cfg_timers - Configure ufs qcom cfg timers
517 * Return: zero for success and non-zero in case of a failure.
531 * It is mandatory to write SYS1CLK_1US_REG register on UFS host in ufs_qcom_cfg_timers()
534 if (host->hw_ver.major < 4 && !ufshcd_is_intr_aggr_allowed(hba)) in ufs_qcom_cfg_timers()
538 dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear); in ufs_qcom_cfg_timers()
539 return -EINVAL; in ufs_qcom_cfg_timers()
542 list_for_each_entry(clki, &hba->clk_list_head, list) { in ufs_qcom_cfg_timers()
543 if (!strcmp(clki->name, "core_clk")) { in ufs_qcom_cfg_timers()
545 core_clk_rate = clki->max_freq; in ufs_qcom_cfg_timers()
547 core_clk_rate = clk_get_rate(clki->clk); in ufs_qcom_cfg_timers()
579 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", in ufs_qcom_link_startup_notify()
581 return -EINVAL; in ufs_qcom_link_startup_notify()
586 dev_err(hba->dev, "cfg core clk ctrl failed\n"); in ufs_qcom_link_startup_notify()
588 * Some UFS devices (and may be host) have issues if LCC is in ufs_qcom_link_startup_notify()
609 if (!host->device_reset) in ufs_qcom_device_reset_ctrl()
612 gpiod_set_value_cansleep(host->device_reset, asserted); in ufs_qcom_device_reset_ctrl()
619 struct phy *phy = host->generic_phy; in ufs_qcom_suspend()
633 /* reset the connected UFS device during power down */ in ufs_qcom_suspend()
646 struct phy *phy = host->generic_phy; in ufs_qcom_resume()
652 dev_err(hba->dev, "%s: failed PHY power on: %d\n", in ufs_qcom_resume()
672 if (host->dev_ref_clk_ctrl_mmio && in ufs_qcom_dev_ref_clk_ctrl()
673 (enable ^ host->is_dev_ref_clk_enabled)) { in ufs_qcom_dev_ref_clk_ctrl()
674 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio); in ufs_qcom_dev_ref_clk_ctrl()
677 temp |= host->dev_ref_clk_en_mask; in ufs_qcom_dev_ref_clk_ctrl()
679 temp &= ~host->dev_ref_clk_en_mask; in ufs_qcom_dev_ref_clk_ctrl()
690 gating_wait = host->hba->dev_info.clk_gating_wait_us; in ufs_qcom_dev_ref_clk_ctrl()
698 * HS-MODE to LS-MODE or HIBERN8 state. Give it in ufs_qcom_dev_ref_clk_ctrl()
706 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio); in ufs_qcom_dev_ref_clk_ctrl()
712 readl(host->dev_ref_clk_ctrl_mmio); in ufs_qcom_dev_ref_clk_ctrl()
722 host->is_dev_ref_clk_enabled = enable; in ufs_qcom_dev_ref_clk_ctrl()
728 struct device *dev = host->hba->dev; in ufs_qcom_icc_set_bw()
731 ret = icc_set_bw(host->icc_ddr, 0, mem_bw); in ufs_qcom_icc_set_bw()
737 ret = icc_set_bw(host->icc_cpu, 0, cfg_bw); in ufs_qcom_icc_set_bw()
748 struct ufs_pa_layer_attr *p = &host->dev_req_params; in ufs_qcom_get_bw_table()
749 int gear = max_t(u32, p->gear_rx, p->gear_tx); in ufs_qcom_get_bw_table()
750 int lane = max_t(u32, p->lane_rx, p->lane_tx); in ufs_qcom_get_bw_table()
753 "ICC scaling for UFS Gear (%d) not supported. Using Gear (%d) bandwidth\n", in ufs_qcom_get_bw_table()
758 "ICC scaling for UFS Lane (%d) not supported. Using Lane (%d) bandwidth\n", in ufs_qcom_get_bw_table()
763 if (p->hs_rate == PA_HS_MODE_B) in ufs_qcom_get_bw_table()
787 struct ufs_host_params *host_params = &host->host_params; in ufs_qcom_pwr_change_notify()
792 return -EINVAL; in ufs_qcom_pwr_change_notify()
799 dev_err(hba->dev, "%s: failed to determine capabilities\n", in ufs_qcom_pwr_change_notify()
805 * During UFS driver probe, always update the PHY gear to match the negotiated in ufs_qcom_pwr_change_notify()
810 if (hba->ufshcd_state == UFSHCD_STATE_RESET) { in ufs_qcom_pwr_change_notify()
816 if (host->phy_gear == dev_req_params->gear_tx) in ufs_qcom_pwr_change_notify()
817 hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; in ufs_qcom_pwr_change_notify()
819 host->phy_gear = dev_req_params->gear_tx; in ufs_qcom_pwr_change_notify()
823 if (!ufshcd_is_hs_mode(&hba->pwr_info) && in ufs_qcom_pwr_change_notify()
827 if (host->hw_ver.major >= 0x4) { in ufs_qcom_pwr_change_notify()
829 dev_req_params->gear_tx, in ufs_qcom_pwr_change_notify()
834 if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx, in ufs_qcom_pwr_change_notify()
835 dev_req_params->pwr_rx, in ufs_qcom_pwr_change_notify()
836 dev_req_params->hs_rate, false, false)) { in ufs_qcom_pwr_change_notify()
837 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", in ufs_qcom_pwr_change_notify()
844 ret = -EINVAL; in ufs_qcom_pwr_change_notify()
848 memcpy(&host->dev_req_params, in ufs_qcom_pwr_change_notify()
854 if (ufshcd_is_hs_mode(&hba->pwr_info) && in ufs_qcom_pwr_change_notify()
859 ret = -EINVAL; in ufs_qcom_pwr_change_notify()
885 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME) in ufs_qcom_apply_dev_quirks()
891 /* UFS device-specific quirks */
916 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
919 * QCOM UFS host controller might have some non standard behaviours (quirks)
921 * quirks to standard UFS host controller driver so standard takes them into
926 const struct ufs_qcom_drvdata *drvdata = of_device_get_match_data(hba->dev); in ufs_qcom_advertise_quirks()
929 if (host->hw_ver.major == 0x2) in ufs_qcom_advertise_quirks()
930 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION; in ufs_qcom_advertise_quirks()
932 if (host->hw_ver.major > 0x3) in ufs_qcom_advertise_quirks()
933 hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; in ufs_qcom_advertise_quirks()
935 if (drvdata && drvdata->quirks) in ufs_qcom_advertise_quirks()
936 hba->quirks |= drvdata->quirks; in ufs_qcom_advertise_quirks()
941 struct ufs_host_params *host_params = &host->host_params; in ufs_qcom_set_phy_gear()
951 host->phy_gear = host_params->hs_tx_gear; in ufs_qcom_set_phy_gear()
953 if (host->hw_ver.major < 0x4) { in ufs_qcom_set_phy_gear()
959 host->phy_gear = UFS_HS_G2; in ufs_qcom_set_phy_gear()
960 } else if (host->hw_ver.major >= 0x5) { in ufs_qcom_set_phy_gear()
961 val = ufshcd_readl(host->hba, REG_UFS_DEBUG_SPARE_CFG); in ufs_qcom_set_phy_gear()
965 * Since the UFS device version is populated, let's remove the in ufs_qcom_set_phy_gear()
970 host->hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; in ufs_qcom_set_phy_gear()
973 * For UFS 3.1 device and older, power up the PHY using HS-G4 in ufs_qcom_set_phy_gear()
977 host->phy_gear = UFS_HS_G4; in ufs_qcom_set_phy_gear()
984 struct ufs_host_params *host_params = &host->host_params; in ufs_qcom_set_host_params()
989 host_params->hs_tx_gear = host_params->hs_rx_gear = ufs_qcom_get_hs_gear(hba); in ufs_qcom_set_host_params()
994 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; in ufs_qcom_set_caps()
995 hba->caps |= UFSHCD_CAP_CLK_SCALING | UFSHCD_CAP_WB_WITH_CLK_SCALING; in ufs_qcom_set_caps()
996 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND; in ufs_qcom_set_caps()
997 hba->caps |= UFSHCD_CAP_WB_EN; in ufs_qcom_set_caps()
998 hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE; in ufs_qcom_set_caps()
999 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND; in ufs_qcom_set_caps()
1003 * ufs_qcom_setup_clocks - enables/disable clocks
1008 * Return: 0 on success, non-zero on failure.
1037 if (ufshcd_is_hs_mode(&hba->pwr_info)) in ufs_qcom_setup_clocks()
1054 ufs_qcom_assert_reset(host->hba); in ufs_qcom_reset_assert()
1065 ufs_qcom_deassert_reset(host->hba); in ufs_qcom_reset_deassert()
1082 struct device *dev = host->hba->dev; in ufs_qcom_icc_init()
1085 host->icc_ddr = devm_of_icc_get(dev, "ufs-ddr"); in ufs_qcom_icc_init()
1086 if (IS_ERR(host->icc_ddr)) in ufs_qcom_icc_init()
1087 return dev_err_probe(dev, PTR_ERR(host->icc_ddr), in ufs_qcom_icc_init()
1090 host->icc_cpu = devm_of_icc_get(dev, "cpu-ufs"); in ufs_qcom_icc_init()
1091 if (IS_ERR(host->icc_cpu)) in ufs_qcom_icc_init()
1092 return dev_err_probe(dev, PTR_ERR(host->icc_cpu), in ufs_qcom_icc_init()
1096 * Set Maximum bandwidth vote before initializing the UFS controller and in ufs_qcom_icc_init()
1109 * ufs_qcom_init - bind phy with controller
1115 * Return: -EPROBE_DEFER if binding fails, returns negative error
1121 struct device *dev = hba->dev; in ufs_qcom_init()
1124 const struct ufs_qcom_drvdata *drvdata = of_device_get_match_data(hba->dev); in ufs_qcom_init()
1128 return -ENOMEM; in ufs_qcom_init()
1131 host->hba = hba; in ufs_qcom_init()
1135 host->core_reset = devm_reset_control_get_optional(hba->dev, "rst"); in ufs_qcom_init()
1136 if (IS_ERR(host->core_reset)) { in ufs_qcom_init()
1137 err = dev_err_probe(dev, PTR_ERR(host->core_reset), in ufs_qcom_init()
1142 /* Fire up the reset controller. Failure here is non-fatal. */ in ufs_qcom_init()
1143 host->rcdev.of_node = dev->of_node; in ufs_qcom_init()
1144 host->rcdev.ops = &ufs_qcom_reset_ops; in ufs_qcom_init()
1145 host->rcdev.owner = dev->driver->owner; in ufs_qcom_init()
1146 host->rcdev.nr_resets = 1; in ufs_qcom_init()
1147 err = devm_reset_controller_register(dev, &host->rcdev); in ufs_qcom_init()
1152 host->generic_phy = devm_phy_get(dev, "ufsphy"); in ufs_qcom_init()
1153 if (IS_ERR(host->generic_phy)) { in ufs_qcom_init()
1154 err = dev_err_probe(dev, PTR_ERR(host->generic_phy), "Failed to get PHY\n"); in ufs_qcom_init()
1163 host->device_reset = devm_gpiod_get_optional(dev, "reset", in ufs_qcom_init()
1165 if (IS_ERR(host->device_reset)) { in ufs_qcom_init()
1166 err = dev_err_probe(dev, PTR_ERR(host->device_reset), in ufs_qcom_init()
1171 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major, in ufs_qcom_init()
1172 &host->hw_ver.minor, &host->hw_ver.step); in ufs_qcom_init()
1174 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1; in ufs_qcom_init()
1175 host->dev_ref_clk_en_mask = BIT(26); in ufs_qcom_init()
1177 list_for_each_entry(clki, &hba->clk_list_head, list) { in ufs_qcom_init()
1178 if (!strcmp(clki->name, "core_clk_unipro")) in ufs_qcom_init()
1179 clki->keep_link_active = true; in ufs_qcom_init()
1200 /* Failure is non-fatal */ in ufs_qcom_init()
1204 if (drvdata && drvdata->no_phy_retention) in ufs_qcom_init()
1205 hba->spm_lvl = UFS_PM_LVL_5; in ufs_qcom_init()
1220 phy_power_off(host->generic_phy); in ufs_qcom_exit()
1221 phy_exit(host->generic_phy); in ufs_qcom_exit()
1225 * ufs_qcom_set_clk_40ns_cycles - Configure 40ns clk cycles
1242 * UFS host controller V4.0.0 onwards needs to program in ufs_qcom_set_clk_40ns_cycles()
1244 * frequency of unipro core clk of UFS host controller. in ufs_qcom_set_clk_40ns_cycles()
1246 if (host->hw_ver.major < 4) in ufs_qcom_set_clk_40ns_cycles()
1280 dev_err(hba->dev, "UNIPRO clk freq %u MHz not supported\n", in ufs_qcom_set_clk_40ns_cycles()
1282 return -EINVAL; in ufs_qcom_set_clk_40ns_cycles()
1298 struct list_head *head = &hba->clk_list_head; in ufs_qcom_set_core_clk_ctrl()
1305 if (!IS_ERR_OR_NULL(clki->clk) && in ufs_qcom_set_core_clk_ctrl()
1306 !strcmp(clki->name, "core_clk_unipro")) { in ufs_qcom_set_core_clk_ctrl()
1307 if (!clki->max_freq) in ufs_qcom_set_core_clk_ctrl()
1310 cycles_in_1us = ceil(clki->max_freq, (1000 * 1000)); in ufs_qcom_set_core_clk_ctrl()
1312 cycles_in_1us = ceil(clk_get_rate(clki->clk), (1000 * 1000)); in ufs_qcom_set_core_clk_ctrl()
1323 /* Bit mask is different for UFS host controller V4.0.0 onwards */ in ufs_qcom_set_core_clk_ctrl()
1324 if (host->hw_ver.major >= 4) { in ufs_qcom_set_core_clk_ctrl()
1326 return -ERANGE; in ufs_qcom_set_core_clk_ctrl()
1331 return -ERANGE; in ufs_qcom_set_core_clk_ctrl()
1352 struct ufs_pa_layer_attr *attr = &host->dev_req_params; in ufs_qcom_clk_scale_up_pre_change()
1355 ret = ufs_qcom_cfg_timers(hba, attr->gear_rx, attr->pwr_rx, in ufs_qcom_clk_scale_up_pre_change()
1356 attr->hs_rate, false, true); in ufs_qcom_clk_scale_up_pre_change()
1358 dev_err(hba->dev, "%s ufs cfg timer failed\n", __func__); in ufs_qcom_clk_scale_up_pre_change()
1441 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, in ufs_qcom_enable_test_bus()
1443 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1); in ufs_qcom_enable_test_bus()
1449 host->testbus.select_major = TSTBUS_UNIPRO; in ufs_qcom_get_default_testbus_cfg()
1450 host->testbus.select_minor = 37; in ufs_qcom_get_default_testbus_cfg()
1455 if (host->testbus.select_major >= TSTBUS_MAX) { in ufs_qcom_testbus_cfg_is_ok()
1456 dev_err(host->hba->dev, in ufs_qcom_testbus_cfg_is_ok()
1458 __func__, host->testbus.select_major); in ufs_qcom_testbus_cfg_is_ok()
1472 return -EINVAL; in ufs_qcom_testbus_config()
1475 return -EPERM; in ufs_qcom_testbus_config()
1477 switch (host->testbus.select_major) { in ufs_qcom_testbus_config()
1534 ufshcd_rmwl(host->hba, TEST_BUS_SEL, in ufs_qcom_testbus_config()
1535 (u32)host->testbus.select_major << 19, in ufs_qcom_testbus_config()
1537 ufshcd_rmwl(host->hba, mask, in ufs_qcom_testbus_config()
1538 (u32)host->testbus.select_minor << offset, in ufs_qcom_testbus_config()
1571 /* clear bit 17 - UTP_DBG_RAMS_EN */ in ufs_qcom_dump_dbg_regs()
1597 * ufs_qcom_device_reset() - toggle the (optional) device reset line
1598 * @hba: per-adapter instance
1607 if (!host->device_reset) in ufs_qcom_device_reset()
1608 return -EOPNOTSUPP; in ufs_qcom_device_reset()
1611 * The UFS device shall detect reset pulses of 1us, sleep for 10us to in ufs_qcom_device_reset()
1628 p->polling_ms = 60; in ufs_qcom_config_scaling_param()
1629 p->timer = DEVFREQ_TIMER_DELAYED; in ufs_qcom_config_scaling_param()
1630 d->upthreshold = 70; in ufs_qcom_config_scaling_param()
1631 d->downdifferential = 5; in ufs_qcom_config_scaling_param()
1633 hba->clk_scaling.suspend_on_no_request = true; in ufs_qcom_config_scaling_param()
1661 struct platform_device *pdev = to_platform_device(hba->dev); in ufs_qcom_mcq_config_resource()
1666 memcpy(hba->res, ufs_res_info, sizeof(ufs_res_info)); in ufs_qcom_mcq_config_resource()
1669 res = &hba->res[i]; in ufs_qcom_mcq_config_resource()
1670 res->resource = platform_get_resource_byname(pdev, in ufs_qcom_mcq_config_resource()
1672 res->name); in ufs_qcom_mcq_config_resource()
1673 if (!res->resource) { in ufs_qcom_mcq_config_resource()
1674 dev_info(hba->dev, "Resource %s not provided\n", res->name); in ufs_qcom_mcq_config_resource()
1676 return -ENODEV; in ufs_qcom_mcq_config_resource()
1679 res_mem = res->resource; in ufs_qcom_mcq_config_resource()
1680 res->base = hba->mmio_base; in ufs_qcom_mcq_config_resource()
1684 res->base = devm_ioremap_resource(hba->dev, res->resource); in ufs_qcom_mcq_config_resource()
1685 if (IS_ERR(res->base)) { in ufs_qcom_mcq_config_resource()
1686 dev_err(hba->dev, "Failed to map res %s, err=%d\n", in ufs_qcom_mcq_config_resource()
1687 res->name, (int)PTR_ERR(res->base)); in ufs_qcom_mcq_config_resource()
1688 ret = PTR_ERR(res->base); in ufs_qcom_mcq_config_resource()
1689 res->base = NULL; in ufs_qcom_mcq_config_resource()
1695 res = &hba->res[RES_MCQ]; in ufs_qcom_mcq_config_resource()
1697 if (res->base) in ufs_qcom_mcq_config_resource()
1701 res_mcq = devm_kzalloc(hba->dev, sizeof(*res_mcq), GFP_KERNEL); in ufs_qcom_mcq_config_resource()
1703 return -ENOMEM; in ufs_qcom_mcq_config_resource()
1705 res_mcq->start = res_mem->start + in ufs_qcom_mcq_config_resource()
1706 MCQ_SQATTR_OFFSET(hba->mcq_capabilities); in ufs_qcom_mcq_config_resource()
1707 res_mcq->end = res_mcq->start + hba->nr_hw_queues * MCQ_QCFG_SIZE - 1; in ufs_qcom_mcq_config_resource()
1708 res_mcq->flags = res_mem->flags; in ufs_qcom_mcq_config_resource()
1709 res_mcq->name = "mcq"; in ufs_qcom_mcq_config_resource()
1713 dev_err(hba->dev, "Failed to insert MCQ resource, err=%d\n", in ufs_qcom_mcq_config_resource()
1718 res->base = devm_ioremap_resource(hba->dev, res_mcq); in ufs_qcom_mcq_config_resource()
1719 if (IS_ERR(res->base)) { in ufs_qcom_mcq_config_resource()
1720 dev_err(hba->dev, "MCQ registers mapping failed, err=%d\n", in ufs_qcom_mcq_config_resource()
1721 (int)PTR_ERR(res->base)); in ufs_qcom_mcq_config_resource()
1722 ret = PTR_ERR(res->base); in ufs_qcom_mcq_config_resource()
1727 hba->mcq_base = res->base; in ufs_qcom_mcq_config_resource()
1730 res->base = NULL; in ufs_qcom_mcq_config_resource()
1741 mem_res = &hba->res[RES_UFS]; in ufs_qcom_op_runtime_config()
1742 sqdao_res = &hba->res[RES_MCQ_SQD]; in ufs_qcom_op_runtime_config()
1744 if (!mem_res->base || !sqdao_res->base) in ufs_qcom_op_runtime_config()
1745 return -EINVAL; in ufs_qcom_op_runtime_config()
1748 opr = &hba->mcq_opr[i]; in ufs_qcom_op_runtime_config()
1749 opr->offset = sqdao_res->resource->start - in ufs_qcom_op_runtime_config()
1750 mem_res->resource->start + 0x40 * i; in ufs_qcom_op_runtime_config()
1751 opr->stride = 0x100; in ufs_qcom_op_runtime_config()
1752 opr->base = sqdao_res->base + 0x40 * i; in ufs_qcom_op_runtime_config()
1767 struct ufshcd_res_info *mcq_vs_res = &hba->res[RES_MCQ_VS]; in ufs_qcom_get_outstanding_cqs()
1769 if (!mcq_vs_res->base) in ufs_qcom_get_outstanding_cqs()
1770 return -EINVAL; in ufs_qcom_get_outstanding_cqs()
1772 *ocqs = readl(mcq_vs_res->base + UFS_MEM_CQIS_VS); in ufs_qcom_get_outstanding_cqs()
1790 u32 id = desc->msi_index; in ufs_qcom_mcq_esi_handler()
1791 struct ufs_hw_queue *hwq = &hba->uhq[id]; in ufs_qcom_mcq_esi_handler()
1806 if (host->esi_enabled) in ufs_qcom_config_esi()
1813 nr_irqs = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL]; in ufs_qcom_config_esi()
1814 ret = platform_device_msi_init_and_alloc_irqs(hba->dev, nr_irqs, in ufs_qcom_config_esi()
1817 dev_err(hba->dev, "Failed to request Platform MSI %d\n", ret); in ufs_qcom_config_esi()
1821 msi_lock_descs(hba->dev); in ufs_qcom_config_esi()
1822 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) { in ufs_qcom_config_esi()
1823 ret = devm_request_irq(hba->dev, desc->irq, in ufs_qcom_config_esi()
1825 IRQF_SHARED, "qcom-mcq-esi", desc); in ufs_qcom_config_esi()
1827 dev_err(hba->dev, "%s: Fail to request IRQ for %d, err = %d\n", in ufs_qcom_config_esi()
1828 __func__, desc->irq, ret); in ufs_qcom_config_esi()
1833 msi_unlock_descs(hba->dev); in ufs_qcom_config_esi()
1837 msi_lock_descs(hba->dev); in ufs_qcom_config_esi()
1838 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) { in ufs_qcom_config_esi()
1841 devm_free_irq(hba->dev, desc->irq, hba); in ufs_qcom_config_esi()
1843 msi_unlock_descs(hba->dev); in ufs_qcom_config_esi()
1844 platform_device_msi_free_irqs_all(hba->dev); in ufs_qcom_config_esi()
1846 if (host->hw_ver.major == 6 && host->hw_ver.minor == 0 && in ufs_qcom_config_esi()
1847 host->hw_ver.step == 0) in ufs_qcom_config_esi()
1849 FIELD_PREP(ESI_VEC_MASK, MAX_ESI_VEC - 1), in ufs_qcom_config_esi()
1852 host->esi_enabled = true; in ufs_qcom_config_esi()
1859 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
1889 * ufs_qcom_probe - probe routine of the driver
1892 * Return: zero for success and non-zero for failure.
1897 struct device *dev = &pdev->dev; in ufs_qcom_probe()
1908 * ufs_qcom_remove - set driver_data of the device to NULL
1919 if (host->esi_enabled) in ufs_qcom_remove()
1920 platform_device_msi_free_irqs_all(hba->dev); in ufs_qcom_remove()
1930 { .compatible = "qcom,sm8550-ufshc", .data = &ufs_qcom_sm8550_drvdata },
1931 { .compatible = "qcom,sm8650-ufshc", .data = &ufs_qcom_sm8550_drvdata },
1961 .name = "ufshcd-qcom",
1969 MODULE_DESCRIPTION("Qualcomm UFS host controller driver");