Lines Matching +full:0 +full:xe4
14 #define PSW_POWER_CTRL (0x04)
15 #define PHY_ISO_EN (0x08)
16 #define HC_LP_CTRL (0x0C)
17 #define PHY_CLK_CTRL (0x10)
18 #define PSW_CLK_CTRL (0x14)
19 #define CLOCK_GATE_BYPASS (0x18)
20 #define RESET_CTRL_EN (0x1C)
21 #define UFS_SYSCTRL (0x5C)
22 #define UFS_DEVICE_RESET_CTRL (0x60)
25 #define BIT_UFS_PSW_MTCMOS_EN (1 << 0)
27 #define BIT_UFS_PHY_ISO_CTRL (1 << 0)
31 #define MASK_SYSCTRL_REF_CLOCK_SEL (0x3 << 8)
32 #define MASK_SYSCTRL_CFG_CLOCK_FREQ (0xFF)
33 #define UFS_FREQ_CFG_CLK (0x39)
35 #define MASK_UFS_CLK_GATE_BYPASS (0x3F)
36 #define BIT_SYSCTRL_LP_RESET_N (1 << 0)
37 #define BIT_UFS_REFCLK_SRC_SEl (1 << 0)
38 #define MASK_UFS_SYSCRTL_BYPASS (0x3F << 16)
39 #define MASK_UFS_DEVICE_RESET (0x1 << 16)
40 #define BIT_UFS_DEVICE_RESET (0x1)
45 #define MPHY_TX_FSM_STATE 0x41
46 #define TX_FSM_HIBERN8 0x1
52 UFS_REG_OCPTHRTL = 0xc0,
53 UFS_REG_OOCPR = 0xc4,
55 UFS_REG_CDACFG = 0xd0,
56 UFS_REG_CDATX1 = 0xd4,
57 UFS_REG_CDATX2 = 0xd8,
58 UFS_REG_CDARX1 = 0xdc,
59 UFS_REG_CDARX2 = 0xe0,
60 UFS_REG_CDASTA = 0xe4,
62 UFS_REG_LBMCFG = 0xf0,
63 UFS_REG_LBMSTA = 0xf4,
64 UFS_REG_UFSMODE = 0xf8,
66 UFS_REG_HCLKDIV = 0xfc,
70 #define UFS_AHIT_AH8ITV_MASK 0x3FF
73 #define UFS_HCLKDIV_NORMAL_VALUE 0xE4
79 #define UFS_HISI_CAP_RESERVED BIT(0)