Lines Matching +full:v +full:- +full:bit

1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd.
41 * results in non-functioning UFS.
55 #define TX_LINERESET_N(v) (((v) >> 10) & 0xFF) argument
57 #define TX_LINERESET_P(v) (((v) >> 12) & 0xFF) argument
60 #define TX_OV_SLEEP_CNT(v) (((v) >> 5) & 0x7F) argument
62 #define TX_HIGH_Z_CNT_H(v) (((v) >> 8) & 0xF) argument
64 #define TX_HIGH_Z_CNT_L(v) ((v) & 0xFF) argument
66 #define TX_BASE_NVAL_L(v) ((v) & 0xFF) argument
68 #define TX_BASE_NVAL_H(v) (((v) >> 8) & 0xFF) argument
70 #define TX_GRAN_NVAL_L(v) ((v) & 0xFF) argument
72 #define TX_GRAN_NVAL_H(v) (((v) >> 8) & 0x3) argument
93 #define RX_LINERESET(v) (((v) >> 12) & 0xFF) argument
100 #define RX_OV_SLEEP_CNT(v) (((v) >> 6) & 0x1F) argument
102 #define RX_OV_STALL_CNT(v) (((v) >> 4) & 0xFF) argument
104 #define RX_BASE_NVAL_L(v) ((v) & 0xFF) argument
106 #define RX_BASE_NVAL_H(v) (((v) >> 8) & 0xFF) argument
108 #define RX_GRAN_NVAL_L(v) ((v) & 0xFF) argument
110 #define RX_GRAN_NVAL_H(v) (((v) >> 8) & 0x3) argument
116 #define UNIPRO_PCLK_PERIOD(ufs) (NSEC_PER_SEC / ufs->pclk_rate)
120 /* vendor specific pre-defined parameters */
239 #define EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL BIT(0)
240 #define EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB BIT(1)
241 #define EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL BIT(2)
242 #define EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX BIT(3)
243 #define EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER BIT(4)
244 #define EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR BIT(5)
245 #define EXYNOS_UFS_OPT_UFSPR_SECURE BIT(6)
246 #define EXYNOS_UFS_OPT_TIMER_TICK_SELECT BIT(7)
250 for (i = (ufs)->rx_sel_idx; \
251 i < (ufs)->rx_sel_idx + (ufs)->avail_ln_rx; i++)
253 for (i = 0; i < (ufs)->avail_ln_tx; i++)
258 writel(val, ufs->reg_##name + reg); \
263 return readl(ufs->reg_##name + reg); \