Lines Matching +full:0 +full:x0402

16 #define COMP_CLK_PERIOD	0x44
21 #define UNIPRO_DBG_FORCE_DME_CTRL_STATE		0x150
26 #define PA_DBG_CLK_PERIOD	0x9514
27 #define PA_DBG_TXPHY_CFGUPDT	0x9518
28 #define PA_DBG_RXPHY_CFGUPDT	0x9519
29 #define PA_DBG_MODE		0x9529
30 #define PA_DBG_SKIP_RESET_PHY	0x9539
31 #define PA_DBG_AUTOMODE_THLD	0x9536
32 #define PA_DBG_OV_TM		0x9540
33 #define PA_DBG_SKIP_LINE_RESET	0x9541
34 #define PA_DBG_LINE_RESET_REQ	0x9543
35 #define PA_DBG_OPTION_SUITE	0x9564
36 #define PA_DBG_OPTION_SUITE_DYN	0x9565
43 #define PA_GS101_DBG_OPTION_SUITE1 0x956a
44 #define PA_GS101_DBG_OPTION_SUITE2 0x956d
49 #define T_DBG_SKIP_INIT_HIBERN8_EXIT	0xc001
54 #define TX_LINERESET_N_VAL	0x0277
55 #define TX_LINERESET_N(v)	(((v) >> 10) & 0xFF)
56 #define TX_LINERESET_P_VAL	0x027D
57 #define TX_LINERESET_P(v)	(((v) >> 12) & 0xFF)
58 #define TX_OV_SLEEP_CNT_TIMER	0x028E
60 #define TX_OV_SLEEP_CNT(v)	(((v) >> 5) & 0x7F)
61 #define TX_HIGH_Z_CNT_11_08	0x028C
62 #define TX_HIGH_Z_CNT_H(v)	(((v) >> 8) & 0xF)
63 #define TX_HIGH_Z_CNT_07_00	0x028D
64 #define TX_HIGH_Z_CNT_L(v)	((v) & 0xFF)
65 #define TX_BASE_NVAL_07_00	0x0293
66 #define TX_BASE_NVAL_L(v)	((v) & 0xFF)
67 #define TX_BASE_NVAL_15_08	0x0294
68 #define TX_BASE_NVAL_H(v)	(((v) >> 8) & 0xFF)
69 #define TX_GRAN_NVAL_07_00	0x0295
70 #define TX_GRAN_NVAL_L(v)	((v) & 0xFF)
71 #define TX_GRAN_NVAL_10_08	0x0296
72 #define TX_GRAN_NVAL_H(v)	(((v) >> 8) & 0x3)
74 #define VND_TX_CLK_PRD		0xAA
75 #define VND_TX_CLK_PRD_EN	0xA9
76 #define VND_TX_LINERESET_PVALUE0	0xAD
77 #define VND_TX_LINERESET_PVALUE1	0xAC
78 #define VND_TX_LINERESET_PVALUE2	0xAB
82 #define VND_RX_CLK_PRD		0x12
83 #define VND_RX_CLK_PRD_EN	0x11
84 #define VND_RX_LINERESET_VALUE0	0x1D
85 #define VND_RX_LINERESET_VALUE1	0x1C
86 #define VND_RX_LINERESET_VALUE2	0x1B
90 #define RX_FILLER_ENABLE	0x0316
92 #define RX_LINERESET_VAL	0x0317
93 #define RX_LINERESET(v)	(((v) >> 12) & 0xFF)
94 #define RX_LCC_IGNORE		0x0318
95 #define RX_SYNC_MASK_LENGTH	0x0321
96 #define RX_HIBERN8_WAIT_VAL_BIT_20_16	0x0331
97 #define RX_HIBERN8_WAIT_VAL_BIT_15_08	0x0332
98 #define RX_HIBERN8_WAIT_VAL_BIT_07_00	0x0333
99 #define RX_OV_SLEEP_CNT_TIMER	0x0340
100 #define RX_OV_SLEEP_CNT(v)	(((v) >> 6) & 0x1F)
101 #define RX_OV_STALL_CNT_TIMER	0x0341
102 #define RX_OV_STALL_CNT(v)	(((v) >> 4) & 0xFF)
103 #define RX_BASE_NVAL_07_00	0x0355
104 #define RX_BASE_NVAL_L(v)	((v) & 0xFF)
105 #define RX_BASE_NVAL_15_08	0x0354
106 #define RX_BASE_NVAL_H(v)	(((v) >> 8) & 0xFF)
107 #define RX_GRAN_NVAL_07_00	0x0353
108 #define RX_GRAN_NVAL_L(v)	((v) & 0xFF)
109 #define RX_GRAN_NVAL_10_08	0x0352
110 #define RX_GRAN_NVAL_H(v)	(((v) >> 8) & 0x3)
112 #define CMN_PWM_CLK_CTRL	0x0402
113 #define PWM_CLK_CTRL_MASK	0x3
124 #define RX_ADV_FINE_GRAN_SUP_EN	0x1
125 #define RX_ADV_FINE_GRAN_STEP_VAL	0x3
126 #define RX_ADV_MIN_ACTV_TIME_CAP	0x9
128 #define PA_GRANULARITY_VAL	0x6
129 #define PA_TACTIVATE_VAL	0x3
130 #define PA_HIBERN8TIME_VAL	0x20
239 #define EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL		BIT(0)
253 	for (i = 0; i < (ufs)->avail_ln_tx; i++)