Lines Matching +full:fsd +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd.
13 #include <linux/arm-smccc.h>
14 #include <linux/clk.h>
25 #include "ufshcd-pltfrm.h"
29 #include "ufs-exynos.h"
106 /* Multi-host registers */
215 if (ufs->sysreg) { in exynos_ufs_shareability()
216 return regmap_update_bits(ufs->sysreg, in exynos_ufs_shareability()
217 ufs->iocc_offset, in exynos_ufs_shareability()
218 ufs->iocc_mask, ufs->iocc_val); in exynos_ufs_shareability()
226 struct ufs_hba *hba = ufs->hba; in gs101_ufs_drv_init()
230 hba->caps |= UFSHCD_CAP_WB_EN; in gs101_ufs_drv_init()
233 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; in gs101_ufs_drv_init()
249 struct ufs_hba *hba = ufs->hba; in exynosauto_ufs_post_hce_enable()
263 struct ufs_hba *hba = ufs->hba; in exynosauto_ufs_pre_link()
267 rx_line_reset_period = (RX_LINE_RESET_TIME * ufs->mclk_rate) / NSEC_PER_MSEC; in exynosauto_ufs_pre_link()
268 tx_line_reset_period = (TX_LINE_RESET_TIME * ufs->mclk_rate) / NSEC_PER_MSEC; in exynosauto_ufs_pre_link()
273 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in exynosauto_ufs_pre_link()
290 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in exynosauto_ufs_pre_link()
318 struct ufs_hba *hba = ufs->hba; in exynosauto_ufs_pre_pwr_change()
331 struct ufs_hba *hba = ufs->hba; in exynosauto_ufs_post_pwr_change()
344 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos7_ufs_pre_link()
345 u32 val = attr->pa_dbg_opt_suite1_val; in exynos7_ufs_pre_link()
346 struct ufs_hba *hba = ufs->hba; in exynos7_ufs_pre_link()
363 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), in exynos7_ufs_pre_link()
369 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), val); in exynos7_ufs_pre_link()
376 struct ufs_hba *hba = ufs->hba; in exynos7_ufs_post_link()
406 struct ufs_hba *hba = ufs->hba; in exynos7_ufs_post_pwr_change()
407 int lanes = max_t(u32, pwr->lane_rx, pwr->lane_tx); in exynos7_ufs_post_pwr_change()
421 * exynos_ufs_auto_ctrl_hcc - HCI core clock control by h/w
423 * - Before host controller S/W reset
424 * - Access to UFS protector's register
452 struct ufs_hba *hba = ufs->hba; in exynos_ufs_get_clk_info()
453 struct list_head *head = &hba->clk_list_head; in exynos_ufs_get_clk_info()
464 if (!IS_ERR(clki->clk)) { in exynos_ufs_get_clk_info()
465 if (!strcmp(clki->name, "core_clk")) in exynos_ufs_get_clk_info()
466 ufs->clk_hci_core = clki->clk; in exynos_ufs_get_clk_info()
467 else if (!strcmp(clki->name, "sclk_unipro_main")) in exynos_ufs_get_clk_info()
468 ufs->clk_unipro_main = clki->clk; in exynos_ufs_get_clk_info()
472 if (!ufs->clk_hci_core || !ufs->clk_unipro_main) { in exynos_ufs_get_clk_info()
473 dev_err(hba->dev, "failed to get clk info\n"); in exynos_ufs_get_clk_info()
474 ret = -EINVAL; in exynos_ufs_get_clk_info()
478 ufs->mclk_rate = clk_get_rate(ufs->clk_unipro_main); in exynos_ufs_get_clk_info()
479 pclk_rate = clk_get_rate(ufs->clk_hci_core); in exynos_ufs_get_clk_info()
480 f_min = ufs->pclk_avail_min; in exynos_ufs_get_clk_info()
481 f_max = ufs->pclk_avail_max; in exynos_ufs_get_clk_info()
483 if (ufs->opts & EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL) { in exynos_ufs_get_clk_info()
494 dev_err(hba->dev, "not available pclk range %lu\n", pclk_rate); in exynos_ufs_get_clk_info()
495 ret = -EINVAL; in exynos_ufs_get_clk_info()
499 ufs->pclk_rate = pclk_rate; in exynos_ufs_get_clk_info()
500 ufs->pclk_div = div; in exynos_ufs_get_clk_info()
508 if (ufs->opts & EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL) { in exynos_ufs_set_unipro_pclk_div()
512 hci_writel(ufs, UNIPRO_APB_CLK(val, ufs->pclk_div), in exynos_ufs_set_unipro_pclk_div()
519 struct ufs_hba *hba = ufs->hba; in exynos_ufs_set_pwm_clk_div()
520 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_set_pwm_clk_div()
523 UIC_ARG_MIB(CMN_PWM_CLK_CTRL), attr->cmn_pwm_clk_ctrl); in exynos_ufs_set_pwm_clk_div()
528 struct ufs_hba *hba = ufs->hba; in exynos_ufs_calc_pwm_clk_div()
529 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_calc_pwm_clk_div()
534 unsigned long clk = 0, _clk, clk_period; in exynos_ufs_calc_pwm_clk_div() local
535 int i = 0, clk_idx = -1; in exynos_ufs_calc_pwm_clk_div()
541 if (_clk > clk) { in exynos_ufs_calc_pwm_clk_div()
543 clk = _clk; in exynos_ufs_calc_pwm_clk_div()
548 if (clk_idx == -1) { in exynos_ufs_calc_pwm_clk_div()
550 dev_err(hba->dev, in exynos_ufs_calc_pwm_clk_div()
554 attr->cmn_pwm_clk_ctrl = clk_idx & PWM_CLK_CTRL_MASK; in exynos_ufs_calc_pwm_clk_div()
560 long pclk_rate = ufs->pclk_rate; in exynos_ufs_calc_time_cntr()
571 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_specify_phy_time_attr()
572 struct ufs_phy_time_cfg *t_cfg = &ufs->t_cfg; in exynos_ufs_specify_phy_time_attr()
574 if (ufs->opts & EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR) in exynos_ufs_specify_phy_time_attr()
577 t_cfg->tx_linereset_p = in exynos_ufs_specify_phy_time_attr()
578 exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_p_nsec); in exynos_ufs_specify_phy_time_attr()
579 t_cfg->tx_linereset_n = in exynos_ufs_specify_phy_time_attr()
580 exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_n_nsec); in exynos_ufs_specify_phy_time_attr()
581 t_cfg->tx_high_z_cnt = in exynos_ufs_specify_phy_time_attr()
582 exynos_ufs_calc_time_cntr(ufs, attr->tx_high_z_cnt_nsec); in exynos_ufs_specify_phy_time_attr()
583 t_cfg->tx_base_n_val = in exynos_ufs_specify_phy_time_attr()
584 exynos_ufs_calc_time_cntr(ufs, attr->tx_base_unit_nsec); in exynos_ufs_specify_phy_time_attr()
585 t_cfg->tx_gran_n_val = in exynos_ufs_specify_phy_time_attr()
586 exynos_ufs_calc_time_cntr(ufs, attr->tx_gran_unit_nsec); in exynos_ufs_specify_phy_time_attr()
587 t_cfg->tx_sleep_cnt = in exynos_ufs_specify_phy_time_attr()
588 exynos_ufs_calc_time_cntr(ufs, attr->tx_sleep_cnt); in exynos_ufs_specify_phy_time_attr()
590 t_cfg->rx_linereset = in exynos_ufs_specify_phy_time_attr()
591 exynos_ufs_calc_time_cntr(ufs, attr->rx_dif_p_nsec); in exynos_ufs_specify_phy_time_attr()
592 t_cfg->rx_hibern8_wait = in exynos_ufs_specify_phy_time_attr()
593 exynos_ufs_calc_time_cntr(ufs, attr->rx_hibern8_wait_nsec); in exynos_ufs_specify_phy_time_attr()
594 t_cfg->rx_base_n_val = in exynos_ufs_specify_phy_time_attr()
595 exynos_ufs_calc_time_cntr(ufs, attr->rx_base_unit_nsec); in exynos_ufs_specify_phy_time_attr()
596 t_cfg->rx_gran_n_val = in exynos_ufs_specify_phy_time_attr()
597 exynos_ufs_calc_time_cntr(ufs, attr->rx_gran_unit_nsec); in exynos_ufs_specify_phy_time_attr()
598 t_cfg->rx_sleep_cnt = in exynos_ufs_specify_phy_time_attr()
599 exynos_ufs_calc_time_cntr(ufs, attr->rx_sleep_cnt); in exynos_ufs_specify_phy_time_attr()
600 t_cfg->rx_stall_cnt = in exynos_ufs_specify_phy_time_attr()
601 exynos_ufs_calc_time_cntr(ufs, attr->rx_stall_cnt); in exynos_ufs_specify_phy_time_attr()
606 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_phy_time_attr()
607 struct ufs_phy_time_cfg *t_cfg = &ufs->t_cfg; in exynos_ufs_config_phy_time_attr()
616 ufs->drv_data->uic_attr->rx_filler_enable); in exynos_ufs_config_phy_time_attr()
618 RX_LINERESET(t_cfg->rx_linereset)); in exynos_ufs_config_phy_time_attr()
620 RX_BASE_NVAL_L(t_cfg->rx_base_n_val)); in exynos_ufs_config_phy_time_attr()
622 RX_BASE_NVAL_H(t_cfg->rx_base_n_val)); in exynos_ufs_config_phy_time_attr()
624 RX_GRAN_NVAL_L(t_cfg->rx_gran_n_val)); in exynos_ufs_config_phy_time_attr()
626 RX_GRAN_NVAL_H(t_cfg->rx_gran_n_val)); in exynos_ufs_config_phy_time_attr()
628 RX_OV_SLEEP_CNT(t_cfg->rx_sleep_cnt)); in exynos_ufs_config_phy_time_attr()
630 RX_OV_STALL_CNT(t_cfg->rx_stall_cnt)); in exynos_ufs_config_phy_time_attr()
635 TX_LINERESET_P(t_cfg->tx_linereset_p)); in exynos_ufs_config_phy_time_attr()
637 TX_HIGH_Z_CNT_L(t_cfg->tx_high_z_cnt)); in exynos_ufs_config_phy_time_attr()
639 TX_HIGH_Z_CNT_H(t_cfg->tx_high_z_cnt)); in exynos_ufs_config_phy_time_attr()
641 TX_BASE_NVAL_L(t_cfg->tx_base_n_val)); in exynos_ufs_config_phy_time_attr()
643 TX_BASE_NVAL_H(t_cfg->tx_base_n_val)); in exynos_ufs_config_phy_time_attr()
645 TX_GRAN_NVAL_L(t_cfg->tx_gran_n_val)); in exynos_ufs_config_phy_time_attr()
647 TX_GRAN_NVAL_H(t_cfg->tx_gran_n_val)); in exynos_ufs_config_phy_time_attr()
650 TX_OV_SLEEP_CNT(t_cfg->tx_sleep_cnt)); in exynos_ufs_config_phy_time_attr()
652 ufs->drv_data->uic_attr->tx_min_activatetime); in exynos_ufs_config_phy_time_attr()
660 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_phy_cap_attr()
661 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_config_phy_cap_attr()
669 attr->rx_hs_g1_sync_len_cap); in exynos_ufs_config_phy_cap_attr()
672 attr->rx_hs_g2_sync_len_cap); in exynos_ufs_config_phy_cap_attr()
675 attr->rx_hs_g3_sync_len_cap); in exynos_ufs_config_phy_cap_attr()
678 attr->rx_hs_g1_prep_sync_len_cap); in exynos_ufs_config_phy_cap_attr()
681 attr->rx_hs_g2_prep_sync_len_cap); in exynos_ufs_config_phy_cap_attr()
684 attr->rx_hs_g3_prep_sync_len_cap); in exynos_ufs_config_phy_cap_attr()
687 if (attr->rx_adv_fine_gran_sup_en == 0) { in exynos_ufs_config_phy_cap_attr()
692 if (attr->rx_min_actv_time_cap) in exynos_ufs_config_phy_cap_attr()
696 attr->rx_min_actv_time_cap); in exynos_ufs_config_phy_cap_attr()
698 if (attr->rx_hibern8_time_cap) in exynos_ufs_config_phy_cap_attr()
701 attr->rx_hibern8_time_cap); in exynos_ufs_config_phy_cap_attr()
703 } else if (attr->rx_adv_fine_gran_sup_en == 1) { in exynos_ufs_config_phy_cap_attr()
705 if (attr->rx_adv_fine_gran_step) in exynos_ufs_config_phy_cap_attr()
709 attr->rx_adv_fine_gran_step)); in exynos_ufs_config_phy_cap_attr()
711 if (attr->rx_adv_min_actv_time_cap) in exynos_ufs_config_phy_cap_attr()
715 attr->rx_adv_min_actv_time_cap); in exynos_ufs_config_phy_cap_attr()
717 if (attr->rx_adv_hibern8_time_cap) in exynos_ufs_config_phy_cap_attr()
721 attr->rx_adv_hibern8_time_cap); in exynos_ufs_config_phy_cap_attr()
730 struct ufs_hba *hba = ufs->hba; in exynos_ufs_establish_connt()
755 if (ufs->opts & EXYNOS_UFS_OPT_UFSPR_SECURE) in exynos_ufs_config_smu()
774 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_sync_pattern_mask()
775 u8 g = max_t(u32, pwr->gear_rx, pwr->gear_tx); in exynos_ufs_config_sync_pattern_mask()
811 major = FIELD_GET(UFS_HW_VER_MAJOR_MASK, hba->ufs_version); in exynos_ufs_get_hs_gear()
816 /* Default is HS-G3 */ in exynos_ufs_get_hs_gear()
825 struct phy *generic_phy = ufs->phy; in exynos_ufs_pre_pwr_mode()
831 ret = -EINVAL; in exynos_ufs_pre_pwr_mode()
847 if (ufs->drv_data->pre_pwr_change) in exynos_ufs_pre_pwr_mode()
848 ufs->drv_data->pre_pwr_change(ufs, dev_req_params); in exynos_ufs_pre_pwr_mode()
853 switch (dev_req_params->hs_rate) { in exynos_ufs_pre_pwr_mode()
876 struct phy *generic_phy = ufs->phy; in exynos_ufs_post_pwr_mode()
877 int gear = max_t(u32, pwr_req->gear_rx, pwr_req->gear_tx); in exynos_ufs_post_pwr_mode()
878 int lanes = max_t(u32, pwr_req->lane_rx, pwr_req->lane_tx); in exynos_ufs_post_pwr_mode()
888 if (ufs->drv_data->post_pwr_change) in exynos_ufs_post_pwr_mode()
889 ufs->drv_data->post_pwr_change(ufs, pwr_req); in exynos_ufs_post_pwr_mode()
892 switch (pwr_req->hs_rate) { in exynos_ufs_post_pwr_mode()
900 "FAST", pwr_req->hs_rate == PA_HS_MODE_A ? "A" : "B", in exynos_ufs_post_pwr_mode()
907 dev_info(hba->dev, "Power mode changed to : %s\n", pwr_str); in exynos_ufs_post_pwr_mode()
950 struct ufs_hba *hba = ufs->hba; in exynos_ufs_phy_init()
951 struct phy *generic_phy = ufs->phy; in exynos_ufs_phy_init()
954 if (ufs->avail_ln_rx == 0 || ufs->avail_ln_tx == 0) { in exynos_ufs_phy_init()
956 &ufs->avail_ln_rx); in exynos_ufs_phy_init()
958 &ufs->avail_ln_tx); in exynos_ufs_phy_init()
959 WARN(ufs->avail_ln_rx != ufs->avail_ln_tx, in exynos_ufs_phy_init()
961 ufs->avail_ln_rx, ufs->avail_ln_tx); in exynos_ufs_phy_init()
964 phy_set_bus_width(generic_phy, ufs->avail_ln_rx); in exynos_ufs_phy_init()
966 if (generic_phy->power_count) { in exynos_ufs_phy_init()
973 dev_err(hba->dev, "%s: phy init failed, ret = %d\n", in exynos_ufs_phy_init()
992 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_config_unipro()
993 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_unipro()
995 if (attr->pa_dbg_clk_period_off) in exynos_ufs_config_unipro()
996 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_clk_period_off), in exynos_ufs_config_unipro()
997 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in exynos_ufs_config_unipro()
1000 ufs->drv_data->uic_attr->tx_trailingclks); in exynos_ufs_config_unipro()
1002 if (attr->pa_dbg_opt_suite1_off) in exynos_ufs_config_unipro()
1003 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), in exynos_ufs_config_unipro()
1004 attr->pa_dbg_opt_suite1_val); in exynos_ufs_config_unipro()
1006 if (attr->pa_dbg_opt_suite2_off) in exynos_ufs_config_unipro()
1007 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite2_off), in exynos_ufs_config_unipro()
1008 attr->pa_dbg_opt_suite2_val); in exynos_ufs_config_unipro()
1041 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) in exynos_ufs_setup_clocks()
1046 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) in exynos_ufs_setup_clocks()
1066 /* m-phy */ in exynos_ufs_pre_link()
1068 if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR)) { in exynos_ufs_pre_link()
1075 if (ufs->drv_data->pre_link) in exynos_ufs_pre_link()
1076 ufs->drv_data->pre_link(ufs); in exynos_ufs_pre_link()
1086 if (ufs->opts & EXYNOS_UFS_OPT_TIMER_TICK_SELECT) { in exynos_ufs_fit_aggr_timeout()
1099 struct phy *generic_phy = ufs->phy; in exynos_ufs_post_link()
1100 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_post_link()
1108 hci_writel(ufs, (1 << hba->nutrs) - 1, HCI_UTRL_NEXUS_TYPE); in exynos_ufs_post_link()
1109 hci_writel(ufs, (1 << hba->nutmrs) - 1, HCI_UTMRL_NEXUS_TYPE); in exynos_ufs_post_link()
1112 if (ufs->opts & EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB) in exynos_ufs_post_link()
1116 if (attr->pa_granularity) { in exynos_ufs_post_link()
1119 attr->pa_granularity); in exynos_ufs_post_link()
1122 if (attr->pa_tactivate) in exynos_ufs_post_link()
1124 attr->pa_tactivate); in exynos_ufs_post_link()
1125 if (attr->pa_hibern8time && in exynos_ufs_post_link()
1126 !(ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER)) in exynos_ufs_post_link()
1128 attr->pa_hibern8time); in exynos_ufs_post_link()
1131 if (ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER) { in exynos_ufs_post_link()
1132 if (!attr->pa_granularity) in exynos_ufs_post_link()
1134 &attr->pa_granularity); in exynos_ufs_post_link()
1135 if (!attr->pa_hibern8time) in exynos_ufs_post_link()
1137 &attr->pa_hibern8time); in exynos_ufs_post_link()
1143 if (attr->pa_granularity < 1 || attr->pa_granularity > 6) { in exynos_ufs_post_link()
1145 dev_warn(hba->dev, in exynos_ufs_post_link()
1148 attr->pa_granularity); in exynos_ufs_post_link()
1149 attr->pa_granularity = 6; in exynos_ufs_post_link()
1155 if (ufs->drv_data->post_link) in exynos_ufs_post_link()
1156 ufs->drv_data->post_link(ufs); in exynos_ufs_post_link()
1163 struct device_node *np = dev->of_node; in exynos_ufs_parse_dt()
1167 ufs->drv_data = device_get_match_data(dev); in exynos_ufs_parse_dt()
1169 if (ufs->drv_data && ufs->drv_data->uic_attr) { in exynos_ufs_parse_dt()
1170 attr = ufs->drv_data->uic_attr; in exynos_ufs_parse_dt()
1173 ret = -EINVAL; in exynos_ufs_parse_dt()
1177 ufs->sysreg = syscon_regmap_lookup_by_phandle(np, "samsung,sysreg"); in exynos_ufs_parse_dt()
1178 if (IS_ERR(ufs->sysreg)) in exynos_ufs_parse_dt()
1179 ufs->sysreg = NULL; in exynos_ufs_parse_dt()
1182 &ufs->iocc_offset)) { in exynos_ufs_parse_dt()
1184 ufs->iocc_offset = UFS_SHAREABILITY_OFFSET; in exynos_ufs_parse_dt()
1188 ufs->iocc_mask = ufs->drv_data->iocc_mask; in exynos_ufs_parse_dt()
1190 * no 'dma-coherent' property means the descriptors are in exynos_ufs_parse_dt()
1191 * non-cacheable so iocc shareability should be disabled. in exynos_ufs_parse_dt()
1193 if (of_dma_is_coherent(dev->of_node)) in exynos_ufs_parse_dt()
1194 ufs->iocc_val = ufs->iocc_mask; in exynos_ufs_parse_dt()
1196 ufs->iocc_val = 0; in exynos_ufs_parse_dt()
1198 ufs->pclk_avail_min = PCLK_AVAIL_MIN; in exynos_ufs_parse_dt()
1199 ufs->pclk_avail_max = PCLK_AVAIL_MAX; in exynos_ufs_parse_dt()
1201 attr->rx_adv_fine_gran_sup_en = RX_ADV_FINE_GRAN_SUP_EN; in exynos_ufs_parse_dt()
1202 attr->rx_adv_fine_gran_step = RX_ADV_FINE_GRAN_STEP_VAL; in exynos_ufs_parse_dt()
1203 attr->rx_adv_min_actv_time_cap = RX_ADV_MIN_ACTV_TIME_CAP; in exynos_ufs_parse_dt()
1204 attr->pa_granularity = PA_GRANULARITY_VAL; in exynos_ufs_parse_dt()
1205 attr->pa_tactivate = PA_TACTIVATE_VAL; in exynos_ufs_parse_dt()
1206 attr->pa_hibern8time = PA_HIBERN8TIME_VAL; in exynos_ufs_parse_dt()
1215 ufs->hba = hba; in exynos_ufs_priv_init()
1216 ufs->opts = ufs->drv_data->opts; in exynos_ufs_priv_init()
1217 ufs->rx_sel_idx = PA_MAXDATALANES; in exynos_ufs_priv_init()
1218 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX) in exynos_ufs_priv_init()
1219 ufs->rx_sel_idx = 0; in exynos_ufs_priv_init()
1220 hba->priv = (void *)ufs; in exynos_ufs_priv_init()
1221 hba->quirks = ufs->drv_data->quirks; in exynos_ufs_priv_init()
1228 * hardware on Exynos and Exynos-based SoCs. The interface to this hardware is
1243 * struct fmp_sg_entry - nonstandard format of PRDT entries when FMP is enabled
1246 * bits of the 'size' field, i.e. the last 32-bit word. When these
1251 * @file_enckey: The first half of the AES-XTS key with all bytes reserved
1252 * @file_twkey: The second half of the AES-XTS key with all bytes reserved
1280 struct blk_crypto_profile *profile = &hba->crypto_profile; in exynos_ufs_fmp_init()
1297 * downstream driver source for gs101 and other Exynos-based SoCs. It in exynos_ufs_fmp_init()
1300 * on other Exynos-based SoCs too, and might even still be the only way in exynos_ufs_fmp_init()
1305 if (!(ufs->opts & EXYNOS_UFS_OPT_UFSPR_SECURE)) in exynos_ufs_fmp_init()
1316 dev_warn(hba->dev, in exynos_ufs_fmp_init()
1329 dev_err(hba->dev, in exynos_ufs_fmp_init()
1336 err = devm_blk_crypto_profile_init(hba->dev, profile, 0); in exynos_ufs_fmp_init()
1339 dev_err(hba->dev, "Failed to initialize crypto profile: %d\n", in exynos_ufs_fmp_init()
1343 profile->max_dun_bytes_supported = AES_BLOCK_SIZE; in exynos_ufs_fmp_init()
1344 profile->dev = hba->dev; in exynos_ufs_fmp_init()
1345 profile->modes_supported[BLK_ENCRYPTION_MODE_AES_256_XTS] = in exynos_ufs_fmp_init()
1348 /* Advertise crypto support to ufshcd-core. */ in exynos_ufs_fmp_init()
1349 hba->caps |= UFSHCD_CAP_CRYPTO; in exynos_ufs_fmp_init()
1351 /* Advertise crypto quirks to ufshcd-core. */ in exynos_ufs_fmp_init()
1352 hba->quirks |= UFSHCD_QUIRK_CUSTOM_CRYPTO_PROFILE | in exynos_ufs_fmp_init()
1362 if (!(hba->caps & UFSHCD_CAP_CRYPTO)) in exynos_ufs_fmp_resume()
1368 dev_err(hba->dev, in exynos_ufs_fmp_resume()
1374 dev_err(hba->dev, in exynos_ufs_fmp_resume()
1381 key + AES_KEYSIZE_256 - (j + 1) * sizeof(u64))); in fmp_key_word()
1390 const u8 *enckey = crypt_ctx->bc_key->raw; in exynos_ufs_fmp_fill_prdt()
1392 u64 dun_lo = crypt_ctx->bc_dun[0]; in exynos_ufs_fmp_fill_prdt()
1393 u64 dun_hi = crypt_ctx->bc_dun[1]; in exynos_ufs_fmp_fill_prdt()
1397 if (WARN_ON_ONCE(!(hba->caps & UFSHCD_CAP_CRYPTO))) in exynos_ufs_fmp_fill_prdt()
1398 return -EIO; in exynos_ufs_fmp_fill_prdt()
1406 if (prd->base.size != cpu_to_le32(DATA_UNIT_SIZE - 1)) { in exynos_ufs_fmp_fill_prdt()
1407 dev_err(hba->dev, in exynos_ufs_fmp_fill_prdt()
1409 return -EIO; in exynos_ufs_fmp_fill_prdt()
1413 prd->base.size |= cpu_to_le32((FMP_ALGO_MODE_AES_XTS << 28) | in exynos_ufs_fmp_fill_prdt()
1417 prd->file_iv[0] = cpu_to_be64(dun_hi); in exynos_ufs_fmp_fill_prdt()
1418 prd->file_iv[1] = cpu_to_be64(dun_lo); in exynos_ufs_fmp_fill_prdt()
1422 prd->file_enckey[j] = fmp_key_word(enckey, j); in exynos_ufs_fmp_fill_prdt()
1423 prd->file_twkey[j] = fmp_key_word(twkey, j); in exynos_ufs_fmp_fill_prdt()
1450 struct device *dev = hba->dev; in exynos_ufs_init()
1457 return -ENOMEM; in exynos_ufs_init()
1459 /* exynos-specific hci */ in exynos_ufs_init()
1460 ufs->reg_hci = devm_platform_ioremap_resource_byname(pdev, "vs_hci"); in exynos_ufs_init()
1461 if (IS_ERR(ufs->reg_hci)) { in exynos_ufs_init()
1463 return PTR_ERR(ufs->reg_hci); in exynos_ufs_init()
1467 ufs->reg_unipro = devm_platform_ioremap_resource_byname(pdev, "unipro"); in exynos_ufs_init()
1468 if (IS_ERR(ufs->reg_unipro)) { in exynos_ufs_init()
1470 return PTR_ERR(ufs->reg_unipro); in exynos_ufs_init()
1474 ufs->reg_ufsp = devm_platform_ioremap_resource_byname(pdev, "ufsp"); in exynos_ufs_init()
1475 if (IS_ERR(ufs->reg_ufsp)) { in exynos_ufs_init()
1477 return PTR_ERR(ufs->reg_ufsp); in exynos_ufs_init()
1486 ufs->phy = devm_phy_get(dev, "ufs-phy"); in exynos_ufs_init()
1487 if (IS_ERR(ufs->phy)) { in exynos_ufs_init()
1488 ret = PTR_ERR(ufs->phy); in exynos_ufs_init()
1489 dev_err(dev, "failed to get ufs-phy\n"); in exynos_ufs_init()
1497 if (ufs->drv_data->drv_init) { in exynos_ufs_init()
1498 ret = ufs->drv_data->drv_init(ufs); in exynos_ufs_init()
1500 dev_err(dev, "failed to init drv-data\n"); in exynos_ufs_init()
1512 hba->host->dma_alignment = DATA_UNIT_SIZE - 1; in exynos_ufs_init()
1516 hba->priv = NULL; in exynos_ufs_init()
1536 dev_err(hba->dev, "timeout host sw-reset\n"); in exynos_ufs_host_reset()
1537 ret = -ETIMEDOUT; in exynos_ufs_host_reset()
1556 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in exynos_ufs_pre_hibern8()
1559 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) in exynos_ufs_pre_hibern8()
1563 if (ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER) { in exynos_ufs_pre_hibern8()
1567 int h8_time = attr->pa_hibern8time * in exynos_ufs_pre_hibern8()
1568 granularity_tbl[attr->pa_granularity - 1]; in exynos_ufs_pre_hibern8()
1573 delta = h8_time - ktime_us_delta(ktime_get(), in exynos_ufs_pre_hibern8()
1574 ufs->entry_hibern8_t); in exynos_ufs_pre_hibern8()
1591 ufs->entry_hibern8_t = ktime_get(); in exynos_ufs_post_hibern8()
1593 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL) in exynos_ufs_post_hibern8()
1612 hba->host->max_segment_size = DATA_UNIT_SIZE; in exynos_ufs_hce_enable_notify()
1614 if (ufs->drv_data->pre_hce_enable) { in exynos_ufs_hce_enable_notify()
1615 ret = ufs->drv_data->pre_hce_enable(ufs); in exynos_ufs_hce_enable_notify()
1627 if (!(ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)) in exynos_ufs_hce_enable_notify()
1630 if (ufs->drv_data->post_hce_enable) in exynos_ufs_hce_enable_notify()
1631 ret = ufs->drv_data->post_hce_enable(ufs); in exynos_ufs_hce_enable_notify()
1699 phy_power_off(ufs->phy); in exynos_ufs_suspend()
1709 phy_power_on(ufs->phy); in exynos_ufs_resume()
1746 return -ETIME; in exynosauto_ufs_vh_wait_ph_ready()
1751 struct device *dev = hba->dev; in exynosauto_ufs_vh_init()
1758 return -ENOMEM; in exynosauto_ufs_vh_init()
1760 /* exynos-specific hci */ in exynosauto_ufs_vh_init()
1761 ufs->reg_hci = devm_platform_ioremap_resource_byname(pdev, "vs_hci"); in exynosauto_ufs_vh_init()
1762 if (IS_ERR(ufs->reg_hci)) { in exynosauto_ufs_vh_init()
1764 return PTR_ERR(ufs->reg_hci); in exynosauto_ufs_vh_init()
1771 ufs->drv_data = device_get_match_data(dev); in exynosauto_ufs_vh_init()
1772 if (!ufs->drv_data) in exynosauto_ufs_vh_init()
1773 return -ENODEV; in exynosauto_ufs_vh_init()
1782 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr; in fsd_ufs_pre_link()
1783 struct ufs_hba *hba = ufs->hba; in fsd_ufs_pre_link()
1786 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_clk_period_off), in fsd_ufs_pre_link()
1787 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in fsd_ufs_pre_link()
1793 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in fsd_ufs_pre_link()
1799 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in fsd_ufs_pre_link()
1811 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), in fsd_ufs_pre_link()
1823 struct ufs_hba *hba = ufs->hba; in fsd_ufs_post_link()
1861 struct ufs_hba *hba = ufs->hba; in fsd_ufs_pre_pwr_change()
1878 return (16 * 1000 * 1000000UL / ufs->mclk_rate); in get_mclk_period_unipro_18()
1883 struct ufs_hba *hba = ufs->hba; in gs101_ufs_pre_link()
1887 rx_line_reset_period = (RX_LINE_RESET_TIME * ufs->mclk_rate) in gs101_ufs_pre_link()
1889 tx_line_reset_period = (TX_LINE_RESET_TIME * ufs->mclk_rate) in gs101_ufs_pre_link()
1898 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in gs101_ufs_pre_link()
1913 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate)); in gs101_ufs_pre_link()
1939 struct ufs_hba *hba = ufs->hba; in gs101_ufs_post_link()
1957 struct ufs_hba *hba = ufs->hba; in gs101_ufs_pre_pwr_change()
1996 struct device *dev = &pdev->dev; in exynos_ufs_probe()
2001 if (drv_data && drv_data->vops) in exynos_ufs_probe()
2002 vops = drv_data->vops; in exynos_ufs_probe()
2018 phy_power_off(ufs->phy); in exynos_ufs_remove()
2019 phy_exit(ufs->phy); in exynos_ufs_remove()
2168 { .compatible = "google,gs101-ufs",
2170 { .compatible = "samsung,exynos7-ufs",
2172 { .compatible = "samsung,exynosautov9-ufs",
2174 { .compatible = "samsung,exynosautov9-ufs-vh",
2176 { .compatible = "tesla,fsd-ufs",
2193 .name = "exynos-ufshc",