Lines Matching full:hba
226 struct ufs_hba *hba = ufs->hba; in gs101_ufs_drv_init() local
230 hba->caps |= UFSHCD_CAP_WB_EN; in gs101_ufs_drv_init()
233 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; in gs101_ufs_drv_init()
249 struct ufs_hba *hba = ufs->hba; in exynosauto_ufs_post_hce_enable() local
252 ufshcd_rmwl(hba, MHCTRL_EN_VH_MASK, MHCTRL_EN_VH(1), MHCTRL); in exynosauto_ufs_post_hce_enable()
263 struct ufs_hba *hba = ufs->hba; in exynosauto_ufs_pre_link() local
270 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40); in exynosauto_ufs_pre_link()
272 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD, i), in exynosauto_ufs_pre_link()
274 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD_EN, i), 0x0); in exynosauto_ufs_pre_link()
276 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE2, i), in exynosauto_ufs_pre_link()
278 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE1, i), in exynosauto_ufs_pre_link()
280 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE0, i), in exynosauto_ufs_pre_link()
283 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, i), 0x79); in exynosauto_ufs_pre_link()
284 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x84, i), 0x1); in exynosauto_ufs_pre_link()
285 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, i), 0xf6); in exynosauto_ufs_pre_link()
289 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD, i), in exynosauto_ufs_pre_link()
292 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD_EN, i), in exynosauto_ufs_pre_link()
295 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE2, i), in exynosauto_ufs_pre_link()
297 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE1, i), in exynosauto_ufs_pre_link()
299 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE0, i), in exynosauto_ufs_pre_link()
303 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x04, i), 0x1); in exynosauto_ufs_pre_link()
306 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0); in exynosauto_ufs_pre_link()
308 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0); in exynosauto_ufs_pre_link()
310 ufshcd_dme_set(hba, UIC_ARG_MIB(0xa011), 0x8000); in exynosauto_ufs_pre_link()
318 struct ufs_hba *hba = ufs->hba; in exynosauto_ufs_pre_pwr_change() local
321 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000); in exynosauto_ufs_pre_pwr_change()
322 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000); in exynosauto_ufs_pre_pwr_change()
323 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000); in exynosauto_ufs_pre_pwr_change()
331 struct ufs_hba *hba = ufs->hba; in exynosauto_ufs_post_pwr_change() local
334 enabled_vh = ufshcd_readl(hba, MHCTRL) & MHCTRL_EN_VH_MASK; in exynosauto_ufs_post_pwr_change()
337 ufshcd_writel(hba, MH_MSG(enabled_vh, MH_MSG_PH_READY), PH2VH_MBOX); in exynosauto_ufs_post_pwr_change()
346 struct ufs_hba *hba = ufs->hba; in exynos7_ufs_pre_link() local
349 exynos_ufs_enable_ov_tm(hba); in exynos7_ufs_pre_link()
351 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x297, i), 0x17); in exynos7_ufs_pre_link()
353 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x362, i), 0xff); in exynos7_ufs_pre_link()
354 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x363, i), 0x00); in exynos7_ufs_pre_link()
356 exynos_ufs_disable_ov_tm(hba); in exynos7_ufs_pre_link()
359 ufshcd_dme_set(hba, in exynos7_ufs_pre_link()
361 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_TXPHY_CFGUPDT), 0x1); in exynos7_ufs_pre_link()
363 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), in exynos7_ufs_pre_link()
365 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_RESET_PHY), 0x1); in exynos7_ufs_pre_link()
366 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_LINE_RESET), 0x1); in exynos7_ufs_pre_link()
367 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_LINE_RESET_REQ), 0x1); in exynos7_ufs_pre_link()
369 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), val); in exynos7_ufs_pre_link()
376 struct ufs_hba *hba = ufs->hba; in exynos7_ufs_post_link() local
379 exynos_ufs_enable_ov_tm(hba); in exynos7_ufs_post_link()
381 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x28b, i), 0x83); in exynos7_ufs_post_link()
382 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x29a, i), 0x07); in exynos7_ufs_post_link()
383 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x277, i), in exynos7_ufs_post_link()
386 exynos_ufs_disable_ov_tm(hba); in exynos7_ufs_post_link()
388 exynos_ufs_enable_dbg_mode(hba); in exynos7_ufs_post_link()
389 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0xbb8); in exynos7_ufs_post_link()
390 exynos_ufs_disable_dbg_mode(hba); in exynos7_ufs_post_link()
406 struct ufs_hba *hba = ufs->hba; in exynos7_ufs_post_pwr_change() local
409 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_RXPHY_CFGUPDT), 0x1); in exynos7_ufs_post_pwr_change()
412 exynos_ufs_enable_dbg_mode(hba); in exynos7_ufs_post_pwr_change()
413 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 0x1); in exynos7_ufs_post_pwr_change()
414 exynos_ufs_disable_dbg_mode(hba); in exynos7_ufs_post_pwr_change()
452 struct ufs_hba *hba = ufs->hba; in exynos_ufs_get_clk_info() local
453 struct list_head *head = &hba->clk_list_head; in exynos_ufs_get_clk_info()
473 dev_err(hba->dev, "failed to get clk info\n"); in exynos_ufs_get_clk_info()
494 dev_err(hba->dev, "not available pclk range %lu\n", pclk_rate); in exynos_ufs_get_clk_info()
519 struct ufs_hba *hba = ufs->hba; in exynos_ufs_set_pwm_clk_div() local
522 ufshcd_dme_set(hba, in exynos_ufs_set_pwm_clk_div()
528 struct ufs_hba *hba = ufs->hba; in exynos_ufs_calc_pwm_clk_div() local
549 ufshcd_dme_get(hba, UIC_ARG_MIB(CMN_PWM_CLK_CTRL), &clk_idx); in exynos_ufs_calc_pwm_clk_div()
550 dev_err(hba->dev, in exynos_ufs_calc_pwm_clk_div()
606 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_phy_time_attr() local
612 exynos_ufs_enable_ov_tm(hba); in exynos_ufs_config_phy_time_attr()
615 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_FILLER_ENABLE, i), in exynos_ufs_config_phy_time_attr()
617 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_LINERESET_VAL, i), in exynos_ufs_config_phy_time_attr()
619 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_BASE_NVAL_07_00, i), in exynos_ufs_config_phy_time_attr()
621 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_BASE_NVAL_15_08, i), in exynos_ufs_config_phy_time_attr()
623 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_GRAN_NVAL_07_00, i), in exynos_ufs_config_phy_time_attr()
625 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_GRAN_NVAL_10_08, i), in exynos_ufs_config_phy_time_attr()
627 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_OV_SLEEP_CNT_TIMER, i), in exynos_ufs_config_phy_time_attr()
629 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_OV_STALL_CNT_TIMER, i), in exynos_ufs_config_phy_time_attr()
634 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_LINERESET_P_VAL, i), in exynos_ufs_config_phy_time_attr()
636 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HIGH_Z_CNT_07_00, i), in exynos_ufs_config_phy_time_attr()
638 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HIGH_Z_CNT_11_08, i), in exynos_ufs_config_phy_time_attr()
640 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_BASE_NVAL_07_00, i), in exynos_ufs_config_phy_time_attr()
642 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_BASE_NVAL_15_08, i), in exynos_ufs_config_phy_time_attr()
644 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_GRAN_NVAL_07_00, i), in exynos_ufs_config_phy_time_attr()
646 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_GRAN_NVAL_10_08, i), in exynos_ufs_config_phy_time_attr()
648 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_OV_SLEEP_CNT_TIMER, i), in exynos_ufs_config_phy_time_attr()
651 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_MIN_ACTIVATETIME, i), in exynos_ufs_config_phy_time_attr()
655 exynos_ufs_disable_ov_tm(hba); in exynos_ufs_config_phy_time_attr()
660 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_phy_cap_attr() local
664 exynos_ufs_enable_ov_tm(hba); in exynos_ufs_config_phy_cap_attr()
667 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
670 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
673 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
676 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
679 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
682 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
689 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
693 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
699 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
706 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
712 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
718 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
725 exynos_ufs_disable_ov_tm(hba); in exynos_ufs_config_phy_cap_attr()
730 struct ufs_hba *hba = ufs->hba; in exynos_ufs_establish_connt() local
739 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_IDLE); in exynos_ufs_establish_connt()
742 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID), DEV_ID); in exynos_ufs_establish_connt()
743 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID_VALID), true); in exynos_ufs_establish_connt()
744 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERDEVICEID), PEER_DEV_ID); in exynos_ufs_establish_connt()
745 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERCPORTID), PEER_CPORT_ID); in exynos_ufs_establish_connt()
746 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CPORTFLAGS), CPORT_DEF_FLAGS); in exynos_ufs_establish_connt()
747 ufshcd_dme_set(hba, UIC_ARG_MIB(T_TRAFFICCLASS), TRAFFIC_CLASS); in exynos_ufs_establish_connt()
748 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_CONNECTED); in exynos_ufs_establish_connt()
774 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_sync_pattern_mask() local
796 exynos_ufs_enable_ov_tm(hba); in exynos_ufs_config_sync_pattern_mask()
799 ufshcd_dme_set(hba, in exynos_ufs_config_sync_pattern_mask()
802 exynos_ufs_disable_ov_tm(hba); in exynos_ufs_config_sync_pattern_mask()
807 static u32 exynos_ufs_get_hs_gear(struct ufs_hba *hba) in exynos_ufs_get_hs_gear() argument
811 major = FIELD_GET(UFS_HW_VER_MAJOR_MASK, hba->ufs_version); in exynos_ufs_get_hs_gear()
820 static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba, in exynos_ufs_pre_pwr_mode() argument
824 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_pre_pwr_mode()
838 host_params.hs_tx_gear = exynos_ufs_get_hs_gear(hba); in exynos_ufs_pre_pwr_mode()
839 host_params.hs_rx_gear = exynos_ufs_get_hs_gear(hba); in exynos_ufs_pre_pwr_mode()
862 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_FC0PROTTIMEOUTVAL), 8064); in exynos_ufs_pre_pwr_mode()
863 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_TC0REPLAYTIMEOUTVAL), 28224); in exynos_ufs_pre_pwr_mode()
864 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_AFC0REQTIMEOUTVAL), 20160); in exynos_ufs_pre_pwr_mode()
872 static int exynos_ufs_post_pwr_mode(struct ufs_hba *hba, in exynos_ufs_post_pwr_mode() argument
875 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_post_pwr_mode()
907 dev_info(hba->dev, "Power mode changed to : %s\n", pwr_str); in exynos_ufs_post_pwr_mode()
912 static void exynos_ufs_specify_nexus_t_xfer_req(struct ufs_hba *hba, in exynos_ufs_specify_nexus_t_xfer_req() argument
915 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_specify_nexus_t_xfer_req()
926 static void exynos_ufs_specify_nexus_t_tm_req(struct ufs_hba *hba, in exynos_ufs_specify_nexus_t_tm_req() argument
929 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_specify_nexus_t_tm_req()
950 struct ufs_hba *hba = ufs->hba; in exynos_ufs_phy_init() local
955 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILRXDATALANES), in exynos_ufs_phy_init()
957 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILTXDATALANES), in exynos_ufs_phy_init()
973 dev_err(hba->dev, "%s: phy init failed, ret = %d\n", in exynos_ufs_phy_init()
993 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_unipro() local
996 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_clk_period_off), in exynos_ufs_config_unipro()
999 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTRAILINGCLOCKS), in exynos_ufs_config_unipro()
1003 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), in exynos_ufs_config_unipro()
1007 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite2_off), in exynos_ufs_config_unipro()
1032 static int exynos_ufs_setup_clocks(struct ufs_hba *hba, bool on, in exynos_ufs_setup_clocks() argument
1035 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_setup_clocks()
1053 static int exynos_ufs_pre_link(struct ufs_hba *hba) in exynos_ufs_pre_link() argument
1055 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_pre_link()
1073 exynos_ufs_setup_clocks(hba, true, PRE_CHANGE); in exynos_ufs_pre_link()
1096 static int exynos_ufs_post_link(struct ufs_hba *hba) in exynos_ufs_post_link() argument
1098 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_post_link()
1108 hci_writel(ufs, (1 << hba->nutrs) - 1, HCI_UTRL_NEXUS_TYPE); in exynos_ufs_post_link()
1109 hci_writel(ufs, (1 << hba->nutmrs) - 1, HCI_UTMRL_NEXUS_TYPE); in exynos_ufs_post_link()
1113 ufshcd_dme_set(hba, in exynos_ufs_post_link()
1117 exynos_ufs_enable_dbg_mode(hba); in exynos_ufs_post_link()
1118 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_GRANULARITY), in exynos_ufs_post_link()
1120 exynos_ufs_disable_dbg_mode(hba); in exynos_ufs_post_link()
1123 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), in exynos_ufs_post_link()
1127 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), in exynos_ufs_post_link()
1133 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY), in exynos_ufs_post_link()
1136 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_HIBERN8TIME), in exynos_ufs_post_link()
1141 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 0); in exynos_ufs_post_link()
1145 dev_warn(hba->dev, in exynos_ufs_post_link()
1212 static inline void exynos_ufs_priv_init(struct ufs_hba *hba, in exynos_ufs_priv_init() argument
1215 ufs->hba = hba; in exynos_ufs_priv_init()
1220 hba->priv = (void *)ufs; in exynos_ufs_priv_init()
1221 hba->quirks = ufs->drv_data->quirks; in exynos_ufs_priv_init()
1278 static void exynos_ufs_fmp_init(struct ufs_hba *hba, struct exynos_ufs *ufs) in exynos_ufs_fmp_init() argument
1280 struct blk_crypto_profile *profile = &hba->crypto_profile; in exynos_ufs_fmp_init()
1291 if (!(ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES) & in exynos_ufs_fmp_init()
1316 dev_warn(hba->dev, in exynos_ufs_fmp_init()
1321 ufshcd_set_sg_entry_size(hba, sizeof(struct fmp_sg_entry)); in exynos_ufs_fmp_init()
1329 dev_err(hba->dev, in exynos_ufs_fmp_init()
1336 err = devm_blk_crypto_profile_init(hba->dev, profile, 0); in exynos_ufs_fmp_init()
1339 dev_err(hba->dev, "Failed to initialize crypto profile: %d\n", in exynos_ufs_fmp_init()
1344 profile->dev = hba->dev; in exynos_ufs_fmp_init()
1349 hba->caps |= UFSHCD_CAP_CRYPTO; in exynos_ufs_fmp_init()
1352 hba->quirks |= UFSHCD_QUIRK_CUSTOM_CRYPTO_PROFILE | in exynos_ufs_fmp_init()
1358 static void exynos_ufs_fmp_resume(struct ufs_hba *hba) in exynos_ufs_fmp_resume() argument
1362 if (!(hba->caps & UFSHCD_CAP_CRYPTO)) in exynos_ufs_fmp_resume()
1368 dev_err(hba->dev, in exynos_ufs_fmp_resume()
1374 dev_err(hba->dev, in exynos_ufs_fmp_resume()
1385 static int exynos_ufs_fmp_fill_prdt(struct ufs_hba *hba, in exynos_ufs_fmp_fill_prdt() argument
1397 if (WARN_ON_ONCE(!(hba->caps & UFSHCD_CAP_CRYPTO))) in exynos_ufs_fmp_fill_prdt()
1407 dev_err(hba->dev, in exynos_ufs_fmp_fill_prdt()
1436 static void exynos_ufs_fmp_init(struct ufs_hba *hba, struct exynos_ufs *ufs) in exynos_ufs_fmp_init() argument
1440 static void exynos_ufs_fmp_resume(struct ufs_hba *hba) in exynos_ufs_fmp_resume() argument
1448 static int exynos_ufs_init(struct ufs_hba *hba) in exynos_ufs_init() argument
1450 struct device *dev = hba->dev; in exynos_ufs_init()
1493 exynos_ufs_priv_init(hba, ufs); in exynos_ufs_init()
1495 exynos_ufs_fmp_init(hba, ufs); in exynos_ufs_init()
1512 hba->host->dma_alignment = DATA_UNIT_SIZE - 1; in exynos_ufs_init()
1516 hba->priv = NULL; in exynos_ufs_init()
1520 static int exynos_ufs_host_reset(struct ufs_hba *hba) in exynos_ufs_host_reset() argument
1522 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_host_reset()
1536 dev_err(hba->dev, "timeout host sw-reset\n"); in exynos_ufs_host_reset()
1544 static void exynos_ufs_dev_hw_reset(struct ufs_hba *hba) in exynos_ufs_dev_hw_reset() argument
1546 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_dev_hw_reset()
1553 static void exynos_ufs_pre_hibern8(struct ufs_hba *hba, enum uic_cmd_dme cmd) in exynos_ufs_pre_hibern8() argument
1555 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_pre_hibern8()
1586 static void exynos_ufs_post_hibern8(struct ufs_hba *hba, enum uic_cmd_dme cmd) in exynos_ufs_post_hibern8() argument
1588 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_post_hibern8()
1598 static int exynos_ufs_hce_enable_notify(struct ufs_hba *hba, in exynos_ufs_hce_enable_notify() argument
1601 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_hce_enable_notify()
1612 hba->host->max_segment_size = DATA_UNIT_SIZE; in exynos_ufs_hce_enable_notify()
1620 ret = exynos_ufs_host_reset(hba); in exynos_ufs_hce_enable_notify()
1623 exynos_ufs_dev_hw_reset(hba); in exynos_ufs_hce_enable_notify()
1639 static int exynos_ufs_link_startup_notify(struct ufs_hba *hba, in exynos_ufs_link_startup_notify() argument
1646 ret = exynos_ufs_pre_link(hba); in exynos_ufs_link_startup_notify()
1649 ret = exynos_ufs_post_link(hba); in exynos_ufs_link_startup_notify()
1656 static int exynos_ufs_pwr_change_notify(struct ufs_hba *hba, in exynos_ufs_pwr_change_notify() argument
1665 ret = exynos_ufs_pre_pwr_mode(hba, dev_max_params, in exynos_ufs_pwr_change_notify()
1669 ret = exynos_ufs_post_pwr_mode(hba, dev_req_params); in exynos_ufs_pwr_change_notify()
1676 static void exynos_ufs_hibern8_notify(struct ufs_hba *hba, in exynos_ufs_hibern8_notify() argument
1682 exynos_ufs_pre_hibern8(hba, cmd); in exynos_ufs_hibern8_notify()
1685 exynos_ufs_post_hibern8(hba, cmd); in exynos_ufs_hibern8_notify()
1690 static int exynos_ufs_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, in exynos_ufs_suspend() argument
1693 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_suspend()
1698 if (!ufshcd_is_link_active(hba)) in exynos_ufs_suspend()
1704 static int exynos_ufs_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) in exynos_ufs_resume() argument
1706 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_resume()
1708 if (!ufshcd_is_link_active(hba)) in exynos_ufs_resume()
1712 exynos_ufs_fmp_resume(hba); in exynos_ufs_resume()
1716 static int exynosauto_ufs_vh_link_startup_notify(struct ufs_hba *hba, in exynosauto_ufs_vh_link_startup_notify() argument
1720 ufshcd_set_link_active(hba); in exynosauto_ufs_vh_link_startup_notify()
1721 ufshcd_set_ufs_dev_active(hba); in exynosauto_ufs_vh_link_startup_notify()
1727 static int exynosauto_ufs_vh_wait_ph_ready(struct ufs_hba *hba) in exynosauto_ufs_vh_wait_ph_ready() argument
1736 mbox = ufshcd_readl(hba, PH2VH_MBOX); in exynosauto_ufs_vh_wait_ph_ready()
1749 static int exynosauto_ufs_vh_init(struct ufs_hba *hba) in exynosauto_ufs_vh_init() argument
1751 struct device *dev = hba->dev; in exynosauto_ufs_vh_init()
1767 ret = exynosauto_ufs_vh_wait_ph_ready(hba); in exynosauto_ufs_vh_init()
1775 exynos_ufs_priv_init(hba, ufs); in exynosauto_ufs_vh_init()
1783 struct ufs_hba *hba = ufs->hba; in fsd_ufs_pre_link() local
1786 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_clk_period_off), in fsd_ufs_pre_link()
1788 ufshcd_dme_set(hba, UIC_ARG_MIB(0x201), 0x12); in fsd_ufs_pre_link()
1789 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40); in fsd_ufs_pre_link()
1792 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xAA, i), in fsd_ufs_pre_link()
1794 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8F, i), 0x3F); in fsd_ufs_pre_link()
1798 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x12, i), in fsd_ufs_pre_link()
1800 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x5C, i), 0x38); in fsd_ufs_pre_link()
1801 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0F, i), 0x0); in fsd_ufs_pre_link()
1802 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x65, i), 0x1); in fsd_ufs_pre_link()
1803 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x69, i), 0x1); in fsd_ufs_pre_link()
1804 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x21, i), 0x0); in fsd_ufs_pre_link()
1805 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x22, i), 0x0); in fsd_ufs_pre_link()
1808 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0); in fsd_ufs_pre_link()
1809 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_AUTOMODE_THLD), 0x4E20); in fsd_ufs_pre_link()
1811 ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), in fsd_ufs_pre_link()
1813 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0); in fsd_ufs_pre_link()
1823 struct ufs_hba *hba = ufs->hba; in fsd_ufs_post_link() local
1828 ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0x8F, 4), in fsd_ufs_post_link()
1830 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), in fsd_ufs_post_link()
1832 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_HIBERN8TIME), in fsd_ufs_post_link()
1836 ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE), in fsd_ufs_post_link()
1838 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), max_rx_hibern8_time_cap + 1); in fsd_ufs_post_link()
1840 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), 0x01); in fsd_ufs_post_link()
1841 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0xFA); in fsd_ufs_post_link()
1842 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), 0x00); in fsd_ufs_post_link()
1844 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40); in fsd_ufs_post_link()
1847 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x35, i), 0x05); in fsd_ufs_post_link()
1848 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x73, i), 0x01); in fsd_ufs_post_link()
1849 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x41, i), 0x02); in fsd_ufs_post_link()
1850 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x42, i), 0xAC); in fsd_ufs_post_link()
1853 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0); in fsd_ufs_post_link()
1861 struct ufs_hba *hba = ufs->hba; in fsd_ufs_pre_pwr_change() local
1863 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), 0x1); in fsd_ufs_pre_pwr_change()
1864 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), 0x1); in fsd_ufs_pre_pwr_change()
1865 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000); in fsd_ufs_pre_pwr_change()
1866 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000); in fsd_ufs_pre_pwr_change()
1867 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000); in fsd_ufs_pre_pwr_change()
1883 struct ufs_hba *hba = ufs->hba; in gs101_ufs_pre_link() local
1894 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40); in gs101_ufs_pre_link()
1897 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD, i), in gs101_ufs_pre_link()
1899 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD_EN, i), 0x0); in gs101_ufs_pre_link()
1900 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE2, i), in gs101_ufs_pre_link()
1902 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE1, i), in gs101_ufs_pre_link()
1904 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE0, i), in gs101_ufs_pre_link()
1906 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, i), 0x69); in gs101_ufs_pre_link()
1907 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x84, i), 0x1); in gs101_ufs_pre_link()
1908 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, i), 0xf6); in gs101_ufs_pre_link()
1912 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD, i), in gs101_ufs_pre_link()
1914 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD_EN, i), in gs101_ufs_pre_link()
1916 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE2, i), in gs101_ufs_pre_link()
1918 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE1, i), in gs101_ufs_pre_link()
1920 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE0, i), in gs101_ufs_pre_link()
1922 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x04, i), 1); in gs101_ufs_pre_link()
1923 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x7F, i), 0); in gs101_ufs_pre_link()
1926 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0); in gs101_ufs_pre_link()
1927 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0); in gs101_ufs_pre_link()
1928 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID), 0x0); in gs101_ufs_pre_link()
1929 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID_VALID), 0x1); in gs101_ufs_pre_link()
1930 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERDEVICEID), 0x1); in gs101_ufs_pre_link()
1931 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_CONNECTED); in gs101_ufs_pre_link()
1932 ufshcd_dme_set(hba, UIC_ARG_MIB(0xA006), 0x8000); in gs101_ufs_pre_link()
1939 struct ufs_hba *hba = ufs->hba; in gs101_ufs_post_link() local
1947 exynos_ufs_enable_dbg_mode(hba); in gs101_ufs_post_link()
1948 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0x3e8); in gs101_ufs_post_link()
1949 exynos_ufs_disable_dbg_mode(hba); in gs101_ufs_post_link()
1957 struct ufs_hba *hba = ufs->hba; in gs101_ufs_pre_pwr_change() local
1959 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000); in gs101_ufs_pre_pwr_change()
1960 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000); in gs101_ufs_pre_pwr_change()
1961 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000); in gs101_ufs_pre_pwr_change()
2013 struct ufs_hba *hba = platform_get_drvdata(pdev); in exynos_ufs_remove() local
2014 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_remove()