Lines Matching +full:qe +full:- +full:firmware
1 // SPDX-License-Identifier: GPL-2.0
12 * If Soft-UART support is needed but not already present, then this driver
13 * will request and upload the "Soft-UART" microcode upon probe. The
30 #include <linux/dma-mapping.h>
32 #include <soc/fsl/qe/ucc_slow.h>
34 #include <linux/firmware.h>
42 * The GUMR flag for Soft UART. This would normally be defined in qe.h,
43 * but Soft-UART is a hack and we want to keep everything related to it in
46 #define UCC_SLOW_GUMR_H_SUART 0x00004000 /* Soft-UART */
49 * soft_uart is 1 if we need to use Soft-UART mode
53 * firmware_loaded is 1 if the firmware has been loaded, 0 otherwise.
62 * Documentation/admin-guide/devices.txt. For the QE
63 * UART, we have major number 204 and minor numbers 46 - 49, which are the
65 * has both a CPM and a QE.
70 /* Since we only have minor numbers 46 - 49, there is a hard limit of 4 ports */
106 __be16 cchars[8]; /* control characters 1-8 */
122 /* The rest is for Soft-UART only */
130 u8 res14[0xBC - 0x9F]; /* reserved */
136 u8 res15[0xD0 - 0xC8]; /* reserved */
142 /* SUPSMR definitions, for Soft-UART only */
176 /* Private per-port data structure */
220 if (likely((addr >= qe_port->bd_virt)) && in cpu2qe_addr()
221 (addr < (qe_port->bd_virt + qe_port->bd_size))) in cpu2qe_addr()
222 return qe_port->bd_dma_addr + (addr - qe_port->bd_virt); in cpu2qe_addr()
239 if (likely((addr >= qe_port->bd_dma_addr) && in qe2cpu_addr()
240 (addr < (qe_port->bd_dma_addr + qe_port->bd_size)))) in qe2cpu_addr()
241 return qe_port->bd_virt + (addr - qe_port->bd_dma_addr); in qe2cpu_addr()
250 * Return 1 if the QE is done transmitting all buffers for this port
253 * ready (READY=1), then we return 0 indicating that the QE is still sending
261 struct qe_bd __iomem *bdp = qe_port->tx_bd_base; in qe_uart_tx_empty()
264 if (ioread16be(&bdp->status) & BD_SC_READY) in qe_uart_tx_empty()
268 if (ioread16be(&bdp->status) & BD_SC_WRAP) in qe_uart_tx_empty()
282 * Although the QE can control the modem control lines (e.g. CTS), we
293 * Although the QE can control the modem control lines (e.g. CTS), this
306 * transmission of data. Instead, it tells the QE to not generate an
314 qe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX); in qe_uart_stop_tx()
323 * A return value of non-zero indicates that it successfully stuffed all
336 struct uart_port *port = &qe_port->port; in qe_uart_tx_pump()
337 struct tty_port *tport = &port->state->port; in qe_uart_tx_pump()
340 if (port->x_char) { in qe_uart_tx_pump()
342 bdp = qe_port->tx_cur; in qe_uart_tx_pump()
344 p = qe2cpu_addr(ioread32be(&bdp->buf), qe_port); in qe_uart_tx_pump()
346 *p++ = port->x_char; in qe_uart_tx_pump()
347 iowrite16be(1, &bdp->length); in qe_uart_tx_pump()
348 qe_setbits_be16(&bdp->status, BD_SC_READY); in qe_uart_tx_pump()
350 if (ioread16be(&bdp->status) & BD_SC_WRAP) in qe_uart_tx_pump()
351 bdp = qe_port->tx_bd_base; in qe_uart_tx_pump()
354 qe_port->tx_cur = bdp; in qe_uart_tx_pump()
356 port->icount.tx++; in qe_uart_tx_pump()
357 port->x_char = 0; in qe_uart_tx_pump()
361 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)) { in qe_uart_tx_pump()
367 bdp = qe_port->tx_cur; in qe_uart_tx_pump()
369 while (!(ioread16be(&bdp->status) & BD_SC_READY) && in qe_uart_tx_pump()
370 !kfifo_is_empty(&tport->xmit_fifo)) { in qe_uart_tx_pump()
371 p = qe2cpu_addr(ioread32be(&bdp->buf), qe_port); in qe_uart_tx_pump()
372 count = uart_fifo_out(port, p, qe_port->tx_fifosize); in qe_uart_tx_pump()
374 iowrite16be(count, &bdp->length); in qe_uart_tx_pump()
375 qe_setbits_be16(&bdp->status, BD_SC_READY); in qe_uart_tx_pump()
378 if (ioread16be(&bdp->status) & BD_SC_WRAP) in qe_uart_tx_pump()
379 bdp = qe_port->tx_bd_base; in qe_uart_tx_pump()
383 qe_port->tx_cur = bdp; in qe_uart_tx_pump()
385 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in qe_uart_tx_pump()
388 if (kfifo_is_empty(&tport->xmit_fifo)) { in qe_uart_tx_pump()
390 don't need to be told when the QE is finished transmitting in qe_uart_tx_pump()
411 if (ioread16be(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX) in qe_uart_start_tx()
416 qe_setbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX); in qe_uart_start_tx()
427 qe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX); in qe_uart_stop_rx()
442 ucc_slow_stop_tx(qe_port->us_private); in qe_uart_break_ctl()
444 ucc_slow_restart_tx(qe_port->us_private); in qe_uart_break_ctl()
455 struct uart_port *port = &qe_port->port; in qe_uart_int_rx()
456 struct tty_port *tport = &port->state->port; in qe_uart_int_rx()
464 bdp = qe_port->rx_cur; in qe_uart_int_rx()
466 status = ioread16be(&bdp->status); in qe_uart_int_rx()
473 i = ioread16be(&bdp->length); in qe_uart_int_rx()
479 dev_dbg(port->dev, "ucc-uart: no room in RX buffer\n"); in qe_uart_int_rx()
484 cp = qe2cpu_addr(ioread32be(&bdp->buf), qe_port); in qe_uart_int_rx()
487 while (i-- > 0) { in qe_uart_int_rx()
489 port->icount.rx++; in qe_uart_int_rx()
504 qe_clrsetbits_be16(&bdp->status, in qe_uart_int_rx()
507 if (ioread16be(&bdp->status) & BD_SC_WRAP) in qe_uart_int_rx()
508 bdp = qe_port->rx_bd_base; in qe_uart_int_rx()
515 qe_port->rx_cur = bdp; in qe_uart_int_rx()
527 port->icount.brk++; in qe_uart_int_rx()
529 port->icount.parity++; in qe_uart_int_rx()
531 port->icount.frame++; in qe_uart_int_rx()
533 port->icount.overrun++; in qe_uart_int_rx()
536 status &= port->read_status_mask; in qe_uart_int_rx()
549 port->sysrq = 0; in qe_uart_int_rx()
560 struct ucc_slow __iomem *uccp = qe_port->uccp; in qe_uart_int()
564 events = ioread16be(&uccp->ucce); in qe_uart_int()
565 iowrite16be(events, &uccp->ucce); in qe_uart_int()
568 uart_handle_break(&qe_port->port); in qe_uart_int()
592 bd_virt = qe_port->bd_virt; in qe_uart_initbd()
593 bdp = qe_port->rx_bd_base; in qe_uart_initbd()
594 qe_port->rx_cur = qe_port->rx_bd_base; in qe_uart_initbd()
595 for (i = 0; i < (qe_port->rx_nrfifos - 1); i++) { in qe_uart_initbd()
596 iowrite16be(BD_SC_EMPTY | BD_SC_INTRPT, &bdp->status); in qe_uart_initbd()
597 iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf); in qe_uart_initbd()
598 iowrite16be(0, &bdp->length); in qe_uart_initbd()
599 bd_virt += qe_port->rx_fifosize; in qe_uart_initbd()
604 iowrite16be(BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT, &bdp->status); in qe_uart_initbd()
605 iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf); in qe_uart_initbd()
606 iowrite16be(0, &bdp->length); in qe_uart_initbd()
612 bd_virt = qe_port->bd_virt + in qe_uart_initbd()
613 L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize); in qe_uart_initbd()
614 qe_port->tx_cur = qe_port->tx_bd_base; in qe_uart_initbd()
615 bdp = qe_port->tx_bd_base; in qe_uart_initbd()
616 for (i = 0; i < (qe_port->tx_nrfifos - 1); i++) { in qe_uart_initbd()
617 iowrite16be(BD_SC_INTRPT, &bdp->status); in qe_uart_initbd()
618 iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf); in qe_uart_initbd()
619 iowrite16be(0, &bdp->length); in qe_uart_initbd()
620 bd_virt += qe_port->tx_fifosize; in qe_uart_initbd()
626 qe_setbits_be16(&qe_port->tx_cur->status, BD_SC_P); in qe_uart_initbd()
629 iowrite16be(BD_SC_WRAP | BD_SC_INTRPT, &bdp->status); in qe_uart_initbd()
630 iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf); in qe_uart_initbd()
631 iowrite16be(0, &bdp->length); in qe_uart_initbd()
639 * does all the UART-specific stuff.
644 struct ucc_slow __iomem *uccp = qe_port->uccp; in qe_uart_init_ucc()
645 struct ucc_uart_pram __iomem *uccup = qe_port->uccup; in qe_uart_init_ucc()
650 ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX); in qe_uart_init_ucc()
653 iowrite8(UCC_BMR_GBL | UCC_BMR_BO_BE, &uccup->common.rbmr); in qe_uart_init_ucc()
654 iowrite8(UCC_BMR_GBL | UCC_BMR_BO_BE, &uccup->common.tbmr); in qe_uart_init_ucc()
655 iowrite16be(qe_port->rx_fifosize, &uccup->common.mrblr); in qe_uart_init_ucc()
656 iowrite16be(0x10, &uccup->maxidl); in qe_uart_init_ucc()
657 iowrite16be(1, &uccup->brkcr); in qe_uart_init_ucc()
658 iowrite16be(0, &uccup->parec); in qe_uart_init_ucc()
659 iowrite16be(0, &uccup->frmec); in qe_uart_init_ucc()
660 iowrite16be(0, &uccup->nosec); in qe_uart_init_ucc()
661 iowrite16be(0, &uccup->brkec); in qe_uart_init_ucc()
662 iowrite16be(0, &uccup->uaddr[0]); in qe_uart_init_ucc()
663 iowrite16be(0, &uccup->uaddr[1]); in qe_uart_init_ucc()
664 iowrite16be(0, &uccup->toseq); in qe_uart_init_ucc()
666 iowrite16be(0xC000, &uccup->cchars[i]); in qe_uart_init_ucc()
667 iowrite16be(0xc0ff, &uccup->rccm); in qe_uart_init_ucc()
671 /* Soft-UART requires a 1X multiplier for TX */ in qe_uart_init_ucc()
672 qe_clrsetbits_be32(&uccp->gumr_l, in qe_uart_init_ucc()
676 qe_clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW, in qe_uart_init_ucc()
679 qe_clrsetbits_be32(&uccp->gumr_l, in qe_uart_init_ucc()
683 qe_clrsetbits_be32(&uccp->gumr_h, in qe_uart_init_ucc()
689 qe_clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK, in qe_uart_init_ucc()
691 qe_clrsetbits_be32(&uccp->gumr_h, in qe_uart_init_ucc()
697 iowrite16be(0, &uccp->uccm); in qe_uart_init_ucc()
698 iowrite16be(0xffff, &uccp->ucce); in qe_uart_init_ucc()
699 iowrite16be(0x7e7e, &uccp->udsr); in qe_uart_init_ucc()
702 iowrite16be(0, &uccp->upsmr); in qe_uart_init_ucc()
705 iowrite16be(0x30, &uccup->supsmr); in qe_uart_init_ucc()
706 iowrite16be(0, &uccup->res92); in qe_uart_init_ucc()
707 iowrite32be(0, &uccup->rx_state); in qe_uart_init_ucc()
708 iowrite32be(0, &uccup->rx_cnt); in qe_uart_init_ucc()
709 iowrite8(0, &uccup->rx_bitmark); in qe_uart_init_ucc()
710 iowrite8(10, &uccup->rx_length); in qe_uart_init_ucc()
711 iowrite32be(0x4000, &uccup->dump_ptr); in qe_uart_init_ucc()
712 iowrite8(0, &uccup->rx_temp_dlst_qe); in qe_uart_init_ucc()
713 iowrite32be(0, &uccup->rx_frame_rem); in qe_uart_init_ucc()
714 iowrite8(0, &uccup->rx_frame_rem_size); in qe_uart_init_ucc()
715 /* Soft-UART requires TX to be 1X */ in qe_uart_init_ucc()
717 &uccup->tx_mode); in qe_uart_init_ucc()
718 iowrite16be(0, &uccup->tx_state); in qe_uart_init_ucc()
719 iowrite8(0, &uccup->resD4); in qe_uart_init_ucc()
720 iowrite16be(0, &uccup->resD5); in qe_uart_init_ucc()
734 qe_clrsetbits_be32(&uccp->gumr_l, in qe_uart_init_ucc()
738 qe_clrsetbits_be32(&uccp->gumr_h, in qe_uart_init_ucc()
743 qe_clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK, in qe_uart_init_ucc()
745 qe_clrbits_be32(&uccp->gumr_h, in qe_uart_init_ucc()
749 cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num); in qe_uart_init_ucc()
753 cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num); in qe_uart_init_ucc()
769 * If we're using Soft-UART mode, then we need to make sure the in qe_uart_startup()
770 * firmware has been uploaded first. in qe_uart_startup()
773 dev_err(port->dev, "Soft-UART firmware not uploaded\n"); in qe_uart_startup()
774 return -ENODEV; in qe_uart_startup()
781 ret = request_irq(port->irq, qe_uart_int, IRQF_SHARED, "ucc-uart", in qe_uart_startup()
784 dev_err(port->dev, "could not claim IRQ %u\n", port->irq); in qe_uart_startup()
788 /* Startup rx-int */ in qe_uart_startup()
789 qe_setbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX); in qe_uart_startup()
790 ucc_slow_enable(qe_port->us_private, COMM_DIR_RX_AND_TX); in qe_uart_startup()
802 struct ucc_slow __iomem *uccp = qe_port->uccp; in qe_uart_shutdown()
809 if (!--timeout) { in qe_uart_shutdown()
810 dev_warn(port->dev, "shutdown timeout\n"); in qe_uart_shutdown()
817 if (qe_port->wait_closing) { in qe_uart_shutdown()
820 schedule_timeout(qe_port->wait_closing); in qe_uart_shutdown()
824 ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX); in qe_uart_shutdown()
825 qe_clrbits_be16(&uccp->uccm, UCC_UART_UCCE_TX | UCC_UART_UCCE_RX); in qe_uart_shutdown()
828 ucc_slow_graceful_stop_tx(qe_port->us_private); in qe_uart_shutdown()
831 free_irq(port->irq, qe_port); in qe_uart_shutdown()
843 struct ucc_slow __iomem *uccp = qe_port->uccp; in qe_uart_set_termios()
846 u16 upsmr = ioread16be(&uccp->upsmr); in qe_uart_set_termios()
847 struct ucc_uart_pram __iomem *uccup = qe_port->uccup; in qe_uart_set_termios()
848 u16 supsmr = ioread16be(&uccup->supsmr); in qe_uart_set_termios()
854 switch (termios->c_cflag & CSIZE) { in qe_uart_set_termios()
874 if (termios->c_cflag & CSTOPB) { in qe_uart_set_termios()
879 if (termios->c_cflag & PARENB) { in qe_uart_set_termios()
883 if (!(termios->c_cflag & PARODD)) { in qe_uart_set_termios()
898 port->read_status_mask = BD_SC_EMPTY | BD_SC_OV; in qe_uart_set_termios()
899 if (termios->c_iflag & INPCK) in qe_uart_set_termios()
900 port->read_status_mask |= BD_SC_FR | BD_SC_PR; in qe_uart_set_termios()
901 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in qe_uart_set_termios()
902 port->read_status_mask |= BD_SC_BR; in qe_uart_set_termios()
907 port->ignore_status_mask = 0; in qe_uart_set_termios()
908 if (termios->c_iflag & IGNPAR) in qe_uart_set_termios()
909 port->ignore_status_mask |= BD_SC_PR | BD_SC_FR; in qe_uart_set_termios()
910 if (termios->c_iflag & IGNBRK) { in qe_uart_set_termios()
911 port->ignore_status_mask |= BD_SC_BR; in qe_uart_set_termios()
916 if (termios->c_iflag & IGNPAR) in qe_uart_set_termios()
917 port->ignore_status_mask |= BD_SC_OV; in qe_uart_set_termios()
922 if ((termios->c_cflag & CREAD) == 0) in qe_uart_set_termios()
923 port->read_status_mask &= ~BD_SC_EMPTY; in qe_uart_set_termios()
925 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); in qe_uart_set_termios()
930 /* Update the per-port timeout. */ in qe_uart_set_termios()
931 uart_update_timeout(port, termios->c_cflag, baud); in qe_uart_set_termios()
933 iowrite16be(upsmr, &uccp->upsmr); in qe_uart_set_termios()
935 iowrite16be(supsmr, &uccup->supsmr); in qe_uart_set_termios()
936 iowrite8(tty_get_frame_size(termios->c_cflag), &uccup->rx_length); in qe_uart_set_termios()
938 /* Soft-UART requires a 1X multiplier for TX */ in qe_uart_set_termios()
939 qe_setbrg(qe_port->us_info.rx_clock, baud, 16); in qe_uart_set_termios()
940 qe_setbrg(qe_port->us_info.tx_clock, baud, 1); in qe_uart_set_termios()
942 qe_setbrg(qe_port->us_info.rx_clock, baud, 16); in qe_uart_set_termios()
943 qe_setbrg(qe_port->us_info.tx_clock, baud, 16); in qe_uart_set_termios()
954 return "QE"; in qe_uart_type()
965 struct ucc_slow_info *us_info = &qe_port->us_info; in qe_uart_request_port()
973 dev_err(port->dev, "could not initialize UCC%u\n", in qe_uart_request_port()
974 qe_port->ucc_num); in qe_uart_request_port()
978 qe_port->us_private = uccs; in qe_uart_request_port()
979 qe_port->uccp = uccs->us_regs; in qe_uart_request_port()
980 qe_port->uccup = (struct ucc_uart_pram __iomem *)uccs->us_pram; in qe_uart_request_port()
981 qe_port->rx_bd_base = uccs->rx_bd; in qe_uart_request_port()
982 qe_port->tx_bd_base = uccs->tx_bd; in qe_uart_request_port()
988 rx_size = L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize); in qe_uart_request_port()
989 tx_size = L1_CACHE_ALIGN(qe_port->tx_nrfifos * qe_port->tx_fifosize); in qe_uart_request_port()
991 bd_virt = dma_alloc_coherent(port->dev, rx_size + tx_size, &bd_dma_addr, in qe_uart_request_port()
994 dev_err(port->dev, "could not allocate buffer descriptors\n"); in qe_uart_request_port()
995 return -ENOMEM; in qe_uart_request_port()
998 qe_port->bd_virt = bd_virt; in qe_uart_request_port()
999 qe_port->bd_dma_addr = bd_dma_addr; in qe_uart_request_port()
1000 qe_port->bd_size = rx_size + tx_size; in qe_uart_request_port()
1002 qe_port->rx_buf = bd_virt; in qe_uart_request_port()
1003 qe_port->tx_buf = qe_port->rx_buf + rx_size; in qe_uart_request_port()
1011 * We say we're a CPM-type port because that's mostly true. Once the device
1018 port->type = PORT_CPM; in qe_uart_config_port()
1031 struct ucc_slow_private *uccs = qe_port->us_private; in qe_uart_release_port()
1033 dma_free_coherent(port->dev, qe_port->bd_size, qe_port->bd_virt, in qe_uart_release_port()
1034 qe_port->bd_dma_addr); in qe_uart_release_port()
1045 if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM) in qe_uart_verify_port()
1046 return -EINVAL; in qe_uart_verify_port()
1048 if (ser->irq < 0 || ser->irq >= irq_get_nr_irqs()) in qe_uart_verify_port()
1049 return -EINVAL; in qe_uart_verify_port()
1051 if (ser->baud_base < 9600) in qe_uart_verify_port()
1052 return -EINVAL; in qe_uart_verify_port()
1058 * Details on these functions can be found in Documentation/driver-api/serial/driver.rst
1118 soc_string = np->name; in soc_info()
1137 * This function is called by the kernel when a firmware is made available,
1138 * or if it times out waiting for the firmware.
1140 static void uart_firmware_cont(const struct firmware *fw, void *context) in uart_firmware_cont()
1142 struct qe_firmware *firmware; in uart_firmware_cont() local
1147 dev_err(dev, "firmware not found\n"); in uart_firmware_cont()
1151 firmware = (struct qe_firmware *) fw->data; in uart_firmware_cont()
1153 if (be32_to_cpu(firmware->header.length) != fw->size) { in uart_firmware_cont()
1154 dev_err(dev, "invalid firmware\n"); in uart_firmware_cont()
1158 ret = qe_upload_firmware(firmware); in uart_firmware_cont()
1160 dev_err(dev, "could not load firmware\n"); in uart_firmware_cont()
1171 struct device_node *np = ofdev->dev.of_node; in soft_uart_init()
1175 if (of_property_read_bool(np, "soft-uart")) { in soft_uart_init()
1176 dev_dbg(&ofdev->dev, "using Soft-UART mode\n"); in soft_uart_init()
1184 /* Check if the firmware has been uploaded. */ in soft_uart_init()
1185 if (qe_fw_info && strstr(qe_fw_info->id, "Soft-UART")) { in soft_uart_init()
1195 dev_err(&ofdev->dev, "unknown CPU model\n"); in soft_uart_init()
1196 return -ENXIO; in soft_uart_init()
1201 dev_info(&ofdev->dev, "waiting for firmware %s\n", in soft_uart_init()
1212 FW_ACTION_UEVENT, filename, &ofdev->dev, in soft_uart_init()
1213 GFP_KERNEL, &ofdev->dev, uart_firmware_cont); in soft_uart_init()
1215 dev_err(&ofdev->dev, in soft_uart_init()
1216 "could not load firmware %s\n", in soft_uart_init()
1236 struct device_node *np = ofdev->dev.of_node; in ucc_uart_probe()
1244 * Determine if we need Soft-UART mode in ucc_uart_probe()
1252 dev_err(&ofdev->dev, "can't allocate QE port structure\n"); in ucc_uart_probe()
1253 return -ENOMEM; in ucc_uart_probe()
1259 dev_err(&ofdev->dev, "missing 'reg' property in device tree\n"); in ucc_uart_probe()
1263 dev_err(&ofdev->dev, "invalid 'reg' property in device tree\n"); in ucc_uart_probe()
1264 ret = -EINVAL; in ucc_uart_probe()
1267 qe_port->port.mapbase = res.start; in ucc_uart_probe()
1270 /* UCCs are numbered 1-7 */ in ucc_uart_probe()
1271 if (of_property_read_u32(np, "cell-index", &val)) { in ucc_uart_probe()
1272 if (of_property_read_u32(np, "device-id", &val)) { in ucc_uart_probe()
1273 dev_err(&ofdev->dev, "UCC is unspecified in device tree\n"); in ucc_uart_probe()
1274 ret = -EINVAL; in ucc_uart_probe()
1280 dev_err(&ofdev->dev, "no support for UCC%u\n", val); in ucc_uart_probe()
1281 ret = -ENODEV; in ucc_uart_probe()
1284 qe_port->ucc_num = val - 1; in ucc_uart_probe()
1288 * device tree. If no clock-source is specified, then just pick a BRG in ucc_uart_probe()
1289 * to use. This requires a new QE library function that manages BRG in ucc_uart_probe()
1293 sprop = of_get_property(np, "rx-clock-name", NULL); in ucc_uart_probe()
1295 dev_err(&ofdev->dev, "missing rx-clock-name in device tree\n"); in ucc_uart_probe()
1296 ret = -ENODEV; in ucc_uart_probe()
1300 qe_port->us_info.rx_clock = qe_clock_source(sprop); in ucc_uart_probe()
1301 if ((qe_port->us_info.rx_clock < QE_BRG1) || in ucc_uart_probe()
1302 (qe_port->us_info.rx_clock > QE_BRG16)) { in ucc_uart_probe()
1303 dev_err(&ofdev->dev, "rx-clock-name must be a BRG for UART\n"); in ucc_uart_probe()
1304 ret = -ENODEV; in ucc_uart_probe()
1310 qe_port->us_info.tx_clock = qe_port->us_info.rx_clock; in ucc_uart_probe()
1312 sprop = of_get_property(np, "tx-clock-name", NULL); in ucc_uart_probe()
1314 dev_err(&ofdev->dev, "missing tx-clock-name in device tree\n"); in ucc_uart_probe()
1315 ret = -ENODEV; in ucc_uart_probe()
1318 qe_port->us_info.tx_clock = qe_clock_source(sprop); in ucc_uart_probe()
1320 if ((qe_port->us_info.tx_clock < QE_BRG1) || in ucc_uart_probe()
1321 (qe_port->us_info.tx_clock > QE_BRG16)) { in ucc_uart_probe()
1322 dev_err(&ofdev->dev, "tx-clock-name must be a BRG for UART\n"); in ucc_uart_probe()
1323 ret = -ENODEV; in ucc_uart_probe()
1327 /* Get the port number, numbered 0-3 */ in ucc_uart_probe()
1328 if (of_property_read_u32(np, "port-number", &val)) { in ucc_uart_probe()
1329 dev_err(&ofdev->dev, "missing port-number in device tree\n"); in ucc_uart_probe()
1330 ret = -EINVAL; in ucc_uart_probe()
1333 qe_port->port.line = val; in ucc_uart_probe()
1334 if (qe_port->port.line >= UCC_MAX_UART) { in ucc_uart_probe()
1335 dev_err(&ofdev->dev, "port-number must be 0-%u\n", in ucc_uart_probe()
1336 UCC_MAX_UART - 1); in ucc_uart_probe()
1337 ret = -EINVAL; in ucc_uart_probe()
1341 qe_port->port.irq = irq_of_parse_and_map(np, 0); in ucc_uart_probe()
1342 if (qe_port->port.irq == 0) { in ucc_uart_probe()
1343 dev_err(&ofdev->dev, "could not map IRQ for UCC%u\n", in ucc_uart_probe()
1344 qe_port->ucc_num + 1); in ucc_uart_probe()
1345 ret = -EINVAL; in ucc_uart_probe()
1350 * Newer device trees have an "fsl,qe" compatible property for the QE in ucc_uart_probe()
1353 np = of_find_compatible_node(NULL, NULL, "fsl,qe"); in ucc_uart_probe()
1355 np = of_find_node_by_type(NULL, "qe"); in ucc_uart_probe()
1357 dev_err(&ofdev->dev, "could not find 'qe' node\n"); in ucc_uart_probe()
1358 ret = -EINVAL; in ucc_uart_probe()
1363 if (of_property_read_u32(np, "brg-frequency", &val)) { in ucc_uart_probe()
1364 dev_err(&ofdev->dev, in ucc_uart_probe()
1365 "missing brg-frequency in device tree\n"); in ucc_uart_probe()
1366 ret = -EINVAL; in ucc_uart_probe()
1371 qe_port->port.uartclk = val; in ucc_uart_probe()
1374 dev_err(&ofdev->dev, in ucc_uart_probe()
1375 "invalid brg-frequency in device tree\n"); in ucc_uart_probe()
1376 ret = -EINVAL; in ucc_uart_probe()
1381 * Older versions of U-Boot do not initialize the brg-frequency in ucc_uart_probe()
1383 * half the QE bus frequency. in ucc_uart_probe()
1385 if (of_property_read_u32(np, "bus-frequency", &val)) { in ucc_uart_probe()
1386 dev_err(&ofdev->dev, in ucc_uart_probe()
1387 "missing QE bus-frequency in device tree\n"); in ucc_uart_probe()
1388 ret = -EINVAL; in ucc_uart_probe()
1392 qe_port->port.uartclk = val / 2; in ucc_uart_probe()
1394 dev_err(&ofdev->dev, in ucc_uart_probe()
1395 "invalid QE bus-frequency in device tree\n"); in ucc_uart_probe()
1396 ret = -EINVAL; in ucc_uart_probe()
1401 spin_lock_init(&qe_port->port.lock); in ucc_uart_probe()
1402 qe_port->np = np; in ucc_uart_probe()
1403 qe_port->port.dev = &ofdev->dev; in ucc_uart_probe()
1404 qe_port->port.ops = &qe_uart_pops; in ucc_uart_probe()
1405 qe_port->port.iotype = UPIO_MEM; in ucc_uart_probe()
1407 qe_port->tx_nrfifos = TX_NUM_FIFO; in ucc_uart_probe()
1408 qe_port->tx_fifosize = TX_BUF_SIZE; in ucc_uart_probe()
1409 qe_port->rx_nrfifos = RX_NUM_FIFO; in ucc_uart_probe()
1410 qe_port->rx_fifosize = RX_BUF_SIZE; in ucc_uart_probe()
1412 qe_port->wait_closing = UCC_WAIT_CLOSING; in ucc_uart_probe()
1413 qe_port->port.fifosize = 512; in ucc_uart_probe()
1414 qe_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP; in ucc_uart_probe()
1416 qe_port->us_info.ucc_num = qe_port->ucc_num; in ucc_uart_probe()
1417 qe_port->us_info.regs = (phys_addr_t) res.start; in ucc_uart_probe()
1418 qe_port->us_info.irq = qe_port->port.irq; in ucc_uart_probe()
1420 qe_port->us_info.rx_bd_ring_len = qe_port->rx_nrfifos; in ucc_uart_probe()
1421 qe_port->us_info.tx_bd_ring_len = qe_port->tx_nrfifos; in ucc_uart_probe()
1424 qe_port->us_info.init_tx = 1; in ucc_uart_probe()
1425 qe_port->us_info.init_rx = 1; in ucc_uart_probe()
1427 /* Add the port to the uart sub-system. This will cause in ucc_uart_probe()
1431 ret = uart_add_one_port(&ucc_uart_driver, &qe_port->port); in ucc_uart_probe()
1433 dev_err(&ofdev->dev, "could not add /dev/ttyQE%u\n", in ucc_uart_probe()
1434 qe_port->port.line); in ucc_uart_probe()
1440 dev_info(&ofdev->dev, "UCC%u assigned to /dev/ttyQE%u\n", in ucc_uart_probe()
1441 qe_port->ucc_num + 1, qe_port->port.line); in ucc_uart_probe()
1444 dev_dbg(&ofdev->dev, "mknod command is 'mknod /dev/ttyQE%u c %u %u'\n", in ucc_uart_probe()
1445 qe_port->port.line, SERIAL_QE_MAJOR, in ucc_uart_probe()
1446 SERIAL_QE_MINOR + qe_port->port.line); in ucc_uart_probe()
1460 dev_info(&ofdev->dev, "removing /dev/ttyQE%u\n", qe_port->port.line); in ucc_uart_remove()
1462 uart_remove_one_port(&ucc_uart_driver, &qe_port->port); in ucc_uart_remove()
1464 of_node_put(qe_port->np); in ucc_uart_remove()
1475 .compatible = "fsl,t1040-ucc-uart",
1496 printk(KERN_INFO "ucc-uart: Using loopback mode\n"); in ucc_uart_init()
1501 printk(KERN_ERR "ucc-uart: could not register UART driver\n"); in ucc_uart_init()
1508 "ucc-uart: could not register platform driver\n"); in ucc_uart_init()
1527 MODULE_DESCRIPTION("Freescale QUICC Engine (QE) UART");