Lines Matching +full:write +full:- +full:1 +full:- +full:bps
1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2) argument
30 /* Write Register 0 */
32 #define R1 1
61 /* Write Register 1 */
77 /* Write Register #2 (Interrupt Vector) */
79 /* Write Register 3 */
93 /* Write Register 4 */
99 #define SB1 0x4 /* 1 stop bit/char */
114 /* Write Register 5 */
118 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
128 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
130 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
132 /* Write Register 7' (ESCC Only) */
133 #define AUTO_TxFLAG 1 /* Automatic Tx SDLC Flag */
141 /* Write Register 8 (transmit buffer) */
143 /* Write Register 9 (Master interrupt control) */
144 #define VIS 1 /* Vector Includes Status */
150 #define NORESET 0 /* No reset on write to R9 */
155 /* Write Register 10 (misc control bits) */
156 #define BIT6 1 /* 6 bit/8bit sync */
163 #define FM1 0x40 /* FM1 (transition = 1) */
167 /* Write Register 11 (Clock Mode control) */
169 #define TRxCTC 1 /* TRxC = Transmit clock */
183 /* Write Register 12 (lower byte of baud rate generator time constant) */
185 /* Write Register 13 (upper byte of baud rate generator time constant) */
187 /* Write Register 14 (Misc control bits) */
188 #define BRENAB 1 /* Baud rate generator enable */
201 /* Write Register 15 (external/status interrupt control) */
202 #define WR7pEN 1 /* WR7' Enable (ESCC only) */
222 /* Read Register 1 */
231 #define RES18 0xe /* 1/8 */
239 /* Read Register 2 (channel b only) - Interrupt vector */
277 #define ZS_CLEARERR(channel) do { sbus_writeb(ERR_RES, &channel->control); \
280 #define ZS_CLEARSTAT(channel) do { sbus_writeb(RES_EXT_INT, &channel->control); \
283 #define ZS_CLEARFIFO(channel) do { sbus_readb(&channel->data); \
285 sbus_readb(&channel->data); \
287 sbus_readb(&channel->data); \