Lines Matching +full:cts +full:- +full:rts +full:- +full:swap
1 // SPDX-License-Identifier: GPL-2.0
9 * Inspired by st-asc.c from STMicroelectronics (c)
16 #include <linux/dma-direction.h>
18 #include <linux/dma-mapping.h>
37 #include "stm32-usart.h"
124 val = readl_relaxed(port->membase + reg); in stm32_usart_set_bits()
126 writel_relaxed(val, port->membase + reg); in stm32_usart_set_bits()
133 val = readl_relaxed(port->membase + reg); in stm32_usart_clr_bits()
135 writel_relaxed(val, port->membase + reg); in stm32_usart_clr_bits()
141 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_tx_empty()
143 if (readl_relaxed(port->membase + ofs->isr) & USART_SR_TC) in stm32_usart_tx_empty()
152 struct serial_rs485 *rs485conf = &port->rs485; in stm32_usart_rs485_rts_enable()
154 if (stm32_port->hw_flow_control || in stm32_usart_rs485_rts_enable()
155 !(rs485conf->flags & SER_RS485_ENABLED)) in stm32_usart_rs485_rts_enable()
158 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { in stm32_usart_rs485_rts_enable()
159 mctrl_gpio_set(stm32_port->gpios, in stm32_usart_rs485_rts_enable()
160 stm32_port->port.mctrl | TIOCM_RTS); in stm32_usart_rs485_rts_enable()
162 mctrl_gpio_set(stm32_port->gpios, in stm32_usart_rs485_rts_enable()
163 stm32_port->port.mctrl & ~TIOCM_RTS); in stm32_usart_rs485_rts_enable()
170 struct serial_rs485 *rs485conf = &port->rs485; in stm32_usart_rs485_rts_disable()
172 if (stm32_port->hw_flow_control || in stm32_usart_rs485_rts_disable()
173 !(rs485conf->flags & SER_RS485_ENABLED)) in stm32_usart_rs485_rts_disable()
176 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { in stm32_usart_rs485_rts_disable()
177 mctrl_gpio_set(stm32_port->gpios, in stm32_usart_rs485_rts_disable()
178 stm32_port->port.mctrl & ~TIOCM_RTS); in stm32_usart_rs485_rts_disable()
180 mctrl_gpio_set(stm32_port->gpios, in stm32_usart_rs485_rts_disable()
181 stm32_port->port.mctrl | TIOCM_RTS); in stm32_usart_rs485_rts_disable()
226 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_config_rs485()
227 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_config_rs485()
231 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_usart_config_rs485()
233 if (rs485conf->flags & SER_RS485_ENABLED) { in stm32_usart_config_rs485()
234 cr1 = readl_relaxed(port->membase + ofs->cr1); in stm32_usart_config_rs485()
235 cr3 = readl_relaxed(port->membase + ofs->cr3); in stm32_usart_config_rs485()
236 usartdiv = readl_relaxed(port->membase + ofs->brr); in stm32_usart_config_rs485()
244 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv); in stm32_usart_config_rs485()
246 rs485conf->delay_rts_before_send, in stm32_usart_config_rs485()
247 rs485conf->delay_rts_after_send, in stm32_usart_config_rs485()
250 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) in stm32_usart_config_rs485()
255 writel_relaxed(cr3, port->membase + ofs->cr3); in stm32_usart_config_rs485()
256 writel_relaxed(cr1, port->membase + ofs->cr1); in stm32_usart_config_rs485()
258 if (!port->rs485_rx_during_tx_gpio) in stm32_usart_config_rs485()
259 rs485conf->flags |= SER_RS485_RX_DURING_TX; in stm32_usart_config_rs485()
262 stm32_usart_clr_bits(port, ofs->cr3, in stm32_usart_config_rs485()
264 stm32_usart_clr_bits(port, ofs->cr1, in stm32_usart_config_rs485()
268 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_usart_config_rs485()
270 /* Adjust RTS polarity in case it's driven in software */ in stm32_usart_config_rs485()
282 struct serial_rs485 *rs485conf = &port->rs485; in stm32_usart_init_rs485()
284 rs485conf->flags = 0; in stm32_usart_init_rs485()
285 rs485conf->delay_rts_before_send = 0; in stm32_usart_init_rs485()
286 rs485conf->delay_rts_after_send = 0; in stm32_usart_init_rs485()
288 if (!pdev->dev.of_node) in stm32_usart_init_rs485()
289 return -ENODEV; in stm32_usart_init_rs485()
296 return stm32_port->rx_ch ? stm32_port->rx_dma_busy : false; in stm32_usart_rx_dma_started()
301 dmaengine_terminate_async(stm32_port->rx_ch); in stm32_usart_rx_dma_terminate()
302 stm32_port->rx_dma_busy = false; in stm32_usart_rx_dma_terminate()
312 struct uart_port *port = &stm32_port->port; in stm32_usart_dma_pause_resume()
317 return -EPERM; in stm32_usart_dma_pause_resume()
319 dma_status = dmaengine_tx_status(chan, chan->cookie, NULL); in stm32_usart_dma_pause_resume()
321 return -EAGAIN; in stm32_usart_dma_pause_resume()
325 dev_err(port->dev, "DMA failed with error code: %d\n", ret); in stm32_usart_dma_pause_resume()
333 return stm32_usart_dma_pause_resume(stm32_port, stm32_port->rx_ch, in stm32_usart_rx_dma_pause()
341 return stm32_usart_dma_pause_resume(stm32_port, stm32_port->rx_ch, in stm32_usart_rx_dma_resume()
351 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_pending_rx_pio()
353 *sr = readl_relaxed(port->membase + ofs->isr); in stm32_usart_pending_rx_pio()
371 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_get_char_pio()
374 c = readl_relaxed(port->membase + ofs->rdr); in stm32_usart_get_char_pio()
376 c &= stm32_port->rdr_mask; in stm32_usart_get_char_pio()
384 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_receive_chars_pio()
402 * cleared by the sequence [read SR - read DR]. in stm32_usart_receive_chars_pio()
404 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG) in stm32_usart_receive_chars_pio()
406 port->membase + ofs->icr); in stm32_usart_receive_chars_pio()
409 port->icount.rx++; in stm32_usart_receive_chars_pio()
413 port->icount.overrun++; in stm32_usart_receive_chars_pio()
415 port->icount.parity++; in stm32_usart_receive_chars_pio()
419 port->icount.brk++; in stm32_usart_receive_chars_pio()
423 port->icount.frame++; in stm32_usart_receive_chars_pio()
427 sr &= port->read_status_mask; in stm32_usart_receive_chars_pio()
450 struct tty_port *ttyport = &stm32_port->port.state->port; in stm32_usart_push_buffer_dma()
454 dma_start = stm32_port->rx_buf + (RX_BUF_L - stm32_port->last_res); in stm32_usart_push_buffer_dma()
461 if (!(stm32_port->rdr_mask == (BIT(8) - 1))) in stm32_usart_push_buffer_dma()
463 *(dma_start + i) &= stm32_port->rdr_mask; in stm32_usart_push_buffer_dma()
466 port->icount.rx += dma_count; in stm32_usart_push_buffer_dma()
468 port->icount.buf_overrun++; in stm32_usart_push_buffer_dma()
469 stm32_port->last_res -= dma_count; in stm32_usart_push_buffer_dma()
470 if (stm32_port->last_res == 0) in stm32_usart_push_buffer_dma()
471 stm32_port->last_res = RX_BUF_L; in stm32_usart_push_buffer_dma()
480 if (stm32_port->rx_dma_state.residue > stm32_port->last_res) { in stm32_usart_receive_chars_dma()
482 dma_size = stm32_port->last_res; in stm32_usart_receive_chars_dma()
487 dma_size = stm32_port->last_res - stm32_port->rx_dma_state.residue; in stm32_usart_receive_chars_dma()
497 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_receive_chars()
503 rx_dma_status = dmaengine_tx_status(stm32_port->rx_ch, in stm32_usart_receive_chars()
504 stm32_port->rx_ch->cookie, in stm32_usart_receive_chars()
505 &stm32_port->rx_dma_state); in stm32_usart_receive_chars()
510 sr = readl_relaxed(port->membase + ofs->isr); in stm32_usart_receive_chars()
513 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); in stm32_usart_receive_chars()
519 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAR); in stm32_usart_receive_chars()
525 dev_dbg(port->dev, "DMA error, fallback to irq mode\n"); in stm32_usart_receive_chars()
538 struct tty_port *tport = &port->state->port; in stm32_usart_rx_dma_complete()
556 if (stm32_port->throttled) in stm32_usart_rx_dma_start_or_resume()
559 if (stm32_port->rx_dma_busy) { in stm32_usart_rx_dma_start_or_resume()
560 rx_dma_status = dmaengine_tx_status(stm32_port->rx_ch, in stm32_usart_rx_dma_start_or_resume()
561 stm32_port->rx_ch->cookie, in stm32_usart_rx_dma_start_or_resume()
569 dev_err(port->dev, "DMA failed : status error.\n"); in stm32_usart_rx_dma_start_or_resume()
573 stm32_port->rx_dma_busy = true; in stm32_usart_rx_dma_start_or_resume()
575 stm32_port->last_res = RX_BUF_L; in stm32_usart_rx_dma_start_or_resume()
577 desc = dmaengine_prep_dma_cyclic(stm32_port->rx_ch, in stm32_usart_rx_dma_start_or_resume()
578 stm32_port->rx_dma_buf, in stm32_usart_rx_dma_start_or_resume()
583 dev_err(port->dev, "rx dma prep cyclic failed\n"); in stm32_usart_rx_dma_start_or_resume()
584 stm32_port->rx_dma_busy = false; in stm32_usart_rx_dma_start_or_resume()
585 return -ENODEV; in stm32_usart_rx_dma_start_or_resume()
588 desc->callback = stm32_usart_rx_dma_complete; in stm32_usart_rx_dma_start_or_resume()
589 desc->callback_param = port; in stm32_usart_rx_dma_start_or_resume()
594 dmaengine_terminate_sync(stm32_port->rx_ch); in stm32_usart_rx_dma_start_or_resume()
595 stm32_port->rx_dma_busy = false; in stm32_usart_rx_dma_start_or_resume()
600 dma_async_issue_pending(stm32_port->rx_ch); in stm32_usart_rx_dma_start_or_resume()
607 dmaengine_terminate_async(stm32_port->tx_ch); in stm32_usart_tx_dma_terminate()
608 stm32_port->tx_dma_busy = false; in stm32_usart_tx_dma_terminate()
620 return stm32_port->tx_dma_busy; in stm32_usart_tx_dma_started()
625 return stm32_usart_dma_pause_resume(stm32_port, stm32_port->tx_ch, in stm32_usart_tx_dma_pause()
633 return stm32_usart_dma_pause_resume(stm32_port, stm32_port->tx_ch, in stm32_usart_tx_dma_resume()
656 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_tx_interrupt_enable()
662 if (stm32_port->fifoen && stm32_port->txftcfg >= 0) in stm32_usart_tx_interrupt_enable()
663 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_TXFTIE); in stm32_usart_tx_interrupt_enable()
665 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE); in stm32_usart_tx_interrupt_enable()
671 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_tc_interrupt_enable()
673 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TCIE); in stm32_usart_tc_interrupt_enable()
679 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_tx_interrupt_disable()
681 if (stm32_port->fifoen && stm32_port->txftcfg >= 0) in stm32_usart_tx_interrupt_disable()
682 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE); in stm32_usart_tx_interrupt_disable()
684 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); in stm32_usart_tx_interrupt_disable()
690 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_tc_interrupt_disable()
692 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TCIE); in stm32_usart_tc_interrupt_disable()
698 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_transmit_chars_pio()
699 struct tty_port *tport = &port->state->port; in stm32_usart_transmit_chars_pio()
705 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) in stm32_usart_transmit_chars_pio()
711 writel_relaxed(ch, port->membase + ofs->tdr); in stm32_usart_transmit_chars_pio()
715 if (kfifo_is_empty(&tport->xmit_fifo)) in stm32_usart_transmit_chars_pio()
724 struct tty_port *tport = &port->state->port; in stm32_usart_transmit_chars_dma()
731 if (ret < 0 && ret != -EAGAIN) in stm32_usart_transmit_chars_dma()
736 count = kfifo_out_peek(&tport->xmit_fifo, &stm32port->tx_buf[0], in stm32_usart_transmit_chars_dma()
739 desc = dmaengine_prep_slave_single(stm32port->tx_ch, in stm32_usart_transmit_chars_dma()
740 stm32port->tx_dma_buf, in stm32_usart_transmit_chars_dma()
754 stm32port->tx_dma_busy = true; in stm32_usart_transmit_chars_dma()
756 desc->callback = stm32_usart_tx_dma_complete; in stm32_usart_transmit_chars_dma()
757 desc->callback_param = port; in stm32_usart_transmit_chars_dma()
763 dev_err(port->dev, "DMA failed with error code: %d\n", ret); in stm32_usart_transmit_chars_dma()
769 dma_async_issue_pending(stm32port->tx_ch); in stm32_usart_transmit_chars_dma()
782 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_transmit_chars()
783 struct tty_port *tport = &port->state->port; in stm32_usart_transmit_chars()
787 if (!stm32_port->hw_flow_control && in stm32_usart_transmit_chars()
788 port->rs485.flags & SER_RS485_ENABLED && in stm32_usart_transmit_chars()
789 (port->x_char || in stm32_usart_transmit_chars()
790 !(kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)))) { in stm32_usart_transmit_chars()
795 if (port->x_char) { in stm32_usart_transmit_chars()
801 readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, in stm32_usart_transmit_chars()
806 dev_warn(port->dev, "1 character may be erased\n"); in stm32_usart_transmit_chars()
808 writel_relaxed(port->x_char, port->membase + ofs->tdr); in stm32_usart_transmit_chars()
809 port->x_char = 0; in stm32_usart_transmit_chars()
810 port->icount.tx++; in stm32_usart_transmit_chars()
817 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)) { in stm32_usart_transmit_chars()
822 if (ofs->icr == UNDEF_REG) in stm32_usart_transmit_chars()
823 stm32_usart_clr_bits(port, ofs->isr, USART_SR_TC); in stm32_usart_transmit_chars()
825 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr); in stm32_usart_transmit_chars()
827 if (stm32_port->tx_ch) in stm32_usart_transmit_chars()
832 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in stm32_usart_transmit_chars()
835 if (kfifo_is_empty(&tport->xmit_fifo)) { in stm32_usart_transmit_chars()
837 if (!stm32_port->hw_flow_control && in stm32_usart_transmit_chars()
838 port->rs485.flags & SER_RS485_ENABLED) { in stm32_usart_transmit_chars()
847 struct tty_port *tport = &port->state->port; in stm32_usart_interrupt()
849 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_interrupt()
854 sr = readl_relaxed(port->membase + ofs->isr); in stm32_usart_interrupt()
856 if (!stm32_port->hw_flow_control && in stm32_usart_interrupt()
857 port->rs485.flags & SER_RS485_ENABLED && in stm32_usart_interrupt()
864 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG) { in stm32_usart_interrupt()
866 port->membase + ofs->icr); in stm32_usart_interrupt()
870 if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG) { in stm32_usart_interrupt()
873 port->membase + ofs->icr); in stm32_usart_interrupt()
874 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE); in stm32_usart_interrupt()
875 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq))) in stm32_usart_interrupt()
876 pm_wakeup_event(tport->tty->dev, 0); in stm32_usart_interrupt()
884 if (!stm32_port->throttled) { in stm32_usart_interrupt()
896 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) { in stm32_usart_interrupt()
904 if (stm32_usart_rx_dma_started(stm32_port) && !stm32_port->throttled) { in stm32_usart_interrupt()
919 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_set_mctrl()
921 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) in stm32_usart_set_mctrl()
922 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_RTSE); in stm32_usart_set_mctrl()
924 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_RTSE); in stm32_usart_set_mctrl()
926 mctrl_gpio_set(stm32_port->gpios, mctrl); in stm32_usart_set_mctrl()
934 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */ in stm32_usart_get_mctrl()
937 return mctrl_gpio_get(stm32_port->gpios, &ret); in stm32_usart_get_mctrl()
942 mctrl_gpio_enable_ms(to_stm32_port(port)->gpios); in stm32_usart_enable_ms()
947 mctrl_gpio_disable_ms(to_stm32_port(port)->gpios); in stm32_usart_disable_ms()
966 struct tty_port *tport = &port->state->port; in stm32_usart_start_tx()
968 if (kfifo_is_empty(&tport->xmit_fifo) && !port->x_char) in stm32_usart_start_tx()
981 if (stm32_port->tx_ch) in stm32_usart_flush_buffer()
989 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_throttle()
1000 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); in stm32_usart_throttle()
1001 if (stm32_port->cr3_irq) in stm32_usart_throttle()
1002 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); in stm32_usart_throttle()
1004 stm32_port->throttled = true; in stm32_usart_throttle()
1012 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_unthrottle()
1016 stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq); in stm32_usart_unthrottle()
1017 if (stm32_port->cr3_irq) in stm32_usart_unthrottle()
1018 stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq); in stm32_usart_unthrottle()
1020 stm32_port->throttled = false; in stm32_usart_unthrottle()
1026 if (stm32_port->rx_ch) in stm32_usart_unthrottle()
1036 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_stop_rx()
1041 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); in stm32_usart_stop_rx()
1042 if (stm32_port->cr3_irq) in stm32_usart_stop_rx()
1043 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); in stm32_usart_stop_rx()
1049 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_break_ctl()
1055 stm32_usart_set_bits(port, ofs->rqr, USART_RQR_SBKRQ); in stm32_usart_break_ctl()
1057 stm32_usart_clr_bits(port, ofs->rqr, USART_RQR_SBKRQ); in stm32_usart_break_ctl()
1065 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_startup()
1066 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_startup()
1067 const char *name = to_platform_device(port->dev)->name; in stm32_usart_startup()
1071 ret = request_irq(port->irq, stm32_usart_interrupt, in stm32_usart_startup()
1076 if (stm32_port->swap) { in stm32_usart_startup()
1077 val = readl_relaxed(port->membase + ofs->cr2); in stm32_usart_startup()
1079 writel_relaxed(val, port->membase + ofs->cr2); in stm32_usart_startup()
1081 stm32_port->throttled = false; in stm32_usart_startup()
1084 if (ofs->rqr != UNDEF_REG) in stm32_usart_startup()
1085 writel_relaxed(USART_RQR_RXFRQ, port->membase + ofs->rqr); in stm32_usart_startup()
1087 if (stm32_port->rx_ch) { in stm32_usart_startup()
1090 free_irq(port->irq, port); in stm32_usart_startup()
1096 val = stm32_port->cr1_irq | USART_CR1_RE | BIT(cfg->uart_enable_bit); in stm32_usart_startup()
1097 stm32_usart_set_bits(port, ofs->cr1, val); in stm32_usart_startup()
1105 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_shutdown()
1106 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_shutdown()
1113 if (stm32_port->tx_ch) in stm32_usart_shutdown()
1114 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_shutdown()
1120 val |= stm32_port->cr1_irq | USART_CR1_RE; in stm32_usart_shutdown()
1121 val |= BIT(cfg->uart_enable_bit); in stm32_usart_shutdown()
1122 if (stm32_port->fifoen) in stm32_usart_shutdown()
1125 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr, in stm32_usart_shutdown()
1131 dev_err(port->dev, "Transmission is not complete\n"); in stm32_usart_shutdown()
1134 if (stm32_port->rx_ch) { in stm32_usart_shutdown()
1136 dmaengine_synchronize(stm32_port->rx_ch); in stm32_usart_shutdown()
1140 if (ofs->rqr != UNDEF_REG) in stm32_usart_shutdown()
1142 port->membase + ofs->rqr); in stm32_usart_shutdown()
1144 stm32_usart_clr_bits(port, ofs->cr1, val); in stm32_usart_shutdown()
1146 free_irq(port->irq, port); in stm32_usart_shutdown()
1156 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_set_termios()
1157 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_set_termios()
1158 struct serial_rs485 *rs485conf = &port->rs485; in stm32_usart_set_termios()
1161 tcflag_t cflag = termios->c_cflag; in stm32_usart_set_termios()
1166 if (!stm32_port->hw_flow_control) in stm32_usart_set_termios()
1169 uart_clk = clk_get_rate(stm32_port->clk); in stm32_usart_set_termios()
1175 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, in stm32_usart_set_termios()
1182 dev_err(port->dev, "Transmission is not complete\n"); in stm32_usart_set_termios()
1185 writel_relaxed(0, port->membase + ofs->cr1); in stm32_usart_set_termios()
1188 if (ofs->rqr != UNDEF_REG) in stm32_usart_set_termios()
1190 port->membase + ofs->rqr); in stm32_usart_set_termios()
1193 if (stm32_port->fifoen) in stm32_usart_set_termios()
1195 cr2 = stm32_port->swap ? USART_CR2_SWAP : 0; in stm32_usart_set_termios()
1198 cr3 = readl_relaxed(port->membase + ofs->cr3); in stm32_usart_set_termios()
1200 if (stm32_port->fifoen) { in stm32_usart_set_termios()
1201 if (stm32_port->txftcfg >= 0) in stm32_usart_set_termios()
1202 cr3 |= stm32_port->txftcfg << USART_CR3_TXFTCFG_SHIFT; in stm32_usart_set_termios()
1203 if (stm32_port->rxftcfg >= 0) in stm32_usart_set_termios()
1204 cr3 |= stm32_port->rxftcfg << USART_CR3_RXFTCFG_SHIFT; in stm32_usart_set_termios()
1211 stm32_port->rdr_mask = (BIT(bits) - 1); in stm32_usart_set_termios()
1227 } else if ((bits == 7) && cfg->has_7bits_data) { in stm32_usart_set_termios()
1230 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n" in stm32_usart_set_termios()
1234 termios->c_cflag = cflag; in stm32_usart_set_termios()
1242 if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch || in stm32_usart_set_termios()
1243 (stm32_port->fifoen && in stm32_usart_set_termios()
1244 stm32_port->rxftcfg >= 0))) { in stm32_usart_set_termios()
1251 stm32_port->cr1_irq = USART_CR1_RTOIE; in stm32_usart_set_termios()
1252 writel_relaxed(bits, port->membase + ofs->rtor); in stm32_usart_set_termios()
1256 * wake up over usart, from low power until the DMA gets re-enabled by resume. in stm32_usart_set_termios()
1258 stm32_port->cr3_irq = USART_CR3_RXFTIE; in stm32_usart_set_termios()
1261 cr1 |= stm32_port->cr1_irq; in stm32_usart_set_termios()
1262 cr3 |= stm32_port->cr3_irq; in stm32_usart_set_termios()
1267 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); in stm32_usart_set_termios()
1269 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; in stm32_usart_set_termios()
1286 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_OVER8); in stm32_usart_set_termios()
1290 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_OVER8); in stm32_usart_set_termios()
1298 if (ofs->presc != UNDEF_REG) { in stm32_usart_set_termios()
1299 port->uartclk = uart_clk_pres; in stm32_usart_set_termios()
1300 writel_relaxed(presc, port->membase + ofs->presc); in stm32_usart_set_termios()
1303 dev_err(port->dev, in stm32_usart_set_termios()
1309 dev_err(port->dev, "unable to set baudrate, input clock is too high"); in stm32_usart_set_termios()
1314 writel_relaxed(brr, port->membase + ofs->brr); in stm32_usart_set_termios()
1318 port->read_status_mask = USART_SR_ORE; in stm32_usart_set_termios()
1319 if (termios->c_iflag & INPCK) in stm32_usart_set_termios()
1320 port->read_status_mask |= USART_SR_PE | USART_SR_FE; in stm32_usart_set_termios()
1321 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in stm32_usart_set_termios()
1322 port->read_status_mask |= USART_SR_FE; in stm32_usart_set_termios()
1325 port->ignore_status_mask = 0; in stm32_usart_set_termios()
1326 if (termios->c_iflag & IGNPAR) in stm32_usart_set_termios()
1327 port->ignore_status_mask = USART_SR_PE | USART_SR_FE; in stm32_usart_set_termios()
1328 if (termios->c_iflag & IGNBRK) { in stm32_usart_set_termios()
1329 port->ignore_status_mask |= USART_SR_FE; in stm32_usart_set_termios()
1334 if (termios->c_iflag & IGNPAR) in stm32_usart_set_termios()
1335 port->ignore_status_mask |= USART_SR_ORE; in stm32_usart_set_termios()
1339 if ((termios->c_cflag & CREAD) == 0) in stm32_usart_set_termios()
1340 port->ignore_status_mask |= USART_SR_DUMMY_RX; in stm32_usart_set_termios()
1342 if (stm32_port->rx_ch) { in stm32_usart_set_termios()
1353 if (stm32_port->tx_ch) in stm32_usart_set_termios()
1356 if (rs485conf->flags & SER_RS485_ENABLED) { in stm32_usart_set_termios()
1358 rs485conf->delay_rts_before_send, in stm32_usart_set_termios()
1359 rs485conf->delay_rts_after_send, in stm32_usart_set_termios()
1361 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { in stm32_usart_set_termios()
1363 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; in stm32_usart_set_termios()
1366 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; in stm32_usart_set_termios()
1375 if (stm32_port->wakeup_src) { in stm32_usart_set_termios()
1380 writel_relaxed(cr3, port->membase + ofs->cr3); in stm32_usart_set_termios()
1381 writel_relaxed(cr2, port->membase + ofs->cr2); in stm32_usart_set_termios()
1382 writel_relaxed(cr1, port->membase + ofs->cr1); in stm32_usart_set_termios()
1384 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_usart_set_termios()
1388 if (UART_ENABLE_MS(port, termios->c_cflag)) in stm32_usart_set_termios()
1396 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL; in stm32_usart_type()
1411 port->type = PORT_STM32; in stm32_usart_config_port()
1418 return -EINVAL; in stm32_usart_verify_port()
1426 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_usart_pm()
1427 const struct stm32_usart_config *cfg = &stm32port->info->cfg; in stm32_usart_pm()
1432 pm_runtime_get_sync(port->dev); in stm32_usart_pm()
1436 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_usart_pm()
1438 pm_runtime_put_sync(port->dev); in stm32_usart_pm()
1450 return clk_prepare_enable(stm32_port->clk); in stm32_usart_poll_init()
1456 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_poll_get_char()
1458 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_RXNE)) in stm32_usart_poll_get_char()
1461 return readl_relaxed(port->membase + ofs->rdr) & stm32_port->rdr_mask; in stm32_usart_poll_get_char()
1515 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_usart_get_ftcfg()
1519 if (WARN_ON(ofs->hwcfgr1 == UNDEF_REG)) in stm32_usart_get_ftcfg()
1523 readl_relaxed(stm32port->port.membase + ofs->hwcfgr1)); in stm32_usart_get_ftcfg()
1529 if (of_property_read_u32(pdev->dev.of_node, p, &bytes)) in stm32_usart_get_ftcfg()
1533 *ftcfg = -EINVAL; in stm32_usart_get_ftcfg()
1542 i = ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg) - 1; in stm32_usart_get_ftcfg()
1544 dev_dbg(&pdev->dev, "%s set to %d/%d bytes\n", p, in stm32_usart_get_ftcfg()
1553 clk_disable_unprepare(stm32port->clk); in stm32_usart_deinit_port()
1566 struct uart_port *port = &stm32port->port; in stm32_usart_init_port()
1574 port->iotype = UPIO_MEM; in stm32_usart_init_port()
1575 port->flags = UPF_BOOT_AUTOCONF; in stm32_usart_init_port()
1576 port->ops = &stm32_uart_ops; in stm32_usart_init_port()
1577 port->dev = &pdev->dev; in stm32_usart_init_port()
1578 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE); in stm32_usart_init_port()
1579 port->irq = irq; in stm32_usart_init_port()
1580 port->rs485_config = stm32_usart_config_rs485; in stm32_usart_init_port()
1581 port->rs485_supported = stm32_rs485_supported; in stm32_usart_init_port()
1587 stm32port->wakeup_src = stm32port->info->cfg.has_wakeup && in stm32_usart_init_port()
1588 of_property_read_bool(pdev->dev.of_node, "wakeup-source"); in stm32_usart_init_port()
1590 stm32port->swap = stm32port->info->cfg.has_swap && in stm32_usart_init_port()
1591 of_property_read_bool(pdev->dev.of_node, "rx-tx-swap"); in stm32_usart_init_port()
1593 port->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in stm32_usart_init_port()
1594 if (IS_ERR(port->membase)) in stm32_usart_init_port()
1595 return PTR_ERR(port->membase); in stm32_usart_init_port()
1596 port->mapbase = res->start; in stm32_usart_init_port()
1598 spin_lock_init(&port->lock); in stm32_usart_init_port()
1600 stm32port->clk = devm_clk_get(&pdev->dev, NULL); in stm32_usart_init_port()
1601 if (IS_ERR(stm32port->clk)) in stm32_usart_init_port()
1602 return PTR_ERR(stm32port->clk); in stm32_usart_init_port()
1605 ret = clk_prepare_enable(stm32port->clk); in stm32_usart_init_port()
1609 stm32port->port.uartclk = clk_get_rate(stm32port->clk); in stm32_usart_init_port()
1610 if (!stm32port->port.uartclk) { in stm32_usart_init_port()
1611 ret = -EINVAL; in stm32_usart_init_port()
1615 stm32port->fifoen = stm32port->info->cfg.has_fifo; in stm32_usart_init_port()
1616 if (stm32port->fifoen) { in stm32_usart_init_port()
1617 stm32_usart_get_ftcfg(pdev, stm32port, "rx-threshold", &stm32port->rxftcfg); in stm32_usart_init_port()
1618 port->fifosize = stm32_usart_get_ftcfg(pdev, stm32port, "tx-threshold", in stm32_usart_init_port()
1619 &stm32port->txftcfg); in stm32_usart_init_port()
1621 port->fifosize = 1; in stm32_usart_init_port()
1624 stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0); in stm32_usart_init_port()
1625 if (IS_ERR(stm32port->gpios)) { in stm32_usart_init_port()
1626 ret = PTR_ERR(stm32port->gpios); in stm32_usart_init_port()
1631 * Both CTS/RTS gpios and "st,hw-flow-ctrl" (deprecated) or "uart-has-rtscts" in stm32_usart_init_port()
1634 if (stm32port->hw_flow_control) { in stm32_usart_init_port()
1635 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) || in stm32_usart_init_port()
1636 mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) { in stm32_usart_init_port()
1637 dev_err(&pdev->dev, "Conflicting RTS/CTS config\n"); in stm32_usart_init_port()
1638 ret = -EINVAL; in stm32_usart_init_port()
1646 clk_disable_unprepare(stm32port->clk); in stm32_usart_init_port()
1653 struct device_node *np = pdev->dev.of_node; in stm32_usart_of_get_port()
1661 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id); in stm32_usart_of_get_port()
1669 of_property_read_bool (np, "st,hw-flow-ctrl") /*deprecated*/ || in stm32_usart_of_get_port()
1670 of_property_read_bool (np, "uart-has-rtscts"); in stm32_usart_of_get_port()
1680 { .compatible = "st,stm32-uart", .data = &stm32f4_info},
1681 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
1682 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info},
1692 if (stm32port->rx_buf) in stm32_usart_of_dma_rx_remove()
1693 dma_free_coherent(&pdev->dev, RX_BUF_L, stm32port->rx_buf, in stm32_usart_of_dma_rx_remove()
1694 stm32port->rx_dma_buf); in stm32_usart_of_dma_rx_remove()
1700 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_usart_of_dma_rx_probe()
1701 struct uart_port *port = &stm32port->port; in stm32_usart_of_dma_rx_probe()
1702 struct device *dev = &pdev->dev; in stm32_usart_of_dma_rx_probe()
1706 stm32port->rx_buf = dma_alloc_coherent(dev, RX_BUF_L, in stm32_usart_of_dma_rx_probe()
1707 &stm32port->rx_dma_buf, in stm32_usart_of_dma_rx_probe()
1709 if (!stm32port->rx_buf) in stm32_usart_of_dma_rx_probe()
1710 return -ENOMEM; in stm32_usart_of_dma_rx_probe()
1714 config.src_addr = port->mapbase + ofs->rdr; in stm32_usart_of_dma_rx_probe()
1717 ret = dmaengine_slave_config(stm32port->rx_ch, &config); in stm32_usart_of_dma_rx_probe()
1730 if (stm32port->tx_buf) in stm32_usart_of_dma_tx_remove()
1731 dma_free_coherent(&pdev->dev, TX_BUF_L, stm32port->tx_buf, in stm32_usart_of_dma_tx_remove()
1732 stm32port->tx_dma_buf); in stm32_usart_of_dma_tx_remove()
1738 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_usart_of_dma_tx_probe()
1739 struct uart_port *port = &stm32port->port; in stm32_usart_of_dma_tx_probe()
1740 struct device *dev = &pdev->dev; in stm32_usart_of_dma_tx_probe()
1744 stm32port->tx_buf = dma_alloc_coherent(dev, TX_BUF_L, in stm32_usart_of_dma_tx_probe()
1745 &stm32port->tx_dma_buf, in stm32_usart_of_dma_tx_probe()
1747 if (!stm32port->tx_buf) in stm32_usart_of_dma_tx_probe()
1748 return -ENOMEM; in stm32_usart_of_dma_tx_probe()
1752 config.dst_addr = port->mapbase + ofs->tdr; in stm32_usart_of_dma_tx_probe()
1755 ret = dmaengine_slave_config(stm32port->tx_ch, &config); in stm32_usart_of_dma_tx_probe()
1772 return -ENODEV; in stm32_usart_serial_probe()
1774 stm32port->info = of_device_get_match_data(&pdev->dev); in stm32_usart_serial_probe()
1775 if (!stm32port->info) in stm32_usart_serial_probe()
1776 return -EINVAL; in stm32_usart_serial_probe()
1778 stm32port->rx_ch = dma_request_chan(&pdev->dev, "rx"); in stm32_usart_serial_probe()
1779 if (PTR_ERR(stm32port->rx_ch) == -EPROBE_DEFER) in stm32_usart_serial_probe()
1780 return -EPROBE_DEFER; in stm32_usart_serial_probe()
1782 /* Fall back in interrupt mode for any non-deferral error */ in stm32_usart_serial_probe()
1783 if (IS_ERR(stm32port->rx_ch)) in stm32_usart_serial_probe()
1784 stm32port->rx_ch = NULL; in stm32_usart_serial_probe()
1786 stm32port->tx_ch = dma_request_chan(&pdev->dev, "tx"); in stm32_usart_serial_probe()
1787 if (PTR_ERR(stm32port->tx_ch) == -EPROBE_DEFER) { in stm32_usart_serial_probe()
1788 ret = -EPROBE_DEFER; in stm32_usart_serial_probe()
1791 /* Fall back in interrupt mode for any non-deferral error */ in stm32_usart_serial_probe()
1792 if (IS_ERR(stm32port->tx_ch)) in stm32_usart_serial_probe()
1793 stm32port->tx_ch = NULL; in stm32_usart_serial_probe()
1799 if (stm32port->wakeup_src) { in stm32_usart_serial_probe()
1800 device_set_wakeup_capable(&pdev->dev, true); in stm32_usart_serial_probe()
1801 ret = dev_pm_set_wake_irq(&pdev->dev, stm32port->port.irq); in stm32_usart_serial_probe()
1806 if (stm32port->rx_ch && stm32_usart_of_dma_rx_probe(stm32port, pdev)) { in stm32_usart_serial_probe()
1808 dma_release_channel(stm32port->rx_ch); in stm32_usart_serial_probe()
1809 stm32port->rx_ch = NULL; in stm32_usart_serial_probe()
1812 if (stm32port->tx_ch && stm32_usart_of_dma_tx_probe(stm32port, pdev)) { in stm32_usart_serial_probe()
1814 dma_release_channel(stm32port->tx_ch); in stm32_usart_serial_probe()
1815 stm32port->tx_ch = NULL; in stm32_usart_serial_probe()
1818 if (!stm32port->rx_ch) in stm32_usart_serial_probe()
1819 dev_info(&pdev->dev, "interrupt mode for rx (no dma)\n"); in stm32_usart_serial_probe()
1820 if (!stm32port->tx_ch) in stm32_usart_serial_probe()
1821 dev_info(&pdev->dev, "interrupt mode for tx (no dma)\n"); in stm32_usart_serial_probe()
1823 platform_set_drvdata(pdev, &stm32port->port); in stm32_usart_serial_probe()
1825 pm_runtime_get_noresume(&pdev->dev); in stm32_usart_serial_probe()
1826 pm_runtime_set_active(&pdev->dev); in stm32_usart_serial_probe()
1827 pm_runtime_enable(&pdev->dev); in stm32_usart_serial_probe()
1829 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port); in stm32_usart_serial_probe()
1833 pm_runtime_put_sync(&pdev->dev); in stm32_usart_serial_probe()
1838 pm_runtime_disable(&pdev->dev); in stm32_usart_serial_probe()
1839 pm_runtime_set_suspended(&pdev->dev); in stm32_usart_serial_probe()
1840 pm_runtime_put_noidle(&pdev->dev); in stm32_usart_serial_probe()
1842 if (stm32port->tx_ch) in stm32_usart_serial_probe()
1844 if (stm32port->rx_ch) in stm32_usart_serial_probe()
1847 if (stm32port->wakeup_src) in stm32_usart_serial_probe()
1848 dev_pm_clear_wake_irq(&pdev->dev); in stm32_usart_serial_probe()
1851 if (stm32port->wakeup_src) in stm32_usart_serial_probe()
1852 device_set_wakeup_capable(&pdev->dev, false); in stm32_usart_serial_probe()
1857 if (stm32port->tx_ch) in stm32_usart_serial_probe()
1858 dma_release_channel(stm32port->tx_ch); in stm32_usart_serial_probe()
1861 if (stm32port->rx_ch) in stm32_usart_serial_probe()
1862 dma_release_channel(stm32port->rx_ch); in stm32_usart_serial_probe()
1871 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_serial_remove()
1874 pm_runtime_get_sync(&pdev->dev); in stm32_usart_serial_remove()
1877 pm_runtime_disable(&pdev->dev); in stm32_usart_serial_remove()
1878 pm_runtime_set_suspended(&pdev->dev); in stm32_usart_serial_remove()
1879 pm_runtime_put_noidle(&pdev->dev); in stm32_usart_serial_remove()
1881 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_PEIE); in stm32_usart_serial_remove()
1883 if (stm32_port->tx_ch) { in stm32_usart_serial_remove()
1885 dma_release_channel(stm32_port->tx_ch); in stm32_usart_serial_remove()
1888 if (stm32_port->rx_ch) { in stm32_usart_serial_remove()
1890 dma_release_channel(stm32_port->rx_ch); in stm32_usart_serial_remove()
1893 cr3 = readl_relaxed(port->membase + ofs->cr3); in stm32_usart_serial_remove()
1898 writel_relaxed(cr3, port->membase + ofs->cr3); in stm32_usart_serial_remove()
1900 if (stm32_port->wakeup_src) { in stm32_usart_serial_remove()
1901 dev_pm_clear_wake_irq(&pdev->dev); in stm32_usart_serial_remove()
1902 device_init_wakeup(&pdev->dev, false); in stm32_usart_serial_remove()
1911 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_console_putchar()
1915 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, isr, in stm32_usart_console_putchar()
1919 dev_err(port->dev, "Error while sending data in UART TX : %d\n", ret); in stm32_usart_console_putchar()
1922 writel_relaxed(ch, port->membase + ofs->tdr); in stm32_usart_console_putchar()
1929 struct uart_port *port = &stm32_ports[co->index].port; in stm32_usart_console_write()
1931 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_console_write()
1932 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_console_write()
1943 old_cr1 = readl_relaxed(port->membase + ofs->cr1); in stm32_usart_console_write()
1945 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit); in stm32_usart_console_write()
1946 writel_relaxed(new_cr1, port->membase + ofs->cr1); in stm32_usart_console_write()
1951 writel_relaxed(old_cr1, port->membase + ofs->cr1); in stm32_usart_console_write()
1965 if (co->index >= STM32_MAX_PORTS) in stm32_usart_console_setup()
1966 return -ENODEV; in stm32_usart_console_setup()
1968 stm32port = &stm32_ports[co->index]; in stm32_usart_console_setup()
1976 if (stm32port->port.mapbase == 0 || !stm32port->port.membase) in stm32_usart_console_setup()
1977 return -ENXIO; in stm32_usart_console_setup()
1982 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow); in stm32_usart_console_setup()
1991 .index = -1,
2004 struct stm32_usart_info *info = port->private_data; in early_stm32_usart_console_putchar()
2006 while (!(readl_relaxed(port->membase + info->ofs.isr) & USART_SR_TXE)) in early_stm32_usart_console_putchar()
2009 writel_relaxed(ch, port->membase + info->ofs.tdr); in early_stm32_usart_console_putchar()
2014 struct earlycon_device *device = console->data; in early_stm32_serial_write()
2015 struct uart_port *port = &device->port; in early_stm32_serial_write()
2022 if (!(device->port.membase || device->port.iobase)) in early_stm32_h7_serial_setup()
2023 return -ENODEV; in early_stm32_h7_serial_setup()
2024 device->port.private_data = &stm32h7_info; in early_stm32_h7_serial_setup()
2025 device->con->write = early_stm32_serial_write; in early_stm32_h7_serial_setup()
2031 if (!(device->port.membase || device->port.iobase)) in early_stm32_f7_serial_setup()
2032 return -ENODEV; in early_stm32_f7_serial_setup()
2033 device->port.private_data = &stm32f7_info; in early_stm32_f7_serial_setup()
2034 device->con->write = early_stm32_serial_write; in early_stm32_f7_serial_setup()
2040 if (!(device->port.membase || device->port.iobase)) in early_stm32_f4_serial_setup()
2041 return -ENODEV; in early_stm32_f4_serial_setup()
2042 device->port.private_data = &stm32f4_info; in early_stm32_f4_serial_setup()
2043 device->con->write = early_stm32_serial_write; in early_stm32_f4_serial_setup()
2047 OF_EARLYCON_DECLARE(stm32, "st,stm32h7-uart", early_stm32_h7_serial_setup);
2048 OF_EARLYCON_DECLARE(stm32, "st,stm32f7-uart", early_stm32_f7_serial_setup);
2049 OF_EARLYCON_DECLARE(stm32, "st,stm32-uart", early_stm32_f4_serial_setup);
2065 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_serial_en_wakeup()
2066 struct tty_port *tport = &port->state->port; in stm32_usart_serial_en_wakeup()
2071 if (!stm32_port->wakeup_src || !tty_port_initialized(tport)) in stm32_usart_serial_en_wakeup()
2075 * Enable low-power wake-up and wake-up irq if argument is set to in stm32_usart_serial_en_wakeup()
2076 * "enable", disable low-power wake-up and wake-up irq otherwise in stm32_usart_serial_en_wakeup()
2079 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM); in stm32_usart_serial_en_wakeup()
2080 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_WUFIE); in stm32_usart_serial_en_wakeup()
2081 mctrl_gpio_enable_irq_wake(stm32_port->gpios); in stm32_usart_serial_en_wakeup()
2085 * entering low-power mode and re-enabled when exiting from in stm32_usart_serial_en_wakeup()
2086 * low-power mode. in stm32_usart_serial_en_wakeup()
2088 if (stm32_port->rx_ch) { in stm32_usart_serial_en_wakeup()
2102 if (stm32_port->rx_ch) { in stm32_usart_serial_en_wakeup()
2107 mctrl_gpio_disable_irq_wake(stm32_port->gpios); in stm32_usart_serial_en_wakeup()
2108 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM); in stm32_usart_serial_en_wakeup()
2109 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE); in stm32_usart_serial_en_wakeup()
2166 clk_disable_unprepare(stm32port->clk); in stm32_usart_runtime_suspend()
2177 return clk_prepare_enable(stm32port->clk); in stm32_usart_runtime_resume()