Lines Matching +full:fifo +full:- +full:watermark +full:- +full:aligned
1 // SPDX-License-Identifier: GPL-2.0
5 * High-speed serial driver for NVIDIA Tegra SoCs
7 * Copyright (c) 2012-2019, NVIDIA CORPORATION. All rights reserved.
16 #include <linux/dma-mapping.h>
56 * Tx fifo trigger level setting in tegra uart is in
79 * @tx_fifo_full_status: Status flag available for checking tx fifo full.
80 * @allow_txfifo_reset_fifo_mode: allow_tx fifo reset with fifo mode or not.
83 * @fifo_mode_enable_status: Is FIFO mode enabled?
159 return readl(tup->uport.membase + (reg << tup->uport.regshift)); in tegra_uart_read()
165 writel(val, tup->uport.membase + (reg << tup->uport.regshift)); in tegra_uart_write()
178 * RI - Ring detector is active in tegra_uart_get_mctrl()
179 * CD/DCD/CAR - Carrier detect is always active. For some reason in tegra_uart_get_mctrl()
181 * DSR - Data Set ready is active as the hardware doesn't support it. in tegra_uart_get_mctrl()
183 * CTS - Clear to send. Always set to active, as the hardware handles in tegra_uart_get_mctrl()
186 if (tup->enable_modem_interrupt) in tegra_uart_get_mctrl()
195 mcr = tup->mcr_shadow; in set_rts()
200 if (mcr != tup->mcr_shadow) { in set_rts()
202 tup->mcr_shadow = mcr; in set_rts()
210 mcr = tup->mcr_shadow; in set_dtr()
215 if (mcr != tup->mcr_shadow) { in set_dtr()
217 tup->mcr_shadow = mcr; in set_dtr()
223 unsigned long mcr = tup->mcr_shadow; in set_loopbk()
230 if (mcr != tup->mcr_shadow) { in set_loopbk()
232 tup->mcr_shadow = mcr; in set_loopbk()
241 tup->rts_active = !!(mctrl & TIOCM_RTS); in tegra_uart_set_mctrl()
242 set_rts(tup, tup->rts_active); in tegra_uart_set_mctrl()
256 lcr = tup->lcr_shadow; in tegra_uart_break_ctl()
262 tup->lcr_shadow = lcr; in tegra_uart_break_ctl()
277 if (tup->current_baud) in tegra_uart_wait_cycle_time()
278 udelay(DIV_ROUND_UP(cycles * 1000000, tup->current_baud * 16)); in tegra_uart_wait_cycle_time()
281 /* Wait for a symbol-time. */
285 if (tup->current_baud) in tegra_uart_wait_sym_time()
286 udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000, in tegra_uart_wait_sym_time()
287 tup->current_baud)); in tegra_uart_wait_sym_time()
300 } while (--tmout); in tegra_uart_wait_fifo_mode_enabled()
302 return -ETIMEDOUT; in tegra_uart_wait_fifo_mode_enabled()
307 unsigned long fcr = tup->fcr_shadow; in tegra_uart_fifo_reset()
310 if (tup->rts_active) in tegra_uart_fifo_reset()
313 if (tup->cdata->allow_txfifo_reset_fifo_mode) { in tegra_uart_fifo_reset()
324 if (tup->cdata->fifo_mode_enable_status) in tegra_uart_fifo_reset()
343 } while (--tmout); in tegra_uart_fifo_reset()
345 if (tup->rts_active) in tegra_uart_fifo_reset()
354 for (i = 0; i < tup->n_adjustable_baud_rates; ++i) { in tegra_get_tolerance_rate()
355 if (baud >= tup->baud_tolerance[i].lower_range_baud && in tegra_get_tolerance_rate()
356 baud <= tup->baud_tolerance[i].upper_range_baud) in tegra_get_tolerance_rate()
358 tup->baud_tolerance[i].tolerance) / 10000); in tegra_get_tolerance_rate()
368 diff = ((long)(tup->configured_rate - tup->required_rate) * 10000) in tegra_check_rate_in_range()
369 / tup->required_rate; in tegra_check_rate_in_range()
370 if (diff < (tup->cdata->error_tolerance_low_range * 100) || in tegra_check_rate_in_range()
371 diff > (tup->cdata->error_tolerance_high_range * 100)) { in tegra_check_rate_in_range()
372 dev_err(tup->uport.dev, in tegra_check_rate_in_range()
374 return -EIO; in tegra_check_rate_in_range()
388 if (tup->current_baud == baud) in tegra_set_baudrate()
391 if (tup->cdata->support_clk_src_div) { in tegra_set_baudrate()
393 tup->required_rate = rate; in tegra_set_baudrate()
395 if (tup->n_adjustable_baud_rates) in tegra_set_baudrate()
398 ret = clk_set_rate(tup->uart_clk, rate); in tegra_set_baudrate()
400 dev_err(tup->uport.dev, in tegra_set_baudrate()
404 tup->configured_rate = clk_get_rate(tup->uart_clk); in tegra_set_baudrate()
410 rate = clk_get_rate(tup->uart_clk); in tegra_set_baudrate()
414 uart_port_lock_irqsave(&tup->uport, &flags); in tegra_set_baudrate()
415 lcr = tup->lcr_shadow; in tegra_set_baudrate()
427 uart_port_unlock_irqrestore(&tup->uport, flags); in tegra_set_baudrate()
429 tup->current_baud = baud; in tegra_set_baudrate()
445 tup->uport.icount.overrun++; in tegra_uart_decode_rx_error()
446 dev_dbg(tup->uport.dev, "Got overrun errors\n"); in tegra_uart_decode_rx_error()
450 tup->uport.icount.parity++; in tegra_uart_decode_rx_error()
451 dev_dbg(tup->uport.dev, "Got Parity errors\n"); in tegra_uart_decode_rx_error()
454 tup->uport.icount.frame++; in tegra_uart_decode_rx_error()
455 dev_dbg(tup->uport.dev, "Got frame errors\n"); in tegra_uart_decode_rx_error()
459 * If FIFO read error without any data, reset Rx FIFO in tegra_uart_decode_rx_error()
463 if (tup->uport.ignore_status_mask & UART_LSR_BI) in tegra_uart_decode_rx_error()
466 tup->uport.icount.brk++; in tegra_uart_decode_rx_error()
467 dev_dbg(tup->uport.dev, "Got Break\n"); in tegra_uart_decode_rx_error()
469 uart_insert_char(&tup->uport, lsr, UART_LSR_OE, 0, flag); in tegra_uart_decode_rx_error()
491 if (tup->cdata->tx_fifo_full_status) { in tegra_uart_fill_tx_fifo()
496 if (WARN_ON_ONCE(!uart_fifo_get(&tup->uport, &ch))) in tegra_uart_fill_tx_fifo()
508 tup->tx_in_progress = TEGRA_UART_TX_PIO; in tegra_uart_start_pio_tx()
509 tup->tx_bytes = bytes; in tegra_uart_start_pio_tx()
510 tup->ier_shadow |= UART_IER_THRI; in tegra_uart_start_pio_tx()
511 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_start_pio_tx()
517 struct tty_port *tport = &tup->uport.state->port; in tegra_uart_tx_dma_complete()
522 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state); in tegra_uart_tx_dma_complete()
523 count = tup->tx_bytes_requested - state.residue; in tegra_uart_tx_dma_complete()
524 async_tx_ack(tup->tx_dma_desc); in tegra_uart_tx_dma_complete()
525 uart_port_lock_irqsave(&tup->uport, &flags); in tegra_uart_tx_dma_complete()
526 uart_xmit_advance(&tup->uport, count); in tegra_uart_tx_dma_complete()
527 tup->tx_in_progress = 0; in tegra_uart_tx_dma_complete()
528 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in tegra_uart_tx_dma_complete()
529 uart_write_wakeup(&tup->uport); in tegra_uart_tx_dma_complete()
531 uart_port_unlock_irqrestore(&tup->uport, flags); in tegra_uart_tx_dma_complete()
537 struct tty_port *tport = &tup->uport.state->port; in tegra_uart_start_tx_dma()
541 tup->tx_bytes = count & ~(0xF); in tegra_uart_start_tx_dma()
542 WARN_ON_ONCE(kfifo_out_linear(&tport->xmit_fifo, &tail, in tegra_uart_start_tx_dma()
544 tx_phys_addr = tup->tx_dma_buf_phys + tail; in tegra_uart_start_tx_dma()
546 dma_sync_single_for_device(tup->uport.dev, tx_phys_addr, in tegra_uart_start_tx_dma()
547 tup->tx_bytes, DMA_TO_DEVICE); in tegra_uart_start_tx_dma()
549 tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan, in tegra_uart_start_tx_dma()
550 tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV, in tegra_uart_start_tx_dma()
552 if (!tup->tx_dma_desc) { in tegra_uart_start_tx_dma()
553 dev_err(tup->uport.dev, "Not able to get desc for Tx\n"); in tegra_uart_start_tx_dma()
554 return -EIO; in tegra_uart_start_tx_dma()
557 tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete; in tegra_uart_start_tx_dma()
558 tup->tx_dma_desc->callback_param = tup; in tegra_uart_start_tx_dma()
559 tup->tx_in_progress = TEGRA_UART_TX_DMA; in tegra_uart_start_tx_dma()
560 tup->tx_bytes_requested = tup->tx_bytes; in tegra_uart_start_tx_dma()
561 tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc); in tegra_uart_start_tx_dma()
562 dma_async_issue_pending(tup->tx_dma_chan); in tegra_uart_start_tx_dma()
568 struct tty_port *tport = &tup->uport.state->port; in tegra_uart_start_next_tx()
573 if (!tup->current_baud) in tegra_uart_start_next_tx()
576 count = kfifo_out_linear_ptr(&tport->xmit_fifo, &tail_ptr, in tegra_uart_start_next_tx()
583 if (tup->use_tx_pio || count < TEGRA_UART_MIN_DMA) in tegra_uart_start_next_tx()
591 /* Called by serial core driver with u->lock taken. */
595 struct tty_port *tport = &u->state->port; in tegra_uart_start_tx()
597 if (!kfifo_is_empty(&tport->xmit_fifo) && !tup->tx_in_progress) in tegra_uart_start_tx()
608 if (!tup->tx_in_progress) { in tegra_uart_tx_empty()
623 if (tup->tx_in_progress != TEGRA_UART_TX_DMA) in tegra_uart_stop_tx()
626 dmaengine_pause(tup->tx_dma_chan); in tegra_uart_stop_tx()
627 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state); in tegra_uart_stop_tx()
628 dmaengine_terminate_all(tup->tx_dma_chan); in tegra_uart_stop_tx()
629 count = tup->tx_bytes_requested - state.residue; in tegra_uart_stop_tx()
630 async_tx_ack(tup->tx_dma_desc); in tegra_uart_stop_tx()
631 uart_xmit_advance(&tup->uport, count); in tegra_uart_stop_tx()
632 tup->tx_in_progress = 0; in tegra_uart_stop_tx()
637 struct tty_port *tport = &tup->uport.state->port; in tegra_uart_handle_tx_pio()
639 tegra_uart_fill_tx_fifo(tup, tup->tx_bytes); in tegra_uart_handle_tx_pio()
640 tup->tx_in_progress = 0; in tegra_uart_handle_tx_pio()
641 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in tegra_uart_handle_tx_pio()
642 uart_write_wakeup(&tup->uport); in tegra_uart_handle_tx_pio()
662 tup->uport.icount.rx++; in tegra_uart_handle_rx_pio()
664 if (uart_handle_sysrq_char(&tup->uport, ch)) in tegra_uart_handle_rx_pio()
667 if (tup->uport.ignore_status_mask & UART_LSR_DR) in tegra_uart_handle_rx_pio()
684 tup->uport.icount.rx += count; in tegra_uart_copy_rx_to_tty()
686 if (tup->uport.ignore_status_mask & UART_LSR_DR) in tegra_uart_copy_rx_to_tty()
689 dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys, in tegra_uart_copy_rx_to_tty()
692 ((unsigned char *)(tup->rx_dma_buf_virt)), count); in tegra_uart_copy_rx_to_tty()
695 dev_err(tup->uport.dev, "RxData copy to tty layer failed\n"); in tegra_uart_copy_rx_to_tty()
697 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys, in tegra_uart_copy_rx_to_tty()
703 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port); in do_handle_rx_pio()
704 struct tty_port *port = &tup->uport.state->port; in do_handle_rx_pio()
716 struct tty_port *port = &tup->uport.state->port; in tegra_uart_rx_buffer_push()
719 async_tx_ack(tup->rx_dma_desc); in tegra_uart_rx_buffer_push()
720 count = tup->rx_bytes_requested - residue; in tegra_uart_rx_buffer_push()
731 struct uart_port *u = &tup->uport; in tegra_uart_rx_dma_complete()
738 status = dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); in tegra_uart_rx_dma_complete()
741 dev_dbg(tup->uport.dev, "RX DMA is in progress\n"); in tegra_uart_rx_dma_complete()
746 if (tup->rts_active) in tegra_uart_rx_dma_complete()
749 tup->rx_dma_active = false; in tegra_uart_rx_dma_complete()
754 if (tup->rts_active) in tegra_uart_rx_dma_complete()
765 if (!tup->rx_dma_active) { in tegra_uart_terminate_rx_dma()
770 dmaengine_pause(tup->rx_dma_chan); in tegra_uart_terminate_rx_dma()
771 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); in tegra_uart_terminate_rx_dma()
772 dmaengine_terminate_all(tup->rx_dma_chan); in tegra_uart_terminate_rx_dma()
775 tup->rx_dma_active = false; in tegra_uart_terminate_rx_dma()
781 if (tup->rts_active) in tegra_uart_handle_rx_dma()
786 if (tup->rts_active) in tegra_uart_handle_rx_dma()
794 if (tup->rx_dma_active) in tegra_uart_start_rx_dma()
797 tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan, in tegra_uart_start_rx_dma()
798 tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM, in tegra_uart_start_rx_dma()
800 if (!tup->rx_dma_desc) { in tegra_uart_start_rx_dma()
801 dev_err(tup->uport.dev, "Not able to get desc for Rx\n"); in tegra_uart_start_rx_dma()
802 return -EIO; in tegra_uart_start_rx_dma()
805 tup->rx_dma_active = true; in tegra_uart_start_rx_dma()
806 tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete; in tegra_uart_start_rx_dma()
807 tup->rx_dma_desc->callback_param = tup; in tegra_uart_start_rx_dma()
808 tup->rx_bytes_requested = count; in tegra_uart_start_rx_dma()
809 tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc); in tegra_uart_start_rx_dma()
810 dma_async_issue_pending(tup->rx_dma_chan); in tegra_uart_start_rx_dma()
824 tup->uport.icount.rng++; in tegra_uart_handle_modem_signal_change()
826 tup->uport.icount.dsr++; in tegra_uart_handle_modem_signal_change()
829 uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD); in tegra_uart_handle_modem_signal_change()
832 uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS); in tegra_uart_handle_modem_signal_change()
838 struct uart_port *u = &tup->uport; in tegra_uart_isr()
849 if (!tup->use_rx_pio && is_rx_int) { in tegra_uart_isr()
851 if (tup->rx_in_progress) { in tegra_uart_isr()
852 ier = tup->ier_shadow; in tegra_uart_isr()
855 tup->ier_shadow = ier; in tegra_uart_isr()
871 tup->ier_shadow &= ~UART_IER_THRI; in tegra_uart_isr()
872 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_isr()
878 if (!tup->use_rx_pio) { in tegra_uart_isr()
879 is_rx_int = tup->rx_in_progress; in tegra_uart_isr()
881 ier = tup->ier_shadow; in tegra_uart_isr()
884 tup->ier_shadow = ier; in tegra_uart_isr()
890 if (!tup->use_rx_pio) { in tegra_uart_isr()
891 is_rx_start = tup->rx_in_progress; in tegra_uart_isr()
892 tup->ier_shadow &= ~UART_IER_RDI; in tegra_uart_isr()
893 tegra_uart_write(tup, tup->ier_shadow, in tegra_uart_isr()
915 struct tty_port *port = &tup->uport.state->port; in tegra_uart_stop_rx()
918 if (tup->rts_active) in tegra_uart_stop_rx()
921 if (!tup->rx_in_progress) in tegra_uart_stop_rx()
926 ier = tup->ier_shadow; in tegra_uart_stop_rx()
929 tup->ier_shadow = ier; in tegra_uart_stop_rx()
931 tup->rx_in_progress = 0; in tegra_uart_stop_rx()
933 if (!tup->use_rx_pio) in tegra_uart_stop_rx()
942 unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud); in tegra_uart_hw_deinit()
943 unsigned long fifo_empty_time = tup->uport.fifosize * char_time; in tegra_uart_hw_deinit()
957 dev_err(tup->uport.dev, in tegra_uart_hw_deinit()
958 "Tx Fifo not empty, CTS disabled, waiting\n"); in tegra_uart_hw_deinit()
960 /* Wait for Tx fifo to be empty */ in tegra_uart_hw_deinit()
964 fifo_empty_time -= wait_time; in tegra_uart_hw_deinit()
970 dev_err(tup->uport.dev, in tegra_uart_hw_deinit()
978 uart_port_lock_irqsave(&tup->uport, &flags); in tegra_uart_hw_deinit()
981 tup->current_baud = 0; in tegra_uart_hw_deinit()
982 uart_port_unlock_irqrestore(&tup->uport, flags); in tegra_uart_hw_deinit()
984 tup->rx_in_progress = 0; in tegra_uart_hw_deinit()
985 tup->tx_in_progress = 0; in tegra_uart_hw_deinit()
987 if (!tup->use_rx_pio) in tegra_uart_hw_deinit()
989 if (!tup->use_tx_pio) in tegra_uart_hw_deinit()
992 clk_disable_unprepare(tup->uart_clk); in tegra_uart_hw_deinit()
999 tup->fcr_shadow = 0; in tegra_uart_hw_init()
1000 tup->mcr_shadow = 0; in tegra_uart_hw_init()
1001 tup->lcr_shadow = 0; in tegra_uart_hw_init()
1002 tup->ier_shadow = 0; in tegra_uart_hw_init()
1003 tup->current_baud = 0; in tegra_uart_hw_init()
1005 ret = clk_prepare_enable(tup->uart_clk); in tegra_uart_hw_init()
1007 dev_err(tup->uport.dev, "could not enable clk\n"); in tegra_uart_hw_init()
1012 reset_control_assert(tup->rst); in tegra_uart_hw_init()
1014 reset_control_deassert(tup->rst); in tegra_uart_hw_init()
1016 tup->rx_in_progress = 0; in tegra_uart_hw_init()
1017 tup->tx_in_progress = 0; in tegra_uart_hw_init()
1026 * interrupt is received. Rx high watermark is set to 4. in tegra_uart_hw_init()
1029 * interrupt the CPU when the number of entries in the FIFO reaches the in tegra_uart_hw_init()
1030 * low watermark. Tx low watermark is set to 16 bytes. in tegra_uart_hw_init()
1037 tup->fcr_shadow = UART_FCR_ENABLE_FIFO; in tegra_uart_hw_init()
1039 if (tup->use_rx_pio) { in tegra_uart_hw_init()
1040 tup->fcr_shadow |= UART_FCR_R_TRIG_11; in tegra_uart_hw_init()
1042 if (tup->cdata->max_dma_burst_bytes == 8) in tegra_uart_hw_init()
1043 tup->fcr_shadow |= UART_FCR_R_TRIG_10; in tegra_uart_hw_init()
1045 tup->fcr_shadow |= UART_FCR_R_TRIG_01; in tegra_uart_hw_init()
1048 tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B; in tegra_uart_hw_init()
1049 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); in tegra_uart_hw_init()
1054 if (tup->cdata->fifo_mode_enable_status) { in tegra_uart_hw_init()
1057 clk_disable_unprepare(tup->uart_clk); in tegra_uart_hw_init()
1058 dev_err(tup->uport.dev, in tegra_uart_hw_init()
1059 "Failed to enable FIFO mode: %d\n", ret); in tegra_uart_hw_init()
1066 * periods after enabling the TX fifo, otherwise data could in tegra_uart_hw_init()
1079 clk_disable_unprepare(tup->uart_clk); in tegra_uart_hw_init()
1080 dev_err(tup->uport.dev, "Failed to set baud rate\n"); in tegra_uart_hw_init()
1083 if (!tup->use_rx_pio) { in tegra_uart_hw_init()
1084 tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR; in tegra_uart_hw_init()
1085 tup->fcr_shadow |= UART_FCR_DMA_SELECT; in tegra_uart_hw_init()
1086 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); in tegra_uart_hw_init()
1088 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); in tegra_uart_hw_init()
1090 tup->rx_in_progress = 1; in tegra_uart_hw_init()
1096 * EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when in tegra_uart_hw_init()
1097 * the DATA is sitting in the FIFO and couldn't be transferred to the in tegra_uart_hw_init()
1102 * For pauses in the data which is not aligned to 4 bytes, we get in tegra_uart_hw_init()
1103 * both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first in tegra_uart_hw_init()
1106 tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | UART_IER_RDI; in tegra_uart_hw_init()
1112 if (!tup->use_rx_pio) in tegra_uart_hw_init()
1113 tup->ier_shadow |= TEGRA_UART_IER_EORD; in tegra_uart_hw_init()
1115 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_hw_init()
1123 dmaengine_terminate_all(tup->rx_dma_chan); in tegra_uart_dma_channel_free()
1124 dma_release_channel(tup->rx_dma_chan); in tegra_uart_dma_channel_free()
1125 dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE, in tegra_uart_dma_channel_free()
1126 tup->rx_dma_buf_virt, tup->rx_dma_buf_phys); in tegra_uart_dma_channel_free()
1127 tup->rx_dma_chan = NULL; in tegra_uart_dma_channel_free()
1128 tup->rx_dma_buf_phys = 0; in tegra_uart_dma_channel_free()
1129 tup->rx_dma_buf_virt = NULL; in tegra_uart_dma_channel_free()
1131 dmaengine_terminate_all(tup->tx_dma_chan); in tegra_uart_dma_channel_free()
1132 dma_release_channel(tup->tx_dma_chan); in tegra_uart_dma_channel_free()
1133 dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys, in tegra_uart_dma_channel_free()
1135 tup->tx_dma_chan = NULL; in tegra_uart_dma_channel_free()
1136 tup->tx_dma_buf_phys = 0; in tegra_uart_dma_channel_free()
1137 tup->tx_dma_buf_virt = NULL; in tegra_uart_dma_channel_free()
1150 dma_chan = dma_request_chan(tup->uport.dev, dma_to_memory ? "rx" : "tx"); in tegra_uart_dma_channel_allocate()
1153 dev_err(tup->uport.dev, in tegra_uart_dma_channel_allocate()
1159 dma_buf = dma_alloc_coherent(tup->uport.dev, in tegra_uart_dma_channel_allocate()
1163 dev_err(tup->uport.dev, in tegra_uart_dma_channel_allocate()
1166 return -ENOMEM; in tegra_uart_dma_channel_allocate()
1168 dma_sync_single_for_device(tup->uport.dev, dma_phys, in tegra_uart_dma_channel_allocate()
1171 dma_sconfig.src_addr = tup->uport.mapbase; in tegra_uart_dma_channel_allocate()
1173 dma_sconfig.src_maxburst = tup->cdata->max_dma_burst_bytes; in tegra_uart_dma_channel_allocate()
1174 tup->rx_dma_chan = dma_chan; in tegra_uart_dma_channel_allocate()
1175 tup->rx_dma_buf_virt = dma_buf; in tegra_uart_dma_channel_allocate()
1176 tup->rx_dma_buf_phys = dma_phys; in tegra_uart_dma_channel_allocate()
1178 dma_buf = tup->uport.state->port.xmit_buf; in tegra_uart_dma_channel_allocate()
1179 dma_phys = dma_map_single(tup->uport.dev, in tegra_uart_dma_channel_allocate()
1181 if (dma_mapping_error(tup->uport.dev, dma_phys)) { in tegra_uart_dma_channel_allocate()
1182 dev_err(tup->uport.dev, "dma_map_single tx failed\n"); in tegra_uart_dma_channel_allocate()
1184 return -ENOMEM; in tegra_uart_dma_channel_allocate()
1186 dma_sconfig.dst_addr = tup->uport.mapbase; in tegra_uart_dma_channel_allocate()
1189 tup->tx_dma_chan = dma_chan; in tegra_uart_dma_channel_allocate()
1190 tup->tx_dma_buf_virt = dma_buf; in tegra_uart_dma_channel_allocate()
1191 tup->tx_dma_buf_phys = dma_phys; in tegra_uart_dma_channel_allocate()
1196 dev_err(tup->uport.dev, in tegra_uart_dma_channel_allocate()
1210 if (!tup->use_tx_pio) { in tegra_uart_startup()
1213 dev_err(u->dev, "Tx Dma allocation failed, err = %d\n", in tegra_uart_startup()
1219 if (!tup->use_rx_pio) { in tegra_uart_startup()
1222 dev_err(u->dev, "Rx Dma allocation failed, err = %d\n", in tegra_uart_startup()
1230 dev_err(u->dev, "Uart HW init failed, err = %d\n", ret); in tegra_uart_startup()
1234 ret = request_irq(u->irq, tegra_uart_isr, 0, in tegra_uart_startup()
1235 dev_name(u->dev), tup); in tegra_uart_startup()
1237 dev_err(u->dev, "Failed to register ISR for IRQ %d\n", u->irq); in tegra_uart_startup()
1243 /* tup->uart_clk is already enabled in tegra_uart_hw_init */ in tegra_uart_startup()
1244 clk_disable_unprepare(tup->uart_clk); in tegra_uart_startup()
1246 if (!tup->use_rx_pio) in tegra_uart_startup()
1249 if (!tup->use_tx_pio) in tegra_uart_startup()
1262 tup->tx_bytes = 0; in tegra_uart_flush_buffer()
1263 if (tup->tx_dma_chan) in tegra_uart_flush_buffer()
1264 dmaengine_terminate_all(tup->tx_dma_chan); in tegra_uart_flush_buffer()
1272 free_irq(u->irq, tup); in tegra_uart_shutdown()
1279 if (tup->enable_modem_interrupt) { in tegra_uart_enable_ms()
1280 tup->ier_shadow |= UART_IER_MSI; in tegra_uart_enable_ms()
1281 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_enable_ms()
1294 struct clk *parent_clk = clk_get_parent(tup->uart_clk); in tegra_uart_set_termios()
1296 int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF; in tegra_uart_set_termios()
1303 if (tup->rts_active) in tegra_uart_set_termios()
1307 tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER); in tegra_uart_set_termios()
1313 lcr = tup->lcr_shadow; in tegra_uart_set_termios()
1317 termios->c_cflag &= ~CMSPAR; in tegra_uart_set_termios()
1319 if ((termios->c_cflag & PARENB) == PARENB) { in tegra_uart_set_termios()
1320 if (termios->c_cflag & PARODD) { in tegra_uart_set_termios()
1331 char_bits = tty_get_char_size(termios->c_cflag); in tegra_uart_set_termios()
1336 if (termios->c_cflag & CSTOPB) in tegra_uart_set_termios()
1342 tup->lcr_shadow = lcr; in tegra_uart_set_termios()
1343 tup->symb_bit = tty_get_frame_size(termios->c_cflag); in tegra_uart_set_termios()
1352 dev_err(tup->uport.dev, "Failed to set baud rate\n"); in tegra_uart_set_termios()
1360 if (termios->c_cflag & CRTSCTS) { in tegra_uart_set_termios()
1361 tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN; in tegra_uart_set_termios()
1362 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN; in tegra_uart_set_termios()
1363 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR); in tegra_uart_set_termios()
1365 if (tup->rts_active) in tegra_uart_set_termios()
1368 tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN; in tegra_uart_set_termios()
1369 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN; in tegra_uart_set_termios()
1370 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR); in tegra_uart_set_termios()
1374 uart_update_timeout(u, termios->c_cflag, baud); in tegra_uart_set_termios()
1379 /* Re-enable interrupt */ in tegra_uart_set_termios()
1380 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_set_termios()
1383 tup->uport.ignore_status_mask = 0; in tegra_uart_set_termios()
1385 if ((termios->c_cflag & CREAD) == 0) in tegra_uart_set_termios()
1386 tup->uport.ignore_status_mask |= UART_LSR_DR; in tegra_uart_set_termios()
1387 if (termios->c_iflag & IGNBRK) in tegra_uart_set_termios()
1388 tup->uport.ignore_status_mask |= UART_LSR_BI; in tegra_uart_set_termios()
1427 struct device_node *np = pdev->dev.of_node; in tegra_uart_parse_dt()
1437 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", port); in tegra_uart_parse_dt()
1440 tup->uport.line = port; in tegra_uart_parse_dt()
1442 tup->enable_modem_interrupt = of_property_read_bool(np, in tegra_uart_parse_dt()
1443 "nvidia,enable-modem-interrupt"); in tegra_uart_parse_dt()
1445 index = of_property_match_string(np, "dma-names", "rx"); in tegra_uart_parse_dt()
1447 tup->use_rx_pio = true; in tegra_uart_parse_dt()
1448 dev_info(&pdev->dev, "RX in PIO mode\n"); in tegra_uart_parse_dt()
1450 index = of_property_match_string(np, "dma-names", "tx"); in tegra_uart_parse_dt()
1452 tup->use_tx_pio = true; in tegra_uart_parse_dt()
1453 dev_info(&pdev->dev, "TX in PIO mode\n"); in tegra_uart_parse_dt()
1456 n_entries = of_property_count_u32_elems(np, "nvidia,adjust-baud-rates"); in tegra_uart_parse_dt()
1458 tup->n_adjustable_baud_rates = n_entries / 3; in tegra_uart_parse_dt()
1459 tup->baud_tolerance = in tegra_uart_parse_dt()
1460 devm_kzalloc(&pdev->dev, (tup->n_adjustable_baud_rates) * in tegra_uart_parse_dt()
1461 sizeof(*tup->baud_tolerance), GFP_KERNEL); in tegra_uart_parse_dt()
1462 if (!tup->baud_tolerance) in tegra_uart_parse_dt()
1463 return -ENOMEM; in tegra_uart_parse_dt()
1468 "nvidia,adjust-baud-rates", in tegra_uart_parse_dt()
1471 tup->baud_tolerance[index].lower_range_baud = in tegra_uart_parse_dt()
1475 "nvidia,adjust-baud-rates", in tegra_uart_parse_dt()
1478 tup->baud_tolerance[index].upper_range_baud = in tegra_uart_parse_dt()
1482 "nvidia,adjust-baud-rates", in tegra_uart_parse_dt()
1485 tup->baud_tolerance[index].tolerance = in tegra_uart_parse_dt()
1489 tup->n_adjustable_baud_rates = 0; in tegra_uart_parse_dt()
1502 .error_tolerance_low_range = -4,
1513 .error_tolerance_low_range = -4,
1535 .error_tolerance_low_range = -2,
1541 .compatible = "nvidia,tegra30-hsuart",
1544 .compatible = "nvidia,tegra20-hsuart",
1547 .compatible = "nvidia,tegra186-hsuart",
1550 .compatible = "nvidia,tegra194-hsuart",
1565 cdata = of_device_get_match_data(&pdev->dev); in tegra_uart_probe()
1567 dev_err(&pdev->dev, "Error: No device match found\n"); in tegra_uart_probe()
1568 return -ENODEV; in tegra_uart_probe()
1571 tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL); in tegra_uart_probe()
1573 dev_err(&pdev->dev, "Failed to allocate memory for tup\n"); in tegra_uart_probe()
1574 return -ENOMEM; in tegra_uart_probe()
1581 u = &tup->uport; in tegra_uart_probe()
1582 u->dev = &pdev->dev; in tegra_uart_probe()
1583 u->ops = &tegra_uart_ops; in tegra_uart_probe()
1584 u->type = PORT_TEGRA; in tegra_uart_probe()
1585 u->fifosize = 32; in tegra_uart_probe()
1586 tup->cdata = cdata; in tegra_uart_probe()
1590 u->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &resource); in tegra_uart_probe()
1591 if (IS_ERR(u->membase)) in tegra_uart_probe()
1592 return PTR_ERR(u->membase); in tegra_uart_probe()
1593 u->mapbase = resource->start; in tegra_uart_probe()
1595 tup->uart_clk = devm_clk_get(&pdev->dev, NULL); in tegra_uart_probe()
1596 if (IS_ERR(tup->uart_clk)) in tegra_uart_probe()
1597 return dev_err_probe(&pdev->dev, PTR_ERR(tup->uart_clk), "Couldn't get the clock"); in tegra_uart_probe()
1599 tup->rst = devm_reset_control_get_exclusive(&pdev->dev, "serial"); in tegra_uart_probe()
1600 if (IS_ERR(tup->rst)) { in tegra_uart_probe()
1601 dev_err(&pdev->dev, "Couldn't get the reset\n"); in tegra_uart_probe()
1602 return PTR_ERR(tup->rst); in tegra_uart_probe()
1605 u->iotype = UPIO_MEM32; in tegra_uart_probe()
1609 u->irq = ret; in tegra_uart_probe()
1610 u->regshift = 2; in tegra_uart_probe()
1613 dev_err(&pdev->dev, "Failed to add uart port, err %d\n", ret); in tegra_uart_probe()
1622 struct uart_port *u = &tup->uport; in tegra_uart_remove()
1631 struct uart_port *u = &tup->uport; in tegra_uart_suspend()
1639 struct uart_port *u = &tup->uport; in tegra_uart_resume()
1653 .name = "serial-tegra",
1671 cdata = match->data; in tegra_uart_init()
1673 tegra_uart_driver.nr = cdata->uart_max_port; in tegra_uart_init()
1701 MODULE_ALIAS("platform:serial-tegra");