1 // SPDX-License-Identifier: GPL-2.0
12  *   rocketport_infinity_express-linux-1.20.tar.gz
13  *     Copyright (C) 2004-2011 Comtrol, Inc.
44 #define ALL_PORTS_MASK			(BIT(PORTS_PER_ASIC) - 1)
75 /* port registers */
79 #define RP2_DATA_BYTE_ERR_PARITY_m	BIT(8)
84 /* This lets uart_insert_char() drop bytes received on a !CREAD port */
146 #define RP2_UART_CTL_DATABITS_s		8
179 	struct uart_port		port;  member
200 #define RP_CAP(ports, smpte) (((ports) << 8) | ((smpte) << 0))
205 	*ports = id->driver_data >> 8;  in rp2_decode_cap()
206 	*smpte = id->driver_data & 0xff;  in rp2_decode_cap()
214 	int ret = -ENOSPC;  in rp2_alloc_ports()
227 static inline struct rp2_uart_port *port_to_up(struct uart_port *port)  in port_to_up()  argument
229 	return container_of(port, struct rp2_uart_port, port);  in port_to_up()
235 	u32 tmp = readl(up->base + reg);  in rp2_rmw()
238 	writel(tmp, up->base + reg);  in rp2_rmw()
256 	spin_lock_irqsave(&up->card->card_lock, flags);  in rp2_mask_ch_irq()
258 	irq_mask = readl(up->asic_base + RP2_CH_IRQ_MASK);  in rp2_mask_ch_irq()
263 	writel(irq_mask, up->asic_base + RP2_CH_IRQ_MASK);  in rp2_mask_ch_irq()
265 	spin_unlock_irqrestore(&up->card->card_lock, flags);  in rp2_mask_ch_irq()
268 static unsigned int rp2_uart_tx_empty(struct uart_port *port)  in rp2_uart_tx_empty()  argument
270 	struct rp2_uart_port *up = port_to_up(port);  in rp2_uart_tx_empty()
278 	uart_port_lock_irqsave(&up->port, &flags);  in rp2_uart_tx_empty()
279 	tx_fifo_bytes = readw(up->base + RP2_TX_FIFO_COUNT);  in rp2_uart_tx_empty()
280 	uart_port_unlock_irqrestore(&up->port, flags);  in rp2_uart_tx_empty()
285 static unsigned int rp2_uart_get_mctrl(struct uart_port *port)  in rp2_uart_get_mctrl()  argument
287 	struct rp2_uart_port *up = port_to_up(port);  in rp2_uart_get_mctrl()
290 	status = readl(up->base + RP2_CHAN_STAT);  in rp2_uart_get_mctrl()
297 static void rp2_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)  in rp2_uart_set_mctrl()  argument
299 	rp2_rmw(port_to_up(port), RP2_TXRX_CTL,  in rp2_uart_set_mctrl()
306 static void rp2_uart_start_tx(struct uart_port *port)  in rp2_uart_start_tx()  argument
308 	rp2_rmw_set(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_TXIRQ_m);  in rp2_uart_start_tx()
311 static void rp2_uart_stop_tx(struct uart_port *port)  in rp2_uart_stop_tx()  argument
313 	rp2_rmw_clr(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_TXIRQ_m);  in rp2_uart_stop_tx()
316 static void rp2_uart_stop_rx(struct uart_port *port)  in rp2_uart_stop_rx()  argument
318 	rp2_rmw_clr(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_RXIRQ_m);  in rp2_uart_stop_rx()
321 static void rp2_uart_break_ctl(struct uart_port *port, int break_state)  in rp2_uart_break_ctl()  argument
325 	uart_port_lock_irqsave(port, &flags);  in rp2_uart_break_ctl()
326 	rp2_rmw(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_BREAK_m,  in rp2_uart_break_ctl()
328 	uart_port_unlock_irqrestore(port, flags);  in rp2_uart_break_ctl()
331 static void rp2_uart_enable_ms(struct uart_port *port)  in rp2_uart_enable_ms()  argument
333 	rp2_rmw_set(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_MSRIRQ_m);  in rp2_uart_enable_ms()
341 	/* baud rate divisor (calculated elsewhere).  0 = divide-by-1 */  in __rp2_uart_set_termios()
342 	writew(baud_div - 1, up->base + RP2_BAUD);  in __rp2_uart_set_termios()
367 	       up->ucode + RP2_TX_SWFLOW);  in __rp2_uart_set_termios()
369 	       up->ucode + RP2_RX_SWFLOW);  in __rp2_uart_set_termios()
372 static void rp2_uart_set_termios(struct uart_port *port, struct ktermios *new,  in rp2_uart_set_termios()  argument
375 	struct rp2_uart_port *up = port_to_up(port);  in rp2_uart_set_termios()
379 	baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);  in rp2_uart_set_termios()
380 	baud_div = uart_get_divisor(port, baud);  in rp2_uart_set_termios()
385 	uart_port_lock_irqsave(port, &flags);  in rp2_uart_set_termios()
388 	port->ignore_status_mask = (new->c_cflag & CREAD) ? 0 : RP2_DUMMY_READ;  in rp2_uart_set_termios()
390 	__rp2_uart_set_termios(up, new->c_cflag, new->c_iflag, baud_div);  in rp2_uart_set_termios()
391 	uart_update_timeout(port, new->c_cflag, baud);  in rp2_uart_set_termios()
393 	uart_port_unlock_irqrestore(port, flags);  in rp2_uart_set_termios()
398 	u16 bytes = readw(up->base + RP2_RX_FIFO_COUNT);  in rp2_rx_chars()
399 	struct tty_port *port = &up->port.state->port;  in rp2_rx_chars()  local
401 	for (; bytes != 0; bytes--) {  in rp2_rx_chars()
402 		u32 byte = readw(up->base + RP2_DATA_BYTE) | RP2_DUMMY_READ;  in rp2_rx_chars()
406 			if (!uart_handle_sysrq_char(&up->port, ch))  in rp2_rx_chars()
407 				uart_insert_char(&up->port, byte, 0, ch,  in rp2_rx_chars()
418 			uart_insert_char(&up->port, byte,  in rp2_rx_chars()
421 		up->port.icount.rx++;  in rp2_rx_chars()
424 	tty_flip_buffer_push(port);  in rp2_rx_chars()
431 	uart_port_tx_limited(&up->port, ch,  in rp2_tx_chars()
432 		FIFO_SIZE - readw(up->base + RP2_TX_FIFO_COUNT),  in rp2_tx_chars()
434 		writeb(ch, up->base + RP2_DATA_BYTE),  in rp2_tx_chars()
442 	uart_port_lock(&up->port);  in rp2_ch_interrupt()
445 	 * The IRQ status bits are clear-on-write.  Other status bits in  in rp2_ch_interrupt()
448 	status = readl(up->base + RP2_CHAN_STAT);  in rp2_ch_interrupt()
449 	writel(status, up->base + RP2_CHAN_STAT);  in rp2_ch_interrupt()
456 		wake_up_interruptible(&up->port.state->port.delta_msr_wait);  in rp2_ch_interrupt()
458 	uart_port_unlock(&up->port);  in rp2_ch_interrupt()
463 	void __iomem *base = card->bar1 + RP2_ASIC_OFFSET(asic_id);  in rp2_asic_interrupt()
469 		rp2_ch_interrupt(&card->ports[ch]);  in rp2_asic_interrupt()
481 	if (card->n_ports >= PORTS_PER_ASIC)  in rp2_uart_interrupt()
491 	readl(up->base + RP2_UART_CTL);  in rp2_flush_fifos()
497 static int rp2_uart_startup(struct uart_port *port)  in rp2_uart_startup()  argument
499 	struct rp2_uart_port *up = port_to_up(port);  in rp2_uart_startup()
506 	rp2_mask_ch_irq(up, up->idx, 1);  in rp2_uart_startup()
511 static void rp2_uart_shutdown(struct uart_port *port)  in rp2_uart_shutdown()  argument
513 	struct rp2_uart_port *up = port_to_up(port);  in rp2_uart_shutdown()
516 	rp2_uart_break_ctl(port, 0);  in rp2_uart_shutdown()
518 	uart_port_lock_irqsave(port, &flags);  in rp2_uart_shutdown()
519 	rp2_mask_ch_irq(up, up->idx, 0);  in rp2_uart_shutdown()
521 	uart_port_unlock_irqrestore(port, flags);  in rp2_uart_shutdown()
524 static const char *rp2_uart_type(struct uart_port *port)  in rp2_uart_type()  argument
526 	return (port->type == PORT_RP2) ? "RocketPort 2 UART" : NULL;  in rp2_uart_type()
529 static void rp2_uart_release_port(struct uart_port *port)  in rp2_uart_release_port()  argument
534 static int rp2_uart_request_port(struct uart_port *port)  in rp2_uart_request_port()  argument
540 static void rp2_uart_config_port(struct uart_port *port, int flags)  in rp2_uart_config_port()  argument
543 		port->type = PORT_RP2;  in rp2_uart_config_port()
546 static int rp2_uart_verify_port(struct uart_port *port,  in rp2_uart_verify_port()  argument
549 	if (ser->type != PORT_UNKNOWN && ser->type != PORT_RP2)  in rp2_uart_verify_port()
550 		return -EINVAL;  in rp2_uart_verify_port()
576 	void __iomem *base = card->bar1 + RP2_ASIC_OFFSET(asic_id);  in rp2_reset_asic()
586 	clk_cfg = (clk_cfg & ~BIT(8)) | BIT(9);  in rp2_reset_asic()
596 	writel(4, card->bar0 + RP2_FPGA_CTL0);  in rp2_init_card()
597 	writel(0, card->bar0 + RP2_FPGA_CTL1);  in rp2_init_card()
600 	if (card->n_ports >= PORTS_PER_ASIC)  in rp2_init_card()
603 	writel(RP2_IRQ_MASK_EN_m, card->bar0 + RP2_IRQ_MASK);  in rp2_init_card()
610 	writel(RP2_UART_CTL_RESET_CH_m, up->base + RP2_UART_CTL);  in rp2_init_port()
611 	readl(up->base + RP2_UART_CTL);  in rp2_init_port()
614 	writel(0, up->base + RP2_TXRX_CTL);  in rp2_init_port()
615 	writel(0, up->base + RP2_UART_CTL);  in rp2_init_port()
616 	readl(up->base + RP2_UART_CTL);  in rp2_init_port()
621 	for (i = 0; i < min_t(int, fw->size, RP2_UCODE_BYTES); i++)  in rp2_init_port()
622 		writeb(fw->data[i], up->ucode + i);  in rp2_init_port()
625 	rp2_uart_set_mctrl(&up->port, 0);  in rp2_init_port()
627 	writeb(RP2_RX_FIFO_ena, up->ucode + RP2_RX_FIFO);  in rp2_init_port()
638 	for (i = 0; i < card->initialized_ports; i++)  in rp2_remove_ports()
639 		uart_remove_one_port(&rp2_uart_driver, &card->ports[i].port);  in rp2_remove_ports()
640 	card->initialized_ports = 0;  in rp2_remove_ports()
648 	phys_base = pci_resource_start(card->pdev, 1);  in rp2_load_firmware()
650 	for (i = 0; i < card->n_ports; i++) {  in rp2_load_firmware()
651 		struct rp2_uart_port *rp = &card->ports[i];  in rp2_load_firmware()
655 		rp->asic_base = card->bar1;  in rp2_load_firmware()
656 		rp->base = card->bar1 + RP2_PORT_BASE + j*RP2_PORT_SPACING;  in rp2_load_firmware()
657 		rp->ucode = card->bar1 + RP2_UCODE_BASE + j*RP2_UCODE_SPACING;  in rp2_load_firmware()
658 		rp->card = card;  in rp2_load_firmware()
659 		rp->idx = j;  in rp2_load_firmware()
661 		p = &rp->port;  in rp2_load_firmware()
662 		p->line = card->minor_start + i;  in rp2_load_firmware()
663 		p->dev = &card->pdev->dev;  in rp2_load_firmware()
664 		p->type = PORT_RP2;  in rp2_load_firmware()
665 		p->iotype = UPIO_MEM32;  in rp2_load_firmware()
666 		p->uartclk = UART_CLOCK;  in rp2_load_firmware()
667 		p->regshift = 2;  in rp2_load_firmware()
668 		p->fifosize = FIFO_SIZE;  in rp2_load_firmware()
669 		p->ops = &rp2_uart_ops;  in rp2_load_firmware()
670 		p->irq = card->pdev->irq;  in rp2_load_firmware()
671 		p->membase = rp->base;  in rp2_load_firmware()
672 		p->mapbase = phys_base + RP2_PORT_BASE + j*RP2_PORT_SPACING;  in rp2_load_firmware()
675 			rp->asic_base += RP2_ASIC_SPACING;  in rp2_load_firmware()
676 			rp->base += RP2_ASIC_SPACING;  in rp2_load_firmware()
677 			rp->ucode += RP2_ASIC_SPACING;  in rp2_load_firmware()
678 			p->mapbase += RP2_ASIC_SPACING;  in rp2_load_firmware()
684 			dev_err(&card->pdev->dev,  in rp2_load_firmware()
685 				"error registering port %d: %d\n", i, rc);  in rp2_load_firmware()
689 		card->initialized_ports++;  in rp2_load_firmware()
703 	card = devm_kzalloc(&pdev->dev, sizeof(*card), GFP_KERNEL);  in rp2_probe()
705 		return -ENOMEM;  in rp2_probe()
707 	spin_lock_init(&card->card_lock);  in rp2_probe()
717 	card->bar0 = pcim_iomap(pdev, 0, 0);  in rp2_probe()
718 	if (!card->bar0)  in rp2_probe()
719 		return -ENOMEM;  in rp2_probe()
720 	card->bar1 = pcim_iomap(pdev, 1, 0);  in rp2_probe()
721 	if (!card->bar1)  in rp2_probe()
722 		return -ENOMEM;  in rp2_probe()
723 	card->pdev = pdev;  in rp2_probe()
725 	rp2_decode_cap(id, &card->n_ports, &card->smpte);  in rp2_probe()
726 	dev_info(&pdev->dev, "found new card with %d ports\n", card->n_ports);  in rp2_probe()
728 	card->minor_start = rp2_alloc_ports(card->n_ports);  in rp2_probe()
729 	if (card->minor_start < 0) {  in rp2_probe()
730 		dev_err(&pdev->dev,  in rp2_probe()
732 		return -EINVAL;  in rp2_probe()
737 	ports = devm_kcalloc(&pdev->dev, card->n_ports, sizeof(*ports),  in rp2_probe()
740 		return -ENOMEM;  in rp2_probe()
741 	card->ports = ports;  in rp2_probe()
743 	rc = request_firmware(&fw, RP2_FW_NAME, &pdev->dev);  in rp2_probe()
745 		dev_err(&pdev->dev, "cannot find '%s' firmware image\n",  in rp2_probe()
756 	rc = devm_request_irq(&pdev->dev, pdev->irq, rp2_uart_interrupt,  in rp2_probe()
775 	{ RP_ID(0x0040), RP_CAP(8,  0) }, /* INF Octa, RJ45, selectable */
777 	{ RP_ID(0x0042), RP_CAP(8,  0) }, /* INF Octa, ext interface */
780 	{ RP_ID(0x0045), RP_CAP(8,  0) }, /* INF Octa, DB, selectable */
784 	{ RP_ID(0x004b), RP_CAP(8,  0) }, /* INF Plus, Octa */
785 	{ RP_ID(0x004c), RP_CAP(8,  0) }, /* INF III, Octa */
790 	{ RP_ID(0x0051), RP_CAP(8,  0) }, /* INF Plus, Octa, RJ45 */
791 	{ RP_ID(0x0052), RP_CAP(8,  1) }, /* INF Octa, SMPTE */
795 	{ RP_ID(0x0060), RP_CAP(8,  0) }, /* EXP Octa, RJ45, selectable */
797 	{ RP_ID(0x0062), RP_CAP(8,  0) }, /* EXP Octa, ext interface */
800 	{ RP_ID(0x0065), RP_CAP(8,  0) }, /* EXP Octa, DB, selectable */
803 	{ RP_ID(0x0068), RP_CAP(8,  0) }, /* EXP Octa, RJ11 */
804 	{ RP_ID(0x0072), RP_CAP(8,  1) }, /* EXP Octa, SMPTE */