Lines Matching full:psc
3 * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs.
62 * psc->mpc52xx_psc_imr
75 #define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase)) macro
83 /* PSC fifo operations for isolating differences between 52xx and 512x */
124 static inline void mpc52xx_set_divisor(struct mpc52xx_psc __iomem *psc, in mpc52xx_set_divisor() argument
128 out_be16(&psc->mpc52xx_psc_clock_select, prescaler); in mpc52xx_set_divisor()
129 out_8(&psc->ctur, divisor >> 8); in mpc52xx_set_divisor()
130 out_8(&psc->ctlr, divisor & 0xff); in mpc52xx_set_divisor()
135 return in_be16(&PSC(port)->mpc52xx_psc_status); in mpc52xx_psc_get_status()
140 return in_8(&PSC(port)->mpc52xx_psc_ipcr); in mpc52xx_psc_get_ipcr()
145 out_8(&PSC(port)->command, cmd); in mpc52xx_psc_command()
150 out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1); in mpc52xx_psc_set_mode()
151 out_8(&PSC(port)->mode, mr1); in mpc52xx_psc_set_mode()
152 out_8(&PSC(port)->mode, mr2); in mpc52xx_psc_set_mode()
158 out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS); in mpc52xx_psc_set_rts()
160 out_8(&PSC(port)->op0, MPC52xx_PSC_OP_RTS); in mpc52xx_psc_set_rts()
165 struct mpc52xx_psc __iomem *psc = PSC(port); in mpc52xx_psc_enable_ms() local
168 in_8(&psc->mpc52xx_psc_ipcr); in mpc52xx_psc_enable_ms()
170 out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD); in mpc52xx_psc_enable_ms()
173 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); in mpc52xx_psc_enable_ms()
178 out_be32(&PSC(port)->sicr, val); in mpc52xx_psc_set_sicr()
183 out_be16(&PSC(port)->mpc52xx_psc_imr, val); in mpc52xx_psc_set_imr()
188 out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1); in mpc52xx_psc_get_mr1()
189 return in_8(&PSC(port)->mode); in mpc52xx_psc_get_mr1()
193 #define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1))
196 struct mpc52xx_psc __iomem *psc = PSC(port); in mpc52xx_psc_fifo_init() local
205 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); in mpc52xx_psc_fifo_init()
210 return in_be16(&PSC(port)->mpc52xx_psc_status) in mpc52xx_psc_raw_rx_rdy()
216 return in_be16(&PSC(port)->mpc52xx_psc_status) in mpc52xx_psc_raw_tx_rdy()
223 return in_be16(&PSC(port)->mpc52xx_psc_isr) in mpc52xx_psc_rx_rdy()
230 return in_be16(&PSC(port)->mpc52xx_psc_isr) in mpc52xx_psc_tx_rdy()
237 u16 sts = in_be16(&PSC(port)->mpc52xx_psc_status); in mpc52xx_psc_tx_empty()
245 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); in mpc52xx_psc_start_tx()
251 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); in mpc52xx_psc_stop_tx()
257 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); in mpc52xx_psc_stop_rx()
270 out_8(&PSC(port)->mpc52xx_psc_buffer_8, c); in mpc52xx_psc_write_char()
275 return in_8(&PSC(port)->mpc52xx_psc_buffer_8); in mpc52xx_psc_read_char()
280 out_be16(&PSC(port)->mpc52xx_psc_imr, 0); in mpc52xx_psc_cw_disable_ints()
285 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); in mpc52xx_psc_cw_restore_ints()
302 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor); in mpc5200_psc_set_baudrate()
328 mpc52xx_set_divisor(PSC(port), prescaler, divisor); in mpc5200b_psc_set_baudrate()
407 #define FIFO_512x(port) ((struct mpc512x_psc_fifo __iomem *)(PSC(port)+1))
409 /* PSC FIFO Controller for mpc512x */
425 out_be16(&PSC(port)->mpc52xx_psc_clock_select, 0xdd00); in mpc512x_psc_fifo_init()
550 * Chapter 4.1 PSC in UART Mode. in mpc512x_psc_set_baudrate()
561 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor); in mpc512x_psc_set_baudrate()
565 /* Init PSC FIFO Controller */
576 "fsl,mpc5121-psc-fifo"); in mpc512x_psc_fifoc_init()
643 /* Read pending PSC FIFOC interrupts */ in mpc512x_psc_handle_irq()
738 dev_err(port->dev, "Failed to get PSC clock entry!\n"); in mpc512x_psc_endis_clock()
872 static inline void mpc5125_set_divisor(struct mpc5125_psc __iomem *psc, in mpc5125_set_divisor() argument
876 out_8(&psc->mpc52xx_psc_clock_select, prescaler); in mpc5125_set_divisor()
877 out_8(&psc->ctur, divisor >> 8); in mpc5125_set_divisor()
878 out_8(&psc->ctlr, divisor & 0xff); in mpc5125_set_divisor()
904 * MPC5125 have compatible PSC FIFO Controller.
938 struct mpc5125_psc __iomem *psc = PSC_5125(port); in mpc5125_psc_enable_ms() local
941 in_8(&psc->mpc52xx_psc_ipcr); in mpc5125_psc_enable_ms()
943 out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD); in mpc5125_psc_enable_ms()
946 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); in mpc5125_psc_enable_ms()
1263 return port->type == PORT_MPC52xx ? "MPC5xxx PSC" : NULL; in mpc52xx_uart_type()
1583 pr_debug("PSC%x out of range\n", co->index); in mpc52xx_console_setup()
1588 pr_debug("PSC%x not found in device tree\n", co->index); in mpc52xx_console_setup()
1598 pr_debug("Could not get resources for PSC%x\n", co->index); in mpc52xx_console_setup()
1620 pr_debug("mpc52xx-psc uart at %p, mapped to %p, irq=%x, freq=%i\n", in mpc52xx_console_setup()
1685 { .compatible = "fsl,mpc5200b-psc-uart", .data = &mpc5200b_psc_ops, },
1686 { .compatible = "fsl,mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
1688 { .compatible = "mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
1693 { .compatible = "fsl,mpc5121-psc-uart", .data = &mpc512x_psc_ops, },
1694 { .compatible = "fsl,mpc5125-psc-uart", .data = &mpc5125_psc_ops, },
1716 /* set the uart clock to the input clock of the psc, the different in mpc52xx_uart_of_probe()
1746 dev_dbg(&op->dev, "Could not allocate resources for PSC\n"); in mpc52xx_uart_of_probe()
1756 dev_dbg(&op->dev, "mpc52xx-psc uart at %p, irq=%x, freq=%i\n", in mpc52xx_uart_of_probe()
1805 /* Find the first free PSC number */ in mpc52xx_uart_of_assign()
1826 /* Assign index to each PSC in device tree */ in mpc52xx_uart_of_enumerate()
1852 .name = "mpc52xx-psc-uart",
1867 printk(KERN_INFO "Serial: MPC52xx PSC UART driver\n"); in mpc52xx_uart_init()
1879 * Map the PSC FIFO Controller and init if on MPC512x. in mpc52xx_uart_init()
1918 MODULE_DESCRIPTION("Freescale MPC52xx PSC UART");