Lines Matching +full:auto +full:- +full:baud
1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2012-2016 Alexander Shiyan <[email protected]>
51 #define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */
65 #define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */
66 #define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */
67 #define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */
106 #define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */
119 #define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */
120 #define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */
123 #define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */
133 #define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */
141 * 00 -> 5 bit words
142 * 01 -> 6 bit words
143 * 10 -> 7 bit words
144 * 11 -> 8 bit words
149 * 0 -> 1 stop bit
150 * 1 -> 1-1.5 stop bits if
156 #define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
177 #define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */
178 #define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */
184 #define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */
189 * 00 -> no transmitter flow
191 * 01 -> receiver compares
195 * 10 -> receiver compares
199 * 11 -> receiver compares
208 * 00 -> no received flow
210 * 01 -> transmitter generates
212 * 10 -> transmitter generates
214 * 11 -> transmitter generates
223 /* Baud rate generator configuration register bits */
224 #define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */
225 #define MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */
232 #define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */
247 /* Crystal-related definitions */
277 u8 power_bit; /* Bit for sleep or power-off mode (active high). */
319 regmap_read(one->regmap, reg, &val); in max310x_port_read()
328 regmap_write(one->regmap, reg, val); in max310x_port_write()
335 regmap_update_bits(one->regmap, reg, mask, val); in max310x_port_update()
345 if (s->devtype->rev_id_val) { in max310x_detect()
346 u8 rev_id_reg = s->devtype->rev_id_reg; in max310x_detect()
349 if (s->devtype->rev_id_reg >= MAX310X_EXTREG_START) { in max310x_detect()
350 ret = s->if_cfg->extended_reg_enable(dev, true); in max310x_detect()
355 if (s->if_cfg->rev_id_offset) in max310x_detect()
356 rev_id_reg -= s->if_cfg->rev_id_offset; in max310x_detect()
359 regmap_read(s->regmap, rev_id_reg, &val); in max310x_detect()
361 if (s->devtype->rev_id_reg >= MAX310X_EXTREG_START) { in max310x_detect()
362 ret = s->if_cfg->extended_reg_enable(dev, false); in max310x_detect()
367 if (((val & MAX310x_REV_MASK) != s->devtype->rev_id_val)) in max310x_detect()
368 return dev_err_probe(dev, -ENODEV, in max310x_detect()
370 s->devtype->name, val); in max310x_detect()
376 ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val); in max310x_detect()
381 return dev_err_probe(dev, -ENODEV, in max310x_detect()
383 s->devtype->name); in max310x_detect()
391 struct max310x_port *s = dev_get_drvdata(port->dev); in max310x_power()
393 max310x_port_update(port, s->devtype->power_reg, s->devtype->power_bit, in max310x_power()
394 on ? 0 : s->devtype->power_bit); in max310x_power()
508 static int max310x_set_baud(struct uart_port *port, int baud) in max310x_set_baud() argument
514 * in case if the requested baud is too high for the pre-defined in max310x_set_baud()
517 div = port->uartclk / baud; in max310x_set_baud()
532 F = c*baud; in max310x_set_baud()
534 /* Calculate the baud rate fraction */ in max310x_set_baud()
536 frac = (16*(port->uartclk % F)) / F; in max310x_set_baud()
544 /* Return the actual baud rate we just programmed */ in max310x_set_baud()
545 return (16*port->uartclk) / (c*(16*div + frac)); in max310x_set_baud()
565 long besterr = -1; in max310x_set_ref_clk()
611 regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg); in max310x_set_ref_clk()
615 regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc); in max310x_set_ref_clk()
624 regmap_read(s->regmap, MAX310X_STS_IRQSTS_REG, &val); in max310x_set_ref_clk()
631 return dev_err_probe(dev, -EAGAIN, in max310x_set_ref_clk()
642 regmap_noinc_write(one->regmap, MAX310X_THR_REG, txbuf, len); in max310x_batch_write()
649 regmap_noinc_read(one->regmap, MAX310X_RHR_REG, rxbuf, len); in max310x_batch_read()
658 if (port->read_status_mask == MAX310X_LSR_RXOVR_BIT) { in max310x_handle_rx()
661 * Break condition, parity checking, framing errors -- they in max310x_handle_rx()
662 * are all ignored. That means that we can do a batch-read. in max310x_handle_rx()
672 max310x_batch_read(port, one->rx_buf, rxlen); in max310x_handle_rx()
674 port->icount.rx += rxlen; in max310x_handle_rx()
676 sts &= port->read_status_mask; in max310x_handle_rx()
679 dev_warn_ratelimited(port->dev, "Hardware RX FIFO overrun\n"); in max310x_handle_rx()
680 port->icount.overrun++; in max310x_handle_rx()
683 for (i = 0; i < (rxlen - 1); ++i) in max310x_handle_rx()
684 uart_insert_char(port, sts, 0, one->rx_buf[i], flag); in max310x_handle_rx()
692 one->rx_buf[rxlen-1], flag); in max310x_handle_rx()
695 if (unlikely(rxlen >= port->fifosize)) { in max310x_handle_rx()
696 dev_warn_ratelimited(port->dev, "Possible RX FIFO overrun\n"); in max310x_handle_rx()
697 port->icount.buf_overrun++; in max310x_handle_rx()
699 rxlen = port->fifosize; in max310x_handle_rx()
702 while (rxlen--) { in max310x_handle_rx()
709 port->icount.rx++; in max310x_handle_rx()
714 port->icount.brk++; in max310x_handle_rx()
718 port->icount.parity++; in max310x_handle_rx()
720 port->icount.frame++; in max310x_handle_rx()
722 port->icount.overrun++; in max310x_handle_rx()
724 sts &= port->read_status_mask; in max310x_handle_rx()
738 if (sts & port->ignore_status_mask) in max310x_handle_rx()
745 tty_flip_buffer_push(&port->state->port); in max310x_handle_rx()
750 struct tty_port *tport = &port->state->port; in max310x_handle_tx()
754 if (unlikely(port->x_char)) { in max310x_handle_tx()
755 max310x_port_write(port, MAX310X_THR_REG, port->x_char); in max310x_handle_tx()
756 port->icount.tx++; in max310x_handle_tx()
757 port->x_char = 0; in max310x_handle_tx()
761 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)) in max310x_handle_tx()
765 * It's a circ buffer -- wrap around. in max310x_handle_tx()
768 while (!kfifo_is_empty(&tport->xmit_fifo)) { in max310x_handle_tx()
771 txlen = port->fifosize - txlen; in max310x_handle_tx()
775 to_send = kfifo_out_linear_ptr(&tport->xmit_fifo, &tail, txlen); in max310x_handle_tx()
780 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in max310x_handle_tx()
788 schedule_work(&one->tx_work); in max310x_start_tx()
793 struct uart_port *port = &s->p[portno].port; in max310x_port_irq()
825 if (s->devtype->nr > 1) { in max310x_ist()
829 WARN_ON_ONCE(regmap_read(s->regmap, in max310x_ist()
831 val = ((1 << s->devtype->nr) - 1) & ~val; in max310x_ist()
834 if (max310x_port_irq(s, fls(val) - 1) == IRQ_HANDLED) in max310x_ist()
849 max310x_handle_tx(&one->port); in max310x_tx_proc()
872 max310x_port_update(&one->port, MAX310X_MODE2_REG, in max310x_md_proc()
874 (one->port.mctrl & TIOCM_LOOP) ? in max310x_md_proc()
882 schedule_work(&one->md_work); in max310x_set_mctrl()
897 int baud; in max310x_set_termios() local
900 termios->c_cflag &= ~CMSPAR; in max310x_set_termios()
903 switch (termios->c_cflag & CSIZE) { in max310x_set_termios()
919 if (termios->c_cflag & PARENB) { in max310x_set_termios()
921 if (!(termios->c_cflag & PARODD)) in max310x_set_termios()
926 if (termios->c_cflag & CSTOPB) in max310x_set_termios()
933 port->read_status_mask = MAX310X_LSR_RXOVR_BIT; in max310x_set_termios()
934 if (termios->c_iflag & INPCK) in max310x_set_termios()
935 port->read_status_mask |= MAX310X_LSR_RXPAR_BIT | in max310x_set_termios()
937 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in max310x_set_termios()
938 port->read_status_mask |= MAX310X_LSR_RXBRK_BIT; in max310x_set_termios()
941 port->ignore_status_mask = 0; in max310x_set_termios()
942 if (termios->c_iflag & IGNBRK) in max310x_set_termios()
943 port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT; in max310x_set_termios()
944 if (!(termios->c_cflag & CREAD)) in max310x_set_termios()
945 port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT | in max310x_set_termios()
951 max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]); in max310x_set_termios()
952 max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]); in max310x_set_termios()
955 * Disable transmitter before enabling AutoCTS or auto transmitter in max310x_set_termios()
958 if (termios->c_cflag & CRTSCTS || termios->c_iflag & IXOFF) { in max310x_set_termios()
964 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); in max310x_set_termios()
966 if (termios->c_cflag & CRTSCTS) { in max310x_set_termios()
968 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; in max310x_set_termios()
972 if (termios->c_iflag & IXON) in max310x_set_termios()
975 if (termios->c_iflag & IXOFF) { in max310x_set_termios()
976 port->status |= UPSTAT_AUTOXOFF; in max310x_set_termios()
983 * Enable transmitter after disabling AutoCTS and auto transmitter in max310x_set_termios()
986 if (!(termios->c_cflag & CRTSCTS) && !(termios->c_iflag & IXOFF)) { in max310x_set_termios()
992 /* Get baud rate generator configuration */ in max310x_set_termios()
993 baud = uart_get_baud_rate(port, termios, old, in max310x_set_termios()
994 port->uartclk / 16 / 0xffff, in max310x_set_termios()
995 port->uartclk / 4); in max310x_set_termios()
998 baud = max310x_set_baud(port, baud); in max310x_set_termios()
1000 /* Update timeout according to new baud rate */ in max310x_set_termios()
1001 uart_update_timeout(port, termios->c_cflag, baud); in max310x_set_termios()
1009 delay = (one->port.rs485.delay_rts_before_send << 4) | in max310x_rs_proc()
1010 one->port.rs485.delay_rts_after_send; in max310x_rs_proc()
1011 max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, delay); in max310x_rs_proc()
1013 if (one->port.rs485.flags & SER_RS485_ENABLED) { in max310x_rs_proc()
1016 if (!(one->port.rs485.flags & SER_RS485_RX_DURING_TX)) in max310x_rs_proc()
1020 max310x_port_update(&one->port, MAX310X_MODE1_REG, in max310x_rs_proc()
1022 max310x_port_update(&one->port, MAX310X_MODE2_REG, in max310x_rs_proc()
1031 if ((rs485->delay_rts_before_send > 0x0f) || in max310x_rs485_config()
1032 (rs485->delay_rts_after_send > 0x0f)) in max310x_rs485_config()
1033 return -ERANGE; in max310x_rs485_config()
1035 port->rs485 = *rs485; in max310x_rs485_config()
1037 schedule_work(&one->rs_work); in max310x_rs485_config()
1059 val = (clamp(port->rs485.delay_rts_before_send, 0U, 15U) << 4) | in max310x_startup()
1060 clamp(port->rs485.delay_rts_after_send, 0U, 15U); in max310x_startup()
1063 if (port->rs485.flags & SER_RS485_ENABLED) { in max310x_startup()
1068 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) in max310x_startup()
1102 struct max310x_port *s = dev_get_drvdata(port->dev); in max310x_type()
1104 return (port->type == PORT_MAX310X) ? s->devtype->name : NULL; in max310x_type()
1116 port->type = PORT_MAX310X; in max310x_config_port()
1121 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X)) in max310x_verify_port()
1122 return -EINVAL; in max310x_verify_port()
1123 if (s->irq != port->irq) in max310x_verify_port()
1124 return -EINVAL; in max310x_verify_port()
1157 for (i = 0; i < s->devtype->nr; i++) { in max310x_suspend()
1158 uart_suspend_port(&max310x_uart, &s->p[i].port); in max310x_suspend()
1159 max310x_power(&s->p[i].port, 0); in max310x_suspend()
1170 for (i = 0; i < s->devtype->nr; i++) { in max310x_resume()
1171 max310x_power(&s->p[i].port, 1); in max310x_resume()
1172 uart_resume_port(&max310x_uart, &s->p[i].port); in max310x_resume()
1185 struct uart_port *port = &s->p[offset / 4].port; in max310x_gpio_get()
1195 struct uart_port *port = &s->p[offset / 4].port; in max310x_gpio_set()
1204 struct uart_port *port = &s->p[offset / 4].port; in max310x_gpio_direction_input()
1215 struct uart_port *port = &s->p[offset / 4].port; in max310x_gpio_direction_output()
1229 struct uart_port *port = &s->p[offset / 4].port; in max310x_gpio_set_config()
1242 return -ENOTSUPP; in max310x_gpio_set_config()
1262 for (i = 0; i < devtype->nr; i++) in max310x_probe()
1267 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr), GFP_KERNEL); in max310x_probe()
1269 return dev_err_probe(dev, -ENOMEM, in max310x_probe()
1273 device_property_read_u32(dev, "clock-frequency", &uartclk); in max310x_probe()
1275 xtal = device_property_match_string(dev, "clock-names", "osc") < 0; in max310x_probe()
1277 s->clk = devm_clk_get_optional(dev, "xtal"); in max310x_probe()
1279 s->clk = devm_clk_get_optional(dev, "osc"); in max310x_probe()
1280 if (IS_ERR(s->clk)) in max310x_probe()
1281 return PTR_ERR(s->clk); in max310x_probe()
1283 ret = clk_prepare_enable(s->clk); in max310x_probe()
1287 freq = clk_get_rate(s->clk); in max310x_probe()
1291 ret = dev_err_probe(dev, -EINVAL, "Cannot get clock rate\n"); in max310x_probe()
1305 ret = -ERANGE; in max310x_probe()
1309 s->regmap = regmaps[0]; in max310x_probe()
1310 s->devtype = devtype; in max310x_probe()
1311 s->if_cfg = if_cfg; in max310x_probe()
1319 for (i = 0; i < devtype->nr; i++) { in max310x_probe()
1339 ret = dev_err_probe(dev, -EAGAIN, "port reset failed\n"); in max310x_probe()
1343 regmap_write(regmaps[i], MAX310X_MODE1_REG, devtype->mode1); in max310x_probe()
1354 for (i = 0; i < devtype->nr; i++) { in max310x_probe()
1359 ret = -ERANGE; in max310x_probe()
1364 s->p[i].port.line = line; in max310x_probe()
1365 s->p[i].port.dev = dev; in max310x_probe()
1366 s->p[i].port.irq = irq; in max310x_probe()
1367 s->p[i].port.type = PORT_MAX310X; in max310x_probe()
1368 s->p[i].port.fifosize = MAX310X_FIFO_SIZE; in max310x_probe()
1369 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; in max310x_probe()
1370 s->p[i].port.iotype = UPIO_PORT; in max310x_probe()
1371 s->p[i].port.iobase = i; in max310x_probe()
1377 s->p[i].port.membase = (void __iomem *)~0; in max310x_probe()
1378 s->p[i].port.uartclk = uartclk; in max310x_probe()
1379 s->p[i].port.rs485_config = max310x_rs485_config; in max310x_probe()
1380 s->p[i].port.rs485_supported = max310x_rs485_supported; in max310x_probe()
1381 s->p[i].port.ops = &max310x_ops; in max310x_probe()
1382 s->p[i].regmap = regmaps[i]; in max310x_probe()
1385 max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0); in max310x_probe()
1387 max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG); in max310x_probe()
1389 INIT_WORK(&s->p[i].tx_work, max310x_tx_proc); in max310x_probe()
1391 INIT_WORK(&s->p[i].md_work, max310x_md_proc); in max310x_probe()
1393 INIT_WORK(&s->p[i].rs_work, max310x_rs_proc); in max310x_probe()
1396 ret = uart_add_one_port(&max310x_uart, &s->p[i].port); in max310x_probe()
1403 max310x_power(&s->p[i].port, 0); in max310x_probe()
1408 s->gpio.owner = THIS_MODULE; in max310x_probe()
1409 s->gpio.parent = dev; in max310x_probe()
1410 s->gpio.label = devtype->name; in max310x_probe()
1411 s->gpio.direction_input = max310x_gpio_direction_input; in max310x_probe()
1412 s->gpio.get = max310x_gpio_get; in max310x_probe()
1413 s->gpio.direction_output= max310x_gpio_direction_output; in max310x_probe()
1414 s->gpio.set = max310x_gpio_set; in max310x_probe()
1415 s->gpio.set_config = max310x_gpio_set_config; in max310x_probe()
1416 s->gpio.base = -1; in max310x_probe()
1417 s->gpio.ngpio = devtype->nr * 4; in max310x_probe()
1418 s->gpio.can_sleep = 1; in max310x_probe()
1419 ret = devm_gpiochip_add_data(dev, &s->gpio, s); in max310x_probe()
1433 for (i = 0; i < devtype->nr; i++) { in max310x_probe()
1434 if (test_and_clear_bit(s->p[i].port.line, max310x_lines)) in max310x_probe()
1435 uart_remove_one_port(&max310x_uart, &s->p[i].port); in max310x_probe()
1439 clk_disable_unprepare(s->clk); in max310x_probe()
1449 for (i = 0; i < s->devtype->nr; i++) { in max310x_remove()
1450 cancel_work_sync(&s->p[i].tx_work); in max310x_remove()
1451 cancel_work_sync(&s->p[i].md_work); in max310x_remove()
1452 cancel_work_sync(&s->p[i].rs_work); in max310x_remove()
1454 if (test_and_clear_bit(s->p[i].port.line, max310x_lines)) in max310x_remove()
1455 uart_remove_one_port(&max310x_uart, &s->p[i].port); in max310x_remove()
1457 max310x_power(&s->p[i].port, 0); in max310x_remove()
1460 clk_disable_unprepare(s->clk); in max310x_remove()
1505 return regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, in max310x_spi_extended_reg_enable()
1522 spi->bits_per_word = 8; in max310x_spi_probe()
1523 spi->mode = spi->mode ? : SPI_MODE_0; in max310x_spi_probe()
1524 spi->max_speed_hz = spi->max_speed_hz ? : 26000000; in max310x_spi_probe()
1531 return dev_err_probe(&spi->dev, -ENODEV, "Failed to match device\n"); in max310x_spi_probe()
1533 for (i = 0; i < devtype->nr; i++) { in max310x_spi_probe()
1542 return max310x_probe(&spi->dev, devtype, &max310x_spi_if_cfg, regmaps, spi->irq); in max310x_spi_probe()
1547 max310x_remove(&spi->dev); in max310x_spi_remove()
1604 * UART1 - UART0 = 0x10 in max310x_i2c_slave_addr()
1605 * UART2 - UART1 = 0x20 + 0x10 in max310x_i2c_slave_addr()
1606 * UART3 - UART2 = 0x10 in max310x_i2c_slave_addr()
1609 addr -= nr * 0x10; in max310x_i2c_slave_addr()
1612 addr -= 0x20; in max310x_i2c_slave_addr()
1627 return dev_err_probe(&client->dev, -ENODEV, "Failed to match device\n"); in max310x_i2c_probe()
1629 if (client->addr < devtype->slave_addr.min || in max310x_i2c_probe()
1630 client->addr > devtype->slave_addr.max) in max310x_i2c_probe()
1631 return dev_err_probe(&client->dev, -EINVAL, in max310x_i2c_probe()
1633 client->addr, devtype->slave_addr.min, in max310x_i2c_probe()
1634 devtype->slave_addr.max); in max310x_i2c_probe()
1639 for (i = 1; i < devtype->nr; i++) { in max310x_i2c_probe()
1640 port_addr = max310x_i2c_slave_addr(client->addr, i); in max310x_i2c_probe()
1641 port_client = devm_i2c_new_dummy_device(&client->dev, in max310x_i2c_probe()
1642 client->adapter, in max310x_i2c_probe()
1649 return max310x_probe(&client->dev, devtype, &max310x_i2c_if_cfg, in max310x_i2c_probe()
1650 regmaps, client->irq); in max310x_i2c_probe()
1655 max310x_remove(&client->dev); in max310x_i2c_remove()