Lines Matching +full:auto +full:- +full:baud
1 // SPDX-License-Identifier: GPL-2.0+
25 * a non-destructive, read-only location on the Neo card.
27 * In this case, we are reading the DVID (Read-only Device Identification)
32 readb(bd->re_map_membase + 0x8D); in neo_pci_posting_flush()
38 ier = readb(&ch->ch_neo_uart->ier); in neo_set_cts_flow_control()
39 efr = readb(&ch->ch_neo_uart->efr); in neo_set_cts_flow_control()
41 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n"); in neo_set_cts_flow_control()
43 /* Turn on auto CTS flow control */ in neo_set_cts_flow_control()
47 /* Turn off auto Xon flow control */ in neo_set_cts_flow_control()
51 writeb(0, &ch->ch_neo_uart->efr); in neo_set_cts_flow_control()
54 writeb(efr, &ch->ch_neo_uart->efr); in neo_set_cts_flow_control()
57 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr); in neo_set_cts_flow_control()
60 writeb(8, &ch->ch_neo_uart->tfifo); in neo_set_cts_flow_control()
61 ch->ch_t_tlevel = 8; in neo_set_cts_flow_control()
63 writeb(ier, &ch->ch_neo_uart->ier); in neo_set_cts_flow_control()
69 ier = readb(&ch->ch_neo_uart->ier); in neo_set_rts_flow_control()
70 efr = readb(&ch->ch_neo_uart->efr); in neo_set_rts_flow_control()
72 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting RTSFLOW\n"); in neo_set_rts_flow_control()
74 /* Turn on auto RTS flow control */ in neo_set_rts_flow_control()
78 /* Turn off auto Xoff flow control */ in neo_set_rts_flow_control()
83 writeb(0, &ch->ch_neo_uart->efr); in neo_set_rts_flow_control()
86 writeb(efr, &ch->ch_neo_uart->efr); in neo_set_rts_flow_control()
88 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr); in neo_set_rts_flow_control()
89 ch->ch_r_watermark = 4; in neo_set_rts_flow_control()
91 writeb(56, &ch->ch_neo_uart->rfifo); in neo_set_rts_flow_control()
92 ch->ch_r_tlevel = 56; in neo_set_rts_flow_control()
94 writeb(ier, &ch->ch_neo_uart->ier); in neo_set_rts_flow_control()
98 * The auto RTS/DTR function must be started by asserting in neo_set_rts_flow_control()
99 * RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after in neo_set_rts_flow_control()
102 ch->ch_mostat |= (UART_MCR_RTS); in neo_set_rts_flow_control()
109 ier = readb(&ch->ch_neo_uart->ier); in neo_set_ixon_flow_control()
110 efr = readb(&ch->ch_neo_uart->efr); in neo_set_ixon_flow_control()
112 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting IXON FLOW\n"); in neo_set_ixon_flow_control()
114 /* Turn off auto CTS flow control */ in neo_set_ixon_flow_control()
118 /* Turn on auto Xon flow control */ in neo_set_ixon_flow_control()
122 writeb(0, &ch->ch_neo_uart->efr); in neo_set_ixon_flow_control()
125 writeb(efr, &ch->ch_neo_uart->efr); in neo_set_ixon_flow_control()
127 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); in neo_set_ixon_flow_control()
128 ch->ch_r_watermark = 4; in neo_set_ixon_flow_control()
130 writeb(32, &ch->ch_neo_uart->rfifo); in neo_set_ixon_flow_control()
131 ch->ch_r_tlevel = 32; in neo_set_ixon_flow_control()
134 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1); in neo_set_ixon_flow_control()
135 writeb(0, &ch->ch_neo_uart->xonchar2); in neo_set_ixon_flow_control()
137 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1); in neo_set_ixon_flow_control()
138 writeb(0, &ch->ch_neo_uart->xoffchar2); in neo_set_ixon_flow_control()
140 writeb(ier, &ch->ch_neo_uart->ier); in neo_set_ixon_flow_control()
146 ier = readb(&ch->ch_neo_uart->ier); in neo_set_ixoff_flow_control()
147 efr = readb(&ch->ch_neo_uart->efr); in neo_set_ixoff_flow_control()
149 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting IXOFF FLOW\n"); in neo_set_ixoff_flow_control()
151 /* Turn off auto RTS flow control */ in neo_set_ixoff_flow_control()
155 /* Turn on auto Xoff flow control */ in neo_set_ixoff_flow_control()
160 writeb(0, &ch->ch_neo_uart->efr); in neo_set_ixoff_flow_control()
163 writeb(efr, &ch->ch_neo_uart->efr); in neo_set_ixoff_flow_control()
166 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); in neo_set_ixoff_flow_control()
168 writeb(8, &ch->ch_neo_uart->tfifo); in neo_set_ixoff_flow_control()
169 ch->ch_t_tlevel = 8; in neo_set_ixoff_flow_control()
172 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1); in neo_set_ixoff_flow_control()
173 writeb(0, &ch->ch_neo_uart->xonchar2); in neo_set_ixoff_flow_control()
175 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1); in neo_set_ixoff_flow_control()
176 writeb(0, &ch->ch_neo_uart->xoffchar2); in neo_set_ixoff_flow_control()
178 writeb(ier, &ch->ch_neo_uart->ier); in neo_set_ixoff_flow_control()
184 ier = readb(&ch->ch_neo_uart->ier); in neo_set_no_input_flow_control()
185 efr = readb(&ch->ch_neo_uart->efr); in neo_set_no_input_flow_control()
187 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Unsetting Input FLOW\n"); in neo_set_no_input_flow_control()
189 /* Turn off auto RTS flow control */ in neo_set_no_input_flow_control()
193 /* Turn off auto Xoff flow control */ in neo_set_no_input_flow_control()
195 if (ch->ch_c_iflag & IXON) in neo_set_no_input_flow_control()
201 writeb(0, &ch->ch_neo_uart->efr); in neo_set_no_input_flow_control()
204 writeb(efr, &ch->ch_neo_uart->efr); in neo_set_no_input_flow_control()
207 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); in neo_set_no_input_flow_control()
209 ch->ch_r_watermark = 0; in neo_set_no_input_flow_control()
211 writeb(16, &ch->ch_neo_uart->tfifo); in neo_set_no_input_flow_control()
212 ch->ch_t_tlevel = 16; in neo_set_no_input_flow_control()
214 writeb(16, &ch->ch_neo_uart->rfifo); in neo_set_no_input_flow_control()
215 ch->ch_r_tlevel = 16; in neo_set_no_input_flow_control()
217 writeb(ier, &ch->ch_neo_uart->ier); in neo_set_no_input_flow_control()
223 ier = readb(&ch->ch_neo_uart->ier); in neo_set_no_output_flow_control()
224 efr = readb(&ch->ch_neo_uart->efr); in neo_set_no_output_flow_control()
226 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Unsetting Output FLOW\n"); in neo_set_no_output_flow_control()
228 /* Turn off auto CTS flow control */ in neo_set_no_output_flow_control()
232 /* Turn off auto Xon flow control */ in neo_set_no_output_flow_control()
233 if (ch->ch_c_iflag & IXOFF) in neo_set_no_output_flow_control()
239 writeb(0, &ch->ch_neo_uart->efr); in neo_set_no_output_flow_control()
242 writeb(efr, &ch->ch_neo_uart->efr); in neo_set_no_output_flow_control()
245 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); in neo_set_no_output_flow_control()
247 ch->ch_r_watermark = 0; in neo_set_no_output_flow_control()
249 writeb(16, &ch->ch_neo_uart->tfifo); in neo_set_no_output_flow_control()
250 ch->ch_t_tlevel = 16; in neo_set_no_output_flow_control()
252 writeb(16, &ch->ch_neo_uart->rfifo); in neo_set_no_output_flow_control()
253 ch->ch_r_tlevel = 16; in neo_set_no_output_flow_control()
255 writeb(ier, &ch->ch_neo_uart->ier); in neo_set_no_output_flow_control()
262 if (ch->ch_c_cflag & CRTSCTS) in neo_set_new_start_stop_chars()
265 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "start\n"); in neo_set_new_start_stop_chars()
268 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1); in neo_set_new_start_stop_chars()
269 writeb(0, &ch->ch_neo_uart->xonchar2); in neo_set_new_start_stop_chars()
271 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1); in neo_set_new_start_stop_chars()
272 writeb(0, &ch->ch_neo_uart->xoffchar2); in neo_set_new_start_stop_chars()
286 head = ch->ch_r_head & RQUEUEMASK; in neo_copy_data_from_uart_to_queue()
287 tail = ch->ch_r_tail & RQUEUEMASK; in neo_copy_data_from_uart_to_queue()
290 linestatus = ch->ch_cached_lsr; in neo_copy_data_from_uart_to_queue()
291 ch->ch_cached_lsr = 0; in neo_copy_data_from_uart_to_queue()
294 qleft = tail - head - 1; in neo_copy_data_from_uart_to_queue()
305 if (!(ch->ch_flags & CH_FIFO_ENABLED)) in neo_copy_data_from_uart_to_queue()
308 total = readb(&ch->ch_neo_uart->rfifo); in neo_copy_data_from_uart_to_queue()
311 * EXAR chip bug - RX FIFO COUNT - Fudge factor. in neo_copy_data_from_uart_to_queue()
315 * The count can be any where from 0-3 bytes "off". in neo_copy_data_from_uart_to_queue()
318 total -= 3; in neo_copy_data_from_uart_to_queue()
334 linestatus = readb(&ch->ch_neo_uart->lsr); in neo_copy_data_from_uart_to_queue()
345 n = min(((u32) total), (RQUEUESIZE - (u32) head)); in neo_copy_data_from_uart_to_queue()
361 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in neo_copy_data_from_uart_to_queue()
366 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, n); in neo_copy_data_from_uart_to_queue()
372 memset(ch->ch_equeue + head, 0, n); in neo_copy_data_from_uart_to_queue()
376 total -= n; in neo_copy_data_from_uart_to_queue()
377 qleft -= n; in neo_copy_data_from_uart_to_queue()
378 ch->ch_rxcount += n; in neo_copy_data_from_uart_to_queue()
385 if (ch->ch_c_iflag & IGNBRK) in neo_copy_data_from_uart_to_queue()
398 linestatus |= readb(&ch->ch_neo_uart->lsr); in neo_copy_data_from_uart_to_queue()
406 ch->ch_cached_lsr = linestatus; in neo_copy_data_from_uart_to_queue()
420 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in neo_copy_data_from_uart_to_queue()
429 memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1); in neo_copy_data_from_uart_to_queue()
442 jsm_dbg(READ, &ch->ch_bd->pci_dev, in neo_copy_data_from_uart_to_queue()
444 ch->ch_rqueue[tail], ch->ch_equeue[tail]); in neo_copy_data_from_uart_to_queue()
446 ch->ch_r_tail = tail = (tail + 1) & RQUEUEMASK; in neo_copy_data_from_uart_to_queue()
447 ch->ch_err_overrun++; in neo_copy_data_from_uart_to_queue()
451 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, 1); in neo_copy_data_from_uart_to_queue()
452 ch->ch_equeue[head] = (u8) linestatus; in neo_copy_data_from_uart_to_queue()
454 jsm_dbg(READ, &ch->ch_bd->pci_dev, "DATA/LSR pair: %x %x\n", in neo_copy_data_from_uart_to_queue()
455 ch->ch_rqueue[head], ch->ch_equeue[head]); in neo_copy_data_from_uart_to_queue()
463 qleft--; in neo_copy_data_from_uart_to_queue()
464 ch->ch_rxcount++; in neo_copy_data_from_uart_to_queue()
470 ch->ch_r_head = head & RQUEUEMASK; in neo_copy_data_from_uart_to_queue()
471 ch->ch_e_head = head & EQUEUEMASK; in neo_copy_data_from_uart_to_queue()
488 tport = &ch->uart_port.state->port; in neo_copy_data_from_queue_to_uart()
491 if (kfifo_is_empty(&tport->xmit_fifo)) in neo_copy_data_from_queue_to_uart()
495 if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING)) in neo_copy_data_from_queue_to_uart()
500 if (!(ch->ch_flags & CH_FIFO_ENABLED)) { in neo_copy_data_from_queue_to_uart()
501 u8 lsrbits = readb(&ch->ch_neo_uart->lsr); in neo_copy_data_from_queue_to_uart()
503 ch->ch_cached_lsr |= lsrbits; in neo_copy_data_from_queue_to_uart()
504 if (ch->ch_cached_lsr & UART_LSR_THRE) { in neo_copy_data_from_queue_to_uart()
505 ch->ch_cached_lsr &= ~(UART_LSR_THRE); in neo_copy_data_from_queue_to_uart()
507 WARN_ON_ONCE(!kfifo_get(&tport->xmit_fifo, &c)); in neo_copy_data_from_queue_to_uart()
508 writeb(c, &ch->ch_neo_uart->txrx); in neo_copy_data_from_queue_to_uart()
509 jsm_dbg(WRITE, &ch->ch_bd->pci_dev, "Tx data: %x\n", c); in neo_copy_data_from_queue_to_uart()
510 ch->ch_txcount++; in neo_copy_data_from_queue_to_uart()
518 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM))) in neo_copy_data_from_queue_to_uart()
521 n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel; in neo_copy_data_from_queue_to_uart()
522 qlen = kfifo_len(&tport->xmit_fifo); in neo_copy_data_from_queue_to_uart()
528 s = kfifo_out_linear_ptr(&tport->xmit_fifo, &tail, n); in neo_copy_data_from_queue_to_uart()
532 memcpy_toio(&ch->ch_neo_uart->txrxburst, tail, s); in neo_copy_data_from_queue_to_uart()
533 kfifo_skip_count(&tport->xmit_fifo, s); in neo_copy_data_from_queue_to_uart()
534 n -= s; in neo_copy_data_from_queue_to_uart()
535 ch->ch_txcount += s; in neo_copy_data_from_queue_to_uart()
539 if (len_written >= ch->ch_t_tlevel) in neo_copy_data_from_queue_to_uart()
540 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in neo_copy_data_from_queue_to_uart()
542 if (kfifo_is_empty(&tport->xmit_fifo)) in neo_copy_data_from_queue_to_uart()
543 uart_write_wakeup(&ch->uart_port); in neo_copy_data_from_queue_to_uart()
550 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev, in neo_parse_modem()
552 ch->ch_portnum, msignals); in neo_parse_modem()
559 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_DCD); in neo_parse_modem()
561 uart_handle_cts_change(&ch->uart_port, msignals & UART_MSR_CTS); in neo_parse_modem()
563 ch->ch_mistat |= UART_MSR_DCD; in neo_parse_modem()
565 ch->ch_mistat &= ~UART_MSR_DCD; in neo_parse_modem()
568 ch->ch_mistat |= UART_MSR_DSR; in neo_parse_modem()
570 ch->ch_mistat &= ~UART_MSR_DSR; in neo_parse_modem()
573 ch->ch_mistat |= UART_MSR_RI; in neo_parse_modem()
575 ch->ch_mistat &= ~UART_MSR_RI; in neo_parse_modem()
578 ch->ch_mistat |= UART_MSR_CTS; in neo_parse_modem()
580 ch->ch_mistat &= ~UART_MSR_CTS; in neo_parse_modem()
582 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev, in neo_parse_modem()
584 ch->ch_portnum, in neo_parse_modem()
585 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR), in neo_parse_modem()
586 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS), in neo_parse_modem()
587 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS), in neo_parse_modem()
588 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR), in neo_parse_modem()
589 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI), in neo_parse_modem()
590 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD)); in neo_parse_modem()
599 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr); in neo_assert_modem_signals()
602 neo_pci_posting_flush(ch->ch_bd); in neo_assert_modem_signals()
618 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr); in neo_flush_uart_write()
623 tmp = readb(&ch->ch_neo_uart->isr_fcr); in neo_flush_uart_write()
625 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev, in neo_flush_uart_write()
633 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in neo_flush_uart_write()
650 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_neo_uart->isr_fcr); in neo_flush_uart_read()
655 tmp = readb(&ch->ch_neo_uart->isr_fcr); in neo_flush_uart_read()
657 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev, in neo_flush_uart_read()
673 spin_lock_irqsave(&ch->ch_lock, lock_flags); in neo_clear_break()
676 if (ch->ch_flags & CH_BREAK_SENDING) { in neo_clear_break()
677 u8 temp = readb(&ch->ch_neo_uart->lcr); in neo_clear_break()
678 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr); in neo_clear_break()
680 ch->ch_flags &= ~(CH_BREAK_SENDING); in neo_clear_break()
681 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev, in neo_clear_break()
686 neo_pci_posting_flush(ch->ch_bd); in neo_clear_break()
688 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); in neo_clear_break()
704 if (port >= brd->maxports) in neo_parse_isr()
707 ch = brd->channels[port]; in neo_parse_isr()
714 isr = readb(&ch->ch_neo_uart->isr_fcr); in neo_parse_isr()
725 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d isr: %x\n", in neo_parse_isr()
729 /* Read data from uart -> queue */ in neo_parse_isr()
733 spin_lock_irqsave(&ch->ch_lock, lock_flags); in neo_parse_isr()
735 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); in neo_parse_isr()
739 /* Transfer data (if any) from Write Queue -> UART. */ in neo_parse_isr()
740 spin_lock_irqsave(&ch->ch_lock, lock_flags); in neo_parse_isr()
741 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in neo_parse_isr()
742 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); in neo_parse_isr()
747 cause = readb(&ch->ch_neo_uart->xoffchar1); in neo_parse_isr()
749 jsm_dbg(INTR, &ch->ch_bd->pci_dev, in neo_parse_isr()
758 spin_lock_irqsave(&ch->ch_lock, lock_flags); in neo_parse_isr()
761 if (brd->channels[port]->ch_flags & CH_STOP) { in neo_parse_isr()
762 ch->ch_flags &= ~(CH_STOP); in neo_parse_isr()
764 jsm_dbg(INTR, &ch->ch_bd->pci_dev, in neo_parse_isr()
769 if (!(brd->channels[port]->ch_flags & CH_STOP)) { in neo_parse_isr()
770 ch->ch_flags |= CH_STOP; in neo_parse_isr()
771 jsm_dbg(INTR, &ch->ch_bd->pci_dev, in neo_parse_isr()
774 jsm_dbg(INTR, &ch->ch_bd->pci_dev, in neo_parse_isr()
778 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); in neo_parse_isr()
783 * If we get here, this means the hardware is doing auto flow control. in neo_parse_isr()
786 cause = readb(&ch->ch_neo_uart->mcr); in neo_parse_isr()
788 /* Which pin is doing auto flow? RTS or DTR? */ in neo_parse_isr()
789 spin_lock_irqsave(&ch->ch_lock, lock_flags); in neo_parse_isr()
792 ch->ch_mostat |= UART_MCR_RTS; in neo_parse_isr()
794 ch->ch_mostat &= ~(UART_MCR_RTS); in neo_parse_isr()
797 ch->ch_mostat |= UART_MCR_DTR; in neo_parse_isr()
799 ch->ch_mostat &= ~(UART_MCR_DTR); in neo_parse_isr()
801 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); in neo_parse_isr()
805 jsm_dbg(INTR, &ch->ch_bd->pci_dev, in neo_parse_isr()
807 uart_port_lock_irqsave(&ch->uart_port, &lock_flags); in neo_parse_isr()
808 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr)); in neo_parse_isr()
809 uart_port_unlock_irqrestore(&ch->uart_port, lock_flags); in neo_parse_isr()
822 if (port >= brd->maxports) in neo_parse_lsr()
825 ch = brd->channels[port]; in neo_parse_lsr()
829 linestatus = readb(&ch->ch_neo_uart->lsr); in neo_parse_lsr()
831 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d port: %d linestatus: %x\n", in neo_parse_lsr()
834 ch->ch_cached_lsr |= linestatus; in neo_parse_lsr()
836 if (ch->ch_cached_lsr & UART_LSR_DR) { in neo_parse_lsr()
837 /* Read data from uart -> queue */ in neo_parse_lsr()
839 spin_lock_irqsave(&ch->ch_lock, lock_flags); in neo_parse_lsr()
841 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); in neo_parse_lsr()
851 jsm_dbg(INTR, &ch->ch_bd->pci_dev, in neo_parse_lsr()
861 ch->ch_err_parity++; in neo_parse_lsr()
862 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d Port: %d. PAR ERR!\n", in neo_parse_lsr()
867 ch->ch_err_frame++; in neo_parse_lsr()
868 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d Port: %d. FRM ERR!\n", in neo_parse_lsr()
873 ch->ch_err_break++; in neo_parse_lsr()
874 jsm_dbg(INTR, &ch->ch_bd->pci_dev, in neo_parse_lsr()
886 ch->ch_err_overrun++; in neo_parse_lsr()
887 jsm_dbg(INTR, &ch->ch_bd->pci_dev, in neo_parse_lsr()
893 spin_lock_irqsave(&ch->ch_lock, lock_flags); in neo_parse_lsr()
894 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in neo_parse_lsr()
895 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); in neo_parse_lsr()
897 /* Transfer data (if any) from Write Queue -> UART. */ in neo_parse_lsr()
901 spin_lock_irqsave(&ch->ch_lock, lock_flags); in neo_parse_lsr()
902 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in neo_parse_lsr()
903 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); in neo_parse_lsr()
905 /* Transfer data (if any) from Write Queue -> UART. */ in neo_parse_lsr()
918 u32 baud; in neo_param() local
922 bd = ch->ch_bd; in neo_param()
927 * If baud rate is zero, flush queues, and set mval to drop DTR. in neo_param()
929 if ((ch->ch_c_cflag & CBAUD) == B0) { in neo_param()
930 ch->ch_r_head = ch->ch_r_tail = 0; in neo_param()
931 ch->ch_e_head = ch->ch_e_tail = 0; in neo_param()
936 ch->ch_flags |= (CH_BAUD0); in neo_param()
937 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR); in neo_param()
969 cflag = C_BAUD(ch->uart_port.state->port.tty); in neo_param()
970 baud = 9600; in neo_param()
973 baud = baud_rates[i].rate; in neo_param()
978 if (ch->ch_flags & CH_BAUD0) in neo_param()
979 ch->ch_flags &= ~(CH_BAUD0); in neo_param()
982 if (ch->ch_c_cflag & PARENB) in neo_param()
985 if (!(ch->ch_c_cflag & PARODD)) in neo_param()
988 if (ch->ch_c_cflag & CMSPAR) in neo_param()
991 if (ch->ch_c_cflag & CSTOPB) in neo_param()
994 lcr |= UART_LCR_WLEN(tty_get_char_size(ch->ch_c_cflag)); in neo_param()
996 ier = readb(&ch->ch_neo_uart->ier); in neo_param()
997 uart_lcr = readb(&ch->ch_neo_uart->lcr); in neo_param()
999 quot = ch->ch_bd->bd_dividend / baud; in neo_param()
1002 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr); in neo_param()
1003 writeb((quot & 0xff), &ch->ch_neo_uart->txrx); in neo_param()
1004 writeb((quot >> 8), &ch->ch_neo_uart->ier); in neo_param()
1005 writeb(lcr, &ch->ch_neo_uart->lcr); in neo_param()
1009 writeb(lcr, &ch->ch_neo_uart->lcr); in neo_param()
1011 if (ch->ch_c_cflag & CREAD) in neo_param()
1016 writeb(ier, &ch->ch_neo_uart->ier); in neo_param()
1021 if (ch->ch_c_cflag & CRTSCTS) in neo_param()
1023 else if (ch->ch_c_iflag & IXON) { in neo_param()
1025 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR)) in neo_param()
1033 if (ch->ch_c_cflag & CRTSCTS) in neo_param()
1035 else if (ch->ch_c_iflag & IXOFF) { in neo_param()
1037 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR)) in neo_param()
1045 * Adjust the RX FIFO Trigger level if baud is less than 9600. in neo_param()
1047 * delay on firing off the RX FIFO interrupt on slower baud rates. in neo_param()
1049 if (baud < 9600) { in neo_param()
1050 writeb(1, &ch->ch_neo_uart->rfifo); in neo_param()
1051 ch->ch_r_tlevel = 1; in neo_param()
1057 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr)); in neo_param()
1080 spin_lock_irqsave(&brd->bd_intr_lock, lock_flags); in neo_intr()
1084 * Bits 0-7: What port triggered the interrupt. in neo_intr()
1085 * Bits 8-31: Each 3bits indicate what type of interrupt occurred. in neo_intr()
1087 uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET); in neo_intr()
1089 jsm_dbg(INTR, &brd->pci_dev, "%s:%d uart_poll: %x\n", in neo_intr()
1093 jsm_dbg(INTR, &brd->pci_dev, in neo_intr()
1095 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags); in neo_intr()
1119 jsm_dbg(INTR, &brd->pci_dev, "%s:%d port: %x type: %x\n", in neo_intr()
1127 jsm_dbg(INTR, &brd->pci_dev, in neo_intr()
1137 * RXRDY Time-out is cleared by reading data in the in neo_intr()
1142 if (port >= brd->nasync) in neo_intr()
1145 ch = brd->channels[port]; in neo_intr()
1152 spin_lock_irqsave(&ch->ch_lock, lock_flags2); in neo_intr()
1154 spin_unlock_irqrestore(&ch->ch_lock, lock_flags2); in neo_intr()
1195 jsm_dbg(INTR, &brd->pci_dev, in neo_intr()
1202 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags); in neo_intr()
1204 jsm_dbg(INTR, &brd->pci_dev, "finish\n"); in neo_intr()
1215 u8 tmp = readb(&ch->ch_neo_uart->ier); in neo_disable_receiver()
1217 writeb(tmp, &ch->ch_neo_uart->ier); in neo_disable_receiver()
1220 neo_pci_posting_flush(ch->ch_bd); in neo_disable_receiver()
1226 * Used as a way to un-enforce queue flow control when in
1231 u8 tmp = readb(&ch->ch_neo_uart->ier); in neo_enable_receiver()
1233 writeb(tmp, &ch->ch_neo_uart->ier); in neo_enable_receiver()
1236 neo_pci_posting_flush(ch->ch_bd); in neo_enable_receiver()
1244 if (ch->ch_startc != __DISABLED_CHAR) { in neo_send_start_character()
1245 ch->ch_xon_sends++; in neo_send_start_character()
1246 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx); in neo_send_start_character()
1249 neo_pci_posting_flush(ch->ch_bd); in neo_send_start_character()
1258 if (ch->ch_stopc != __DISABLED_CHAR) { in neo_send_stop_character()
1259 ch->ch_xoff_sends++; in neo_send_stop_character()
1260 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx); in neo_send_stop_character()
1263 neo_pci_posting_flush(ch->ch_bd); in neo_send_stop_character()
1272 writeb(0, &ch->ch_neo_uart->ier); in neo_uart_init()
1273 writeb(0, &ch->ch_neo_uart->efr); in neo_uart_init()
1274 writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr); in neo_uart_init()
1277 readb(&ch->ch_neo_uart->txrx); in neo_uart_init()
1278 writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr); in neo_uart_init()
1279 readb(&ch->ch_neo_uart->lsr); in neo_uart_init()
1280 readb(&ch->ch_neo_uart->msr); in neo_uart_init()
1282 ch->ch_flags |= CH_FIFO_ENABLED; in neo_uart_init()
1285 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr); in neo_uart_init()
1294 writeb(0, &ch->ch_neo_uart->efr); in neo_uart_off()
1297 writeb(0, &ch->ch_neo_uart->ier); in neo_uart_off()
1310 if (!(ch->ch_flags & CH_BREAK_SENDING)) { in neo_send_break()
1311 u8 temp = readb(&ch->ch_neo_uart->lcr); in neo_send_break()
1312 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr); in neo_send_break()
1313 ch->ch_flags |= (CH_BREAK_SENDING); in neo_send_break()
1316 neo_pci_posting_flush(ch->ch_bd); in neo_send_break()