1 // SPDX-License-Identifier: GPL-2.0+
54 	u8 lcrb = readb(&ch->ch_cls_uart->lcr);  in cls_set_cts_flow_control()
55 	u8 ier = readb(&ch->ch_cls_uart->ier);  in cls_set_cts_flow_control()
60 	 * the Line Control Register is set to 0xBFh.  in cls_set_cts_flow_control()
62 	writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);  in cls_set_cts_flow_control()
64 	isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);  in cls_set_cts_flow_control()
66 	/* Turn on CTS flow control, turn off IXON flow control */  in cls_set_cts_flow_control()
70 	writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);  in cls_set_cts_flow_control()
73 	writeb(lcrb, &ch->ch_cls_uart->lcr);  in cls_set_cts_flow_control()
76 	 * Enable interrupts for CTS flow, turn off interrupts for  in cls_set_cts_flow_control()
81 	writeb(ier, &ch->ch_cls_uart->ier);  in cls_set_cts_flow_control()
84 	writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);  in cls_set_cts_flow_control()
88 		&ch->ch_cls_uart->isr_fcr);  in cls_set_cts_flow_control()
90 	ch->ch_t_tlevel = 16;  in cls_set_cts_flow_control()
95 	u8 lcrb = readb(&ch->ch_cls_uart->lcr);  in cls_set_ixon_flow_control()
96 	u8 ier = readb(&ch->ch_cls_uart->ier);  in cls_set_ixon_flow_control()
101 	 * the Line Control Register is set to 0xBFh.  in cls_set_ixon_flow_control()
103 	writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);  in cls_set_ixon_flow_control()
105 	isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);  in cls_set_ixon_flow_control()
107 	/* Turn on IXON flow control, turn off CTS flow control */  in cls_set_ixon_flow_control()
111 	writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);  in cls_set_ixon_flow_control()
114 	writeb(ch->ch_startc, &ch->ch_cls_uart->mcr);  in cls_set_ixon_flow_control()
115 	writeb(0, &ch->ch_cls_uart->lsr);  in cls_set_ixon_flow_control()
116 	writeb(ch->ch_stopc, &ch->ch_cls_uart->msr);  in cls_set_ixon_flow_control()
117 	writeb(0, &ch->ch_cls_uart->spr);  in cls_set_ixon_flow_control()
120 	writeb(lcrb, &ch->ch_cls_uart->lcr);  in cls_set_ixon_flow_control()
123 	 * Disable interrupts for CTS flow, turn on interrupts for  in cls_set_ixon_flow_control()
128 	writeb(ier, &ch->ch_cls_uart->ier);  in cls_set_ixon_flow_control()
131 	writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);  in cls_set_ixon_flow_control()
135 		&ch->ch_cls_uart->isr_fcr);  in cls_set_ixon_flow_control()
140 	u8 lcrb = readb(&ch->ch_cls_uart->lcr);  in cls_set_no_output_flow_control()
141 	u8 ier = readb(&ch->ch_cls_uart->ier);  in cls_set_no_output_flow_control()
146 	 * the Line Control Register is set to 0xBFh.  in cls_set_no_output_flow_control()
148 	writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);  in cls_set_no_output_flow_control()
150 	isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);  in cls_set_no_output_flow_control()
152 	/* Turn off IXON flow control, turn off CTS flow control */  in cls_set_no_output_flow_control()
156 	writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);  in cls_set_no_output_flow_control()
159 	writeb(lcrb, &ch->ch_cls_uart->lcr);  in cls_set_no_output_flow_control()
162 	 * Disable interrupts for CTS flow, turn off interrupts for  in cls_set_no_output_flow_control()
167 	writeb(ier, &ch->ch_cls_uart->ier);  in cls_set_no_output_flow_control()
170 	writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);  in cls_set_no_output_flow_control()
174 		&ch->ch_cls_uart->isr_fcr);  in cls_set_no_output_flow_control()
176 	ch->ch_r_watermark = 0;  in cls_set_no_output_flow_control()
177 	ch->ch_t_tlevel = 16;  in cls_set_no_output_flow_control()
178 	ch->ch_r_tlevel = 16;  in cls_set_no_output_flow_control()
183 	u8 lcrb = readb(&ch->ch_cls_uart->lcr);  in cls_set_rts_flow_control()
184 	u8 ier = readb(&ch->ch_cls_uart->ier);  in cls_set_rts_flow_control()
189 	 * the Line Control Register is set to 0xBFh.  in cls_set_rts_flow_control()
191 	writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);  in cls_set_rts_flow_control()
193 	isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);  in cls_set_rts_flow_control()
195 	/* Turn on RTS flow control, turn off IXOFF flow control */  in cls_set_rts_flow_control()
199 	writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);  in cls_set_rts_flow_control()
202 	writeb(lcrb, &ch->ch_cls_uart->lcr);  in cls_set_rts_flow_control()
204 	/* Enable interrupts for RTS flow */  in cls_set_rts_flow_control()
206 	writeb(ier, &ch->ch_cls_uart->ier);  in cls_set_rts_flow_control()
209 	writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);  in cls_set_rts_flow_control()
213 		&ch->ch_cls_uart->isr_fcr);  in cls_set_rts_flow_control()
215 	ch->ch_r_watermark = 4;  in cls_set_rts_flow_control()
216 	ch->ch_r_tlevel = 8;  in cls_set_rts_flow_control()
221 	u8 lcrb = readb(&ch->ch_cls_uart->lcr);  in cls_set_ixoff_flow_control()
222 	u8 ier = readb(&ch->ch_cls_uart->ier);  in cls_set_ixoff_flow_control()
227 	 * the Line Control Register is set to 0xBFh.  in cls_set_ixoff_flow_control()
229 	writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);  in cls_set_ixoff_flow_control()
231 	isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);  in cls_set_ixoff_flow_control()
233 	/* Turn on IXOFF flow control, turn off RTS flow control */  in cls_set_ixoff_flow_control()
237 	writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);  in cls_set_ixoff_flow_control()
240 	writeb(ch->ch_startc, &ch->ch_cls_uart->mcr);  in cls_set_ixoff_flow_control()
241 	writeb(0, &ch->ch_cls_uart->lsr);  in cls_set_ixoff_flow_control()
242 	writeb(ch->ch_stopc, &ch->ch_cls_uart->msr);  in cls_set_ixoff_flow_control()
243 	writeb(0, &ch->ch_cls_uart->spr);  in cls_set_ixoff_flow_control()
246 	writeb(lcrb, &ch->ch_cls_uart->lcr);  in cls_set_ixoff_flow_control()
248 	/* Disable interrupts for RTS flow */  in cls_set_ixoff_flow_control()
250 	writeb(ier, &ch->ch_cls_uart->ier);  in cls_set_ixoff_flow_control()
253 	writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);  in cls_set_ixoff_flow_control()
257 		&ch->ch_cls_uart->isr_fcr);  in cls_set_ixoff_flow_control()
262 	u8 lcrb = readb(&ch->ch_cls_uart->lcr);  in cls_set_no_input_flow_control()
263 	u8 ier = readb(&ch->ch_cls_uart->ier);  in cls_set_no_input_flow_control()
268 	 * the Line Control Register is set to 0xBFh.  in cls_set_no_input_flow_control()
270 	writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);  in cls_set_no_input_flow_control()
272 	isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);  in cls_set_no_input_flow_control()
274 	/* Turn off IXOFF flow control, turn off RTS flow control */  in cls_set_no_input_flow_control()
278 	writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);  in cls_set_no_input_flow_control()
281 	writeb(lcrb, &ch->ch_cls_uart->lcr);  in cls_set_no_input_flow_control()
283 	/* Disable interrupts for RTS flow */  in cls_set_no_input_flow_control()
285 	writeb(ier, &ch->ch_cls_uart->ier);  in cls_set_no_input_flow_control()
288 	writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);  in cls_set_no_input_flow_control()
292 		&ch->ch_cls_uart->isr_fcr);  in cls_set_no_input_flow_control()
294 	ch->ch_t_tlevel = 16;  in cls_set_no_input_flow_control()
295 	ch->ch_r_tlevel = 16;  in cls_set_no_input_flow_control()
309 	spin_lock_irqsave(&ch->ch_lock, lock_flags);  in cls_clear_break()
312 	if (ch->ch_flags & CH_BREAK_SENDING) {  in cls_clear_break()
313 		u8 temp = readb(&ch->ch_cls_uart->lcr);  in cls_clear_break()
315 		writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr);  in cls_clear_break()
317 		ch->ch_flags &= ~(CH_BREAK_SENDING);  in cls_clear_break()
318 		jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,  in cls_clear_break()
322 	spin_unlock_irqrestore(&ch->ch_lock, lock_flags);  in cls_clear_break()
327 	u8 tmp = readb(&ch->ch_cls_uart->ier);  in cls_disable_receiver()
330 	writeb(tmp, &ch->ch_cls_uart->ier);  in cls_disable_receiver()
335 	u8 tmp = readb(&ch->ch_cls_uart->ier);  in cls_enable_receiver()
338 	writeb(tmp, &ch->ch_cls_uart->ier);  in cls_enable_receiver()
347 	writeb(ch->ch_mostat, &ch->ch_cls_uart->mcr);  in cls_assert_modem_signals()
362 	spin_lock_irqsave(&ch->ch_lock, flags);  in cls_copy_data_from_uart_to_queue()
365 	head = ch->ch_r_head & RQUEUEMASK;  in cls_copy_data_from_uart_to_queue()
366 	tail = ch->ch_r_tail & RQUEUEMASK;  in cls_copy_data_from_uart_to_queue()
368 	ch->ch_cached_lsr = 0;  in cls_copy_data_from_uart_to_queue()
371 	qleft = tail - head - 1;  in cls_copy_data_from_uart_to_queue()
379 	if (ch->ch_c_iflag & IGNBRK)  in cls_copy_data_from_uart_to_queue()
387 		linestatus = readb(&ch->ch_cls_uart->lsr);  in cls_copy_data_from_uart_to_queue()
398 			readb(&ch->ch_cls_uart->txrx);  in cls_copy_data_from_uart_to_queue()
412 			ch->ch_r_tail = tail;  in cls_copy_data_from_uart_to_queue()
413 			ch->ch_err_overrun++;  in cls_copy_data_from_uart_to_queue()
417 		ch->ch_equeue[head] = linestatus & (UART_LSR_BI | UART_LSR_PE  in cls_copy_data_from_uart_to_queue()
419 		ch->ch_rqueue[head] = readb(&ch->ch_cls_uart->txrx);  in cls_copy_data_from_uart_to_queue()
421 		qleft--;  in cls_copy_data_from_uart_to_queue()
423 		if (ch->ch_equeue[head] & UART_LSR_PE)  in cls_copy_data_from_uart_to_queue()
424 			ch->ch_err_parity++;  in cls_copy_data_from_uart_to_queue()
425 		if (ch->ch_equeue[head] & UART_LSR_BI)  in cls_copy_data_from_uart_to_queue()
426 			ch->ch_err_break++;  in cls_copy_data_from_uart_to_queue()
427 		if (ch->ch_equeue[head] & UART_LSR_FE)  in cls_copy_data_from_uart_to_queue()
428 			ch->ch_err_frame++;  in cls_copy_data_from_uart_to_queue()
432 		ch->ch_rxcount++;  in cls_copy_data_from_uart_to_queue()
438 	ch->ch_r_head = head & RQUEUEMASK;  in cls_copy_data_from_uart_to_queue()
439 	ch->ch_e_head = head & EQUEUEMASK;  in cls_copy_data_from_uart_to_queue()
441 	spin_unlock_irqrestore(&ch->ch_lock, flags);  in cls_copy_data_from_uart_to_queue()
453 	tport = &ch->uart_port.state->port;  in cls_copy_data_from_queue_to_uart()
456 	if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING))  in cls_copy_data_from_queue_to_uart()
460 	if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))  in cls_copy_data_from_queue_to_uart()
467 		if (!kfifo_get(&tport->xmit_fifo, &c))  in cls_copy_data_from_queue_to_uart()
470 		writeb(c, &ch->ch_cls_uart->txrx);  in cls_copy_data_from_queue_to_uart()
471 		n--;  in cls_copy_data_from_queue_to_uart()
472 		ch->ch_txcount++;  in cls_copy_data_from_queue_to_uart()
476 	if (len_written > ch->ch_t_tlevel)  in cls_copy_data_from_queue_to_uart()
477 		ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);  in cls_copy_data_from_queue_to_uart()
479 	if (kfifo_is_empty(&tport->xmit_fifo))  in cls_copy_data_from_queue_to_uart()
480 		uart_write_wakeup(&ch->uart_port);  in cls_copy_data_from_queue_to_uart()
487 	jsm_dbg(MSIGS, &ch->ch_bd->pci_dev,  in cls_parse_modem()
489 		ch->ch_portnum, msignals);  in cls_parse_modem()
499 		uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_DCD);  in cls_parse_modem()
501 		uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_CTS);  in cls_parse_modem()
504 		ch->ch_mistat |= UART_MSR_DCD;  in cls_parse_modem()
506 		ch->ch_mistat &= ~UART_MSR_DCD;  in cls_parse_modem()
509 		ch->ch_mistat |= UART_MSR_DSR;  in cls_parse_modem()
511 		ch->ch_mistat &= ~UART_MSR_DSR;  in cls_parse_modem()
514 		ch->ch_mistat |= UART_MSR_RI;  in cls_parse_modem()
516 		ch->ch_mistat &= ~UART_MSR_RI;  in cls_parse_modem()
519 		ch->ch_mistat |= UART_MSR_CTS;  in cls_parse_modem()
521 		ch->ch_mistat &= ~UART_MSR_CTS;  in cls_parse_modem()
523 	jsm_dbg(MSIGS, &ch->ch_bd->pci_dev,  in cls_parse_modem()
525 		ch->ch_portnum,  in cls_parse_modem()
526 		!!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR),  in cls_parse_modem()
527 		!!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS),  in cls_parse_modem()
528 		!!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS),  in cls_parse_modem()
529 		!!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR),  in cls_parse_modem()
530 		!!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI),  in cls_parse_modem()
531 		!!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD));  in cls_parse_modem()
546 	if (port >= brd->nasync)  in cls_parse_isr()
549 	ch = brd->channels[port];  in cls_parse_isr()
555 		isr = readb(&ch->ch_cls_uart->isr_fcr);  in cls_parse_isr()
563 			/* Read data from uart -> queue */  in cls_parse_isr()
570 			/* Transfer data (if any) from Write Queue -> UART. */  in cls_parse_isr()
571 			spin_lock_irqsave(&ch->ch_lock, flags);  in cls_parse_isr()
572 			ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);  in cls_parse_isr()
573 			spin_unlock_irqrestore(&ch->ch_lock, flags);  in cls_parse_isr()
584 		cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr));  in cls_parse_isr()
598 						&ch->ch_cls_uart->isr_fcr);  in cls_flush_uart_write()
602 		tmp = readb(&ch->ch_cls_uart->isr_fcr);  in cls_flush_uart_write()
604 			jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,  in cls_flush_uart_write()
611 	ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);  in cls_flush_uart_write()
639 	if (ch->ch_startc != __DISABLED_CHAR) {  in cls_send_start_character()
640 		ch->ch_xon_sends++;  in cls_send_start_character()
641 		writeb(ch->ch_startc, &ch->ch_cls_uart->txrx);  in cls_send_start_character()
650 	if (ch->ch_stopc != __DISABLED_CHAR) {  in cls_send_stop_character()
651 		ch->ch_xoff_sends++;  in cls_send_stop_character()
652 		writeb(ch->ch_stopc, &ch->ch_cls_uart->txrx);  in cls_send_stop_character()
671 	bd = ch->ch_bd;  in cls_param()
678 	if ((ch->ch_c_cflag & CBAUD) == B0) {  in cls_param()
679 		ch->ch_r_head = 0;  in cls_param()
680 		ch->ch_r_tail = 0;  in cls_param()
681 		ch->ch_e_head = 0;  in cls_param()
682 		ch->ch_e_tail = 0;  in cls_param()
688 		ch->ch_flags |= (CH_BAUD0);  in cls_param()
689 		ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);  in cls_param()
694 	cflag = C_BAUD(ch->uart_port.state->port.tty);  in cls_param()
703 	if (ch->ch_flags & CH_BAUD0)  in cls_param()
704 		ch->ch_flags &= ~(CH_BAUD0);  in cls_param()
706 	if (ch->ch_c_cflag & PARENB)  in cls_param()
709 	if (!(ch->ch_c_cflag & PARODD))  in cls_param()
712 	if (ch->ch_c_cflag & CMSPAR)  in cls_param()
715 	if (ch->ch_c_cflag & CSTOPB)  in cls_param()
718 	lcr |= UART_LCR_WLEN(tty_get_char_size(ch->ch_c_cflag));  in cls_param()
720 	ier = readb(&ch->ch_cls_uart->ier);  in cls_param()
721 	uart_lcr = readb(&ch->ch_cls_uart->lcr);  in cls_param()
723 	quot = ch->ch_bd->bd_dividend / baud;  in cls_param()
726 		writeb(UART_LCR_DLAB, &ch->ch_cls_uart->lcr);  in cls_param()
727 		writeb((quot & 0xff), &ch->ch_cls_uart->txrx);  in cls_param()
728 		writeb((quot >> 8), &ch->ch_cls_uart->ier);  in cls_param()
729 		writeb(lcr, &ch->ch_cls_uart->lcr);  in cls_param()
733 		writeb(lcr, &ch->ch_cls_uart->lcr);  in cls_param()
735 	if (ch->ch_c_cflag & CREAD)  in cls_param()
740 	writeb(ier, &ch->ch_cls_uart->ier);  in cls_param()
742 	if (ch->ch_c_cflag & CRTSCTS)  in cls_param()
744 	else if (ch->ch_c_iflag & IXON) {  in cls_param()
747 		 * then we should disable flow control.  in cls_param()
749 		if ((ch->ch_startc == __DISABLED_CHAR) ||  in cls_param()
750 			(ch->ch_stopc == __DISABLED_CHAR))  in cls_param()
757 	if (ch->ch_c_cflag & CRTSCTS)  in cls_param()
759 	else if (ch->ch_c_iflag & IXOFF) {  in cls_param()
762 		 * then we should disable flow control.  in cls_param()
764 		if ((ch->ch_startc == __DISABLED_CHAR) ||  in cls_param()
765 			(ch->ch_stopc == __DISABLED_CHAR))  in cls_param()
775 	cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr));  in cls_param()
791 	spin_lock_irqsave(&brd->bd_intr_lock, lock_flags);  in cls_intr()
797 	uart_poll = readb(brd->re_map_membase + UART_CLASSIC_POLL_ADDR_OFFSET);  in cls_intr()
799 	jsm_dbg(INTR, &brd->pci_dev, "%s:%d uart_poll: %x\n",  in cls_intr()
803 		jsm_dbg(INTR, &brd->pci_dev,  in cls_intr()
805 		spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags);  in cls_intr()
812 	for (i = 0; i < brd->nasync; i++)  in cls_intr()
815 	spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags);  in cls_intr()
823 	unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);  in cls_uart_init()
826 	writeb(0, &ch->ch_cls_uart->ier);  in cls_uart_init()
830 	 * the Line Control Register is set to 0xBFh.  in cls_uart_init()
832 	writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);  in cls_uart_init()
834 	isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);  in cls_uart_init()
839 	writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);  in cls_uart_init()
842 	writeb(lcrb, &ch->ch_cls_uart->lcr);  in cls_uart_init()
845 	readb(&ch->ch_cls_uart->txrx);  in cls_uart_init()
848 						 &ch->ch_cls_uart->isr_fcr);  in cls_uart_init()
851 	ch->ch_flags |= (CH_FIFO_ENABLED | CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);  in cls_uart_init()
853 	readb(&ch->ch_cls_uart->lsr);  in cls_uart_init()
854 	readb(&ch->ch_cls_uart->msr);  in cls_uart_init()
863 	writeb(0, &ch->ch_cls_uart->ier);  in cls_uart_off()
875 	if (!(ch->ch_flags & CH_BREAK_SENDING)) {  in cls_send_break()
876 		u8 temp = readb(&ch->ch_cls_uart->lcr);  in cls_send_break()
878 		writeb((temp | UART_LCR_SBC), &ch->ch_cls_uart->lcr);  in cls_send_break()
879 		ch->ch_flags |= (CH_BREAK_SENDING);  in cls_send_break()