Lines Matching +full:write +full:- +full:1 +full:- +full:bps

1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)  argument
38 /* Write Register 0 */
40 #define	R1	1
69 /* Write Register 1 */
85 /* Write Register #2 (Interrupt Vector) */
87 /* Write Register 3 */
101 /* Write Register 4 */
107 #define	SB1		0x4	/* 1 stop bit/char */
122 /* Write Register 5 */
126 #define	SDLC_CRC	0x4	/* SDLC/CRC-16 */
136 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
138 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
140 /* Write Register 8 (transmit buffer) */
142 /* Write Register 9 (Master interrupt control) */
143 #define	VIS	1	/* Vector Includes Status */
148 #define	NORESET	0	/* No reset on write to R9 */
153 /* Write Register 10 (misc control bits) */
154 #define	BIT6	1	/* 6 bit/8bit sync */
161 #define	FM1	0x40	/* FM1 (transition = 1) */
165 /* Write Register 11 (Clock Mode control) */
167 #define	TRxCTC	1	/* TRxC = Transmit clock */
181 /* Write Register 12 (lower byte of baud rate generator time constant) */
183 /* Write Register 13 (upper byte of baud rate generator time constant) */
185 /* Write Register 14 (Misc control bits) */
186 #define	BRENAB 	1	/* Baud rate generator enable */
199 /* Write Register 15 (external/status interrupt control) */
218 /* Read Register 1 */
227 #define	RES18		0xe	/* 1/8 */
235 /* Read Register 2 (channel b only) - Interrupt vector */
269 #define ZS_CLEARERR(channel)    do { writeb(ERR_RES, &channel->control); \
272 #define ZS_CLEARSTAT(channel)   do { writeb(RES_EXT_INT, &channel->control); \
275 #define ZS_CLEARFIFO(channel)   do { readb(&channel->data); \
277 				     readb(&channel->data); \
279 				     readb(&channel->data); \