Lines Matching +full:auto +full:- +full:baud
1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2012-2014 Freescale Semiconductor, Inc.
14 #include <linux/dma-mapping.h>
30 /* All registers are 8-bit width */
119 /* 32-bit global registers only for i.MX7ULP/i.MX8x
124 /* 32-bit register definition */
246 #define DRIVER_NAME "fsl-lpuart"
339 .rx_watermark = 7, /* A lower watermark is ideal for low baud rates. */
349 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, },
350 { .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, },
351 { .compatible = "fsl,ls1028a-lpuart", .data = &ls1028a_data, },
352 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx7ulp_data, },
353 { .compatible = "fsl,imx8ulp-lpuart", .data = &imx8ulp_data, },
354 { .compatible = "fsl,imx8qxp-lpuart", .data = &imx8qxp_data, },
355 { .compatible = "fsl,imxrt1050-lpuart", .data = &imxrt1050_data},
365 return (sport->devtype == LS1021A_LPUART || in is_layerscape_lpuart()
366 sport->devtype == LS1028A_LPUART); in is_layerscape_lpuart()
371 return sport->devtype == IMX7ULP_LPUART; in is_imx7ulp_lpuart()
376 return sport->devtype == IMX8ULP_LPUART; in is_imx8ulp_lpuart()
381 return sport->devtype == IMX8QXP_LPUART; in is_imx8qxp_lpuart()
386 switch (port->iotype) { in lpuart32_read()
388 return readl(port->membase + off); in lpuart32_read()
390 return ioread32be(port->membase + off); in lpuart32_read()
399 switch (port->iotype) { in lpuart32_write()
401 writel(val, port->membase + off); in lpuart32_write()
404 iowrite32be(val, port->membase + off); in lpuart32_write()
414 ret = clk_prepare_enable(sport->ipg_clk); in __lpuart_enable_clks()
418 ret = clk_prepare_enable(sport->baud_clk); in __lpuart_enable_clks()
420 clk_disable_unprepare(sport->ipg_clk); in __lpuart_enable_clks()
424 clk_disable_unprepare(sport->baud_clk); in __lpuart_enable_clks()
425 clk_disable_unprepare(sport->ipg_clk); in __lpuart_enable_clks()
434 return clk_get_rate(sport->baud_clk); in lpuart_get_baud_clk_rate()
436 return clk_get_rate(sport->ipg_clk); in lpuart_get_baud_clk_rate()
446 temp = readb(port->membase + UARTCR2); in lpuart_stop_tx()
448 writeb(temp, port->membase + UARTCR2); in lpuart_stop_tx()
464 temp = readb(port->membase + UARTCR2); in lpuart_stop_rx()
465 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); in lpuart_stop_rx()
478 struct tty_port *tport = &sport->port.state->port; in lpuart_dma_tx()
479 struct scatterlist *sgl = sport->tx_sgl; in lpuart_dma_tx()
480 struct device *dev = sport->port.dev; in lpuart_dma_tx()
481 struct dma_chan *chan = sport->dma_tx_chan; in lpuart_dma_tx()
484 if (sport->dma_tx_in_progress) in lpuart_dma_tx()
487 sg_init_table(sgl, ARRAY_SIZE(sport->tx_sgl)); in lpuart_dma_tx()
488 sport->dma_tx_bytes = kfifo_len(&tport->xmit_fifo); in lpuart_dma_tx()
489 sport->dma_tx_nents = kfifo_dma_out_prepare(&tport->xmit_fifo, sgl, in lpuart_dma_tx()
490 ARRAY_SIZE(sport->tx_sgl), sport->dma_tx_bytes); in lpuart_dma_tx()
492 ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents, in lpuart_dma_tx()
499 sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl, in lpuart_dma_tx()
502 if (!sport->dma_tx_desc) { in lpuart_dma_tx()
503 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, in lpuart_dma_tx()
509 sport->dma_tx_desc->callback = lpuart_dma_tx_complete; in lpuart_dma_tx()
510 sport->dma_tx_desc->callback_param = sport; in lpuart_dma_tx()
511 sport->dma_tx_in_progress = true; in lpuart_dma_tx()
512 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc); in lpuart_dma_tx()
518 return kfifo_is_empty(&port->state->port.xmit_fifo) || in lpuart_stopped_or_empty()
525 struct scatterlist *sgl = &sport->tx_sgl[0]; in lpuart_dma_tx_complete()
526 struct tty_port *tport = &sport->port.state->port; in lpuart_dma_tx_complete()
527 struct dma_chan *chan = sport->dma_tx_chan; in lpuart_dma_tx_complete()
530 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_dma_tx_complete()
531 if (!sport->dma_tx_in_progress) { in lpuart_dma_tx_complete()
532 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_dma_tx_complete()
536 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, in lpuart_dma_tx_complete()
539 uart_xmit_advance(&sport->port, sport->dma_tx_bytes); in lpuart_dma_tx_complete()
540 sport->dma_tx_in_progress = false; in lpuart_dma_tx_complete()
541 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_dma_tx_complete()
543 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in lpuart_dma_tx_complete()
544 uart_write_wakeup(&sport->port); in lpuart_dma_tx_complete()
546 if (waitqueue_active(&sport->dma_wait)) { in lpuart_dma_tx_complete()
547 wake_up(&sport->dma_wait); in lpuart_dma_tx_complete()
551 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_dma_tx_complete()
553 if (!lpuart_stopped_or_empty(&sport->port)) in lpuart_dma_tx_complete()
556 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_dma_tx_complete()
561 switch (sport->port.iotype) { in lpuart_dma_datareg_addr()
563 return sport->port.mapbase + UARTDATA; in lpuart_dma_datareg_addr()
565 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1; in lpuart_dma_datareg_addr()
567 return sport->port.mapbase + UARTDR; in lpuart_dma_datareg_addr()
581 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig); in lpuart_dma_tx_request()
584 dev_err(port->dev, in lpuart_dma_tx_request()
594 return sport->port.iotype == UPIO_MEM32 || in lpuart_is_32()
595 sport->port.iotype == UPIO_MEM32BE; in lpuart_is_32()
601 struct dma_chan *chan = sport->dma_tx_chan; in lpuart_flush_buffer()
604 if (sport->lpuart_dma_tx_use) { in lpuart_flush_buffer()
605 if (sport->dma_tx_in_progress) { in lpuart_flush_buffer()
606 dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0], in lpuart_flush_buffer()
607 sport->dma_tx_nents, DMA_TO_DEVICE); in lpuart_flush_buffer()
608 sport->dma_tx_in_progress = false; in lpuart_flush_buffer()
618 val = readb(port->membase + UARTCFIFO); in lpuart_flush_buffer()
620 writeb(val, port->membase + UARTCFIFO); in lpuart_flush_buffer()
627 while (!(readb(port->membase + offset) & bit)) in lpuart_wait_bit_set()
645 port->fifosize = 0; in lpuart_poll_init()
649 writeb(0, port->membase + UARTCR2); in lpuart_poll_init()
651 temp = readb(port->membase + UARTPFIFO); in lpuart_poll_init()
654 port->membase + UARTPFIFO); in lpuart_poll_init()
658 port->membase + UARTCFIFO); in lpuart_poll_init()
661 if (readb(port->membase + UARTSR1) & UARTSR1_RDRF) { in lpuart_poll_init()
662 readb(port->membase + UARTDR); in lpuart_poll_init()
663 writeb(UARTSFIFO_RXUF, port->membase + UARTSFIFO); in lpuart_poll_init()
666 writeb(0, port->membase + UARTTWFIFO); in lpuart_poll_init()
667 writeb(1, port->membase + UARTRWFIFO); in lpuart_poll_init()
670 writeb(UARTCR2_RE | UARTCR2_TE, port->membase + UARTCR2); in lpuart_poll_init()
680 writeb(c, port->membase + UARTDR); in lpuart_poll_put_char()
685 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF)) in lpuart_poll_get_char()
688 return readb(port->membase + UARTDR); in lpuart_poll_get_char()
696 port->fifosize = 0; in lpuart32_poll_init()
741 struct uart_port *port = &sport->port; in lpuart_transmit_buffer()
745 readb(port->membase + UARTTCFIFO) < sport->txfifo_size, in lpuart_transmit_buffer()
746 writeb(ch, port->membase + UARTDR)); in lpuart_transmit_buffer()
751 struct tty_port *tport = &sport->port.state->port; in lpuart32_transmit_buffer()
755 if (sport->port.x_char) { in lpuart32_transmit_buffer()
756 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA); in lpuart32_transmit_buffer()
757 sport->port.icount.tx++; in lpuart32_transmit_buffer()
758 sport->port.x_char = 0; in lpuart32_transmit_buffer()
762 if (lpuart_stopped_or_empty(&sport->port)) { in lpuart32_transmit_buffer()
763 lpuart32_stop_tx(&sport->port); in lpuart32_transmit_buffer()
767 txcnt = lpuart32_read(&sport->port, UARTWATER); in lpuart32_transmit_buffer()
770 while (txcnt < sport->txfifo_size && in lpuart32_transmit_buffer()
771 uart_fifo_get(&sport->port, &c)) { in lpuart32_transmit_buffer()
772 lpuart32_write(&sport->port, c, UARTDATA); in lpuart32_transmit_buffer()
773 txcnt = lpuart32_read(&sport->port, UARTWATER); in lpuart32_transmit_buffer()
778 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in lpuart32_transmit_buffer()
779 uart_write_wakeup(&sport->port); in lpuart32_transmit_buffer()
781 if (kfifo_is_empty(&tport->xmit_fifo)) in lpuart32_transmit_buffer()
782 lpuart32_stop_tx(&sport->port); in lpuart32_transmit_buffer()
791 temp = readb(port->membase + UARTCR2); in lpuart_start_tx()
792 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2); in lpuart_start_tx()
794 if (sport->lpuart_dma_tx_use) { in lpuart_start_tx()
798 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE) in lpuart_start_tx()
808 if (sport->lpuart_dma_tx_use) { in lpuart32_start_tx()
825 pm_runtime_mark_last_busy(port->dev); in lpuart_uart_pm()
826 pm_runtime_put_autosuspend(port->dev); in lpuart_uart_pm()
829 pm_runtime_get_sync(port->dev); in lpuart_uart_pm()
839 u8 sr1 = readb(port->membase + UARTSR1); in lpuart_tx_empty()
840 u8 sfifo = readb(port->membase + UARTSFIFO); in lpuart_tx_empty()
842 if (sport->dma_tx_in_progress) in lpuart_tx_empty()
859 if (sport->dma_tx_in_progress) in lpuart32_tx_empty()
875 uart_port_lock(&sport->port); in lpuart_txint()
877 uart_port_unlock(&sport->port); in lpuart_txint()
883 struct tty_port *port = &sport->port.state->port; in lpuart_rxint()
886 uart_port_lock(&sport->port); in lpuart_rxint()
888 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { in lpuart_rxint()
890 sport->port.icount.rx++; in lpuart_rxint()
895 sr = readb(sport->port.membase + UARTSR1); in lpuart_rxint()
896 rx = readb(sport->port.membase + UARTDR); in lpuart_rxint()
898 if (uart_prepare_sysrq_char(&sport->port, rx)) in lpuart_rxint()
903 sport->port.icount.parity++; in lpuart_rxint()
905 sport->port.icount.frame++; in lpuart_rxint()
910 if (sr & sport->port.ignore_status_mask) { in lpuart_rxint()
916 sr &= sport->port.read_status_mask; in lpuart_rxint()
926 sport->port.sysrq = 0; in lpuart_rxint()
930 sport->port.icount.buf_overrun++; in lpuart_rxint()
935 sport->port.icount.overrun += overrun; in lpuart_rxint()
941 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); in lpuart_rxint()
942 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO); in lpuart_rxint()
945 uart_unlock_and_check_sysrq(&sport->port); in lpuart_rxint()
952 uart_port_lock(&sport->port); in lpuart32_txint()
954 uart_port_unlock(&sport->port); in lpuart32_txint()
960 struct tty_port *port = &sport->port.state->port; in lpuart32_rxint()
964 uart_port_lock(&sport->port); in lpuart32_rxint()
966 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) { in lpuart32_rxint()
968 sport->port.icount.rx++; in lpuart32_rxint()
973 sr = lpuart32_read(&sport->port, UARTSTAT); in lpuart32_rxint()
974 rx = lpuart32_read(&sport->port, UARTDATA); in lpuart32_rxint()
983 if (is_break && uart_handle_break(&sport->port)) in lpuart32_rxint()
986 if (uart_prepare_sysrq_char(&sport->port, rx)) in lpuart32_rxint()
991 sport->port.icount.parity++; in lpuart32_rxint()
994 sport->port.icount.brk++; in lpuart32_rxint()
996 sport->port.icount.frame++; in lpuart32_rxint()
1000 sport->port.icount.overrun++; in lpuart32_rxint()
1002 if (sr & sport->port.ignore_status_mask) { in lpuart32_rxint()
1008 sr &= sport->port.read_status_mask; in lpuart32_rxint()
1023 if (sport->is_cs7) in lpuart32_rxint()
1027 sport->port.icount.buf_overrun++; in lpuart32_rxint()
1031 uart_unlock_and_check_sysrq(&sport->port); in lpuart32_rxint()
1041 sts = readb(sport->port.membase + UARTSR1); in lpuart_int()
1044 if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) { in lpuart_int()
1045 readb(sport->port.membase + UARTDR); in lpuart_int()
1046 uart_handle_break(&sport->port); in lpuart_int()
1048 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); in lpuart_int()
1052 if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use) in lpuart_int()
1055 if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use) in lpuart_int()
1064 while (count--) { in lpuart_handle_sysrq_chars()
1073 struct circ_buf *ring = &sport->rx_ring; in lpuart_handle_sysrq()
1076 if (ring->head < ring->tail) { in lpuart_handle_sysrq()
1077 count = sport->rx_sgl.length - ring->tail; in lpuart_handle_sysrq()
1078 lpuart_handle_sysrq_chars(&sport->port, in lpuart_handle_sysrq()
1079 ring->buf + ring->tail, count); in lpuart_handle_sysrq()
1080 ring->tail = 0; in lpuart_handle_sysrq()
1083 if (ring->head > ring->tail) { in lpuart_handle_sysrq()
1084 count = ring->head - ring->tail; in lpuart_handle_sysrq()
1085 lpuart_handle_sysrq_chars(&sport->port, in lpuart_handle_sysrq()
1086 ring->buf + ring->tail, count); in lpuart_handle_sysrq()
1087 ring->tail = ring->head; in lpuart_handle_sysrq()
1104 struct tty_port *port = &sport->port.state->port; in lpuart_copy_rx_to_tty()
1107 struct dma_chan *chan = sport->dma_rx_chan; in lpuart_copy_rx_to_tty()
1108 struct circ_buf *ring = &sport->rx_ring; in lpuart_copy_rx_to_tty()
1113 u32 sr = lpuart32_read(&sport->port, UARTSTAT); in lpuart_copy_rx_to_tty()
1117 lpuart32_write(&sport->port, sr, UARTSTAT); in lpuart_copy_rx_to_tty()
1120 sport->port.icount.parity++; in lpuart_copy_rx_to_tty()
1122 sport->port.icount.frame++; in lpuart_copy_rx_to_tty()
1125 u8 sr = readb(sport->port.membase + UARTSR1); in lpuart_copy_rx_to_tty()
1131 cr2 = readb(sport->port.membase + UARTCR2); in lpuart_copy_rx_to_tty()
1133 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_copy_rx_to_tty()
1136 readb(sport->port.membase + UARTDR); in lpuart_copy_rx_to_tty()
1139 sport->port.icount.parity++; in lpuart_copy_rx_to_tty()
1141 sport->port.icount.frame++; in lpuart_copy_rx_to_tty()
1151 if (readb(sport->port.membase + UARTSFIFO) & in lpuart_copy_rx_to_tty()
1154 sport->port.membase + UARTSFIFO); in lpuart_copy_rx_to_tty()
1156 sport->port.membase + UARTCFIFO); in lpuart_copy_rx_to_tty()
1160 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_copy_rx_to_tty()
1164 async_tx_ack(sport->dma_rx_desc); in lpuart_copy_rx_to_tty()
1166 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_copy_rx_to_tty()
1168 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); in lpuart_copy_rx_to_tty()
1170 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); in lpuart_copy_rx_to_tty()
1171 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_copy_rx_to_tty()
1176 dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1, in lpuart_copy_rx_to_tty()
1180 * ring->head points to the end of data already written by the DMA. in lpuart_copy_rx_to_tty()
1181 * ring->tail points to the beginning of data to be read by the in lpuart_copy_rx_to_tty()
1186 ring->head = sport->rx_sgl.length - state.residue; in lpuart_copy_rx_to_tty()
1187 BUG_ON(ring->head > sport->rx_sgl.length); in lpuart_copy_rx_to_tty()
1192 if (sport->port.sysrq) { in lpuart_copy_rx_to_tty()
1198 * At this point ring->head may point to the first byte right after the in lpuart_copy_rx_to_tty()
1200 * 0 <= ring->head <= sport->rx_sgl.length in lpuart_copy_rx_to_tty()
1202 * However ring->tail must always points inside the dma buffer: in lpuart_copy_rx_to_tty()
1203 * 0 <= ring->tail <= sport->rx_sgl.length - 1 in lpuart_copy_rx_to_tty()
1209 if (ring->head < ring->tail) { in lpuart_copy_rx_to_tty()
1210 count = sport->rx_sgl.length - ring->tail; in lpuart_copy_rx_to_tty()
1212 copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail, in lpuart_copy_rx_to_tty()
1213 count, sport->is_cs7); in lpuart_copy_rx_to_tty()
1215 sport->port.icount.buf_overrun++; in lpuart_copy_rx_to_tty()
1216 ring->tail = 0; in lpuart_copy_rx_to_tty()
1217 sport->port.icount.rx += copied; in lpuart_copy_rx_to_tty()
1221 if (ring->tail < ring->head) { in lpuart_copy_rx_to_tty()
1222 count = ring->head - ring->tail; in lpuart_copy_rx_to_tty()
1223 copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail, in lpuart_copy_rx_to_tty()
1224 count, sport->is_cs7); in lpuart_copy_rx_to_tty()
1226 sport->port.icount.buf_overrun++; in lpuart_copy_rx_to_tty()
1227 /* Wrap ring->head if needed */ in lpuart_copy_rx_to_tty()
1228 if (ring->head >= sport->rx_sgl.length) in lpuart_copy_rx_to_tty()
1229 ring->head = 0; in lpuart_copy_rx_to_tty()
1230 ring->tail = ring->head; in lpuart_copy_rx_to_tty()
1231 sport->port.icount.rx += copied; in lpuart_copy_rx_to_tty()
1234 sport->last_residue = state.residue; in lpuart_copy_rx_to_tty()
1237 dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1, in lpuart_copy_rx_to_tty()
1240 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_copy_rx_to_tty()
1243 if (!sport->dma_idle_int) in lpuart_copy_rx_to_tty()
1244 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout); in lpuart_copy_rx_to_tty()
1257 struct dma_chan *chan = sport->dma_rx_chan; in lpuart32_dma_idleint()
1258 struct circ_buf *ring = &sport->rx_ring; in lpuart32_dma_idleint()
1262 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); in lpuart32_dma_idleint()
1264 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); in lpuart32_dma_idleint()
1268 ring->head = sport->rx_sgl.length - state.residue; in lpuart32_dma_idleint()
1269 count = CIRC_CNT(ring->head, ring->tail, sport->rx_sgl.length); in lpuart32_dma_idleint()
1281 sts = lpuart32_read(&sport->port, UARTSTAT); in lpuart32_int()
1282 rxcount = lpuart32_read(&sport->port, UARTWATER); in lpuart32_int()
1285 if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use) in lpuart32_int()
1288 if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use) in lpuart32_int()
1291 if ((sts & UARTSTAT_IDLE) && sport->lpuart_dma_rx_use && sport->dma_idle_int) in lpuart32_int()
1294 lpuart32_write(&sport->port, sts, UARTSTAT); in lpuart32_int()
1309 struct dma_chan *chan = sport->dma_rx_chan; in lpuart_timer_func()
1310 struct circ_buf *ring = &sport->rx_ring; in lpuart_timer_func()
1315 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); in lpuart_timer_func()
1317 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); in lpuart_timer_func()
1321 ring->head = sport->rx_sgl.length - state.residue; in lpuart_timer_func()
1322 count = CIRC_CNT(ring->head, ring->tail, sport->rx_sgl.length); in lpuart_timer_func()
1325 if ((count != 0) && (sport->last_residue == state.residue)) in lpuart_timer_func()
1328 mod_timer(&sport->lpuart_timer, in lpuart_timer_func()
1329 jiffies + sport->dma_rx_timeout); in lpuart_timer_func()
1331 if (uart_port_trylock_irqsave(&sport->port, &flags)) { in lpuart_timer_func()
1332 sport->last_residue = state.residue; in lpuart_timer_func()
1333 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_timer_func()
1340 struct circ_buf *ring = &sport->rx_ring; in lpuart_start_rx_dma()
1342 struct tty_port *port = &sport->port.state->port; in lpuart_start_rx_dma()
1343 struct tty_struct *tty = port->tty; in lpuart_start_rx_dma()
1344 struct ktermios *termios = &tty->termios; in lpuart_start_rx_dma()
1345 struct dma_chan *chan = sport->dma_rx_chan; in lpuart_start_rx_dma()
1346 unsigned int bits = tty_get_frame_size(termios->c_cflag); in lpuart_start_rx_dma()
1347 unsigned int baud = tty_get_baud_rate(tty); in lpuart_start_rx_dma() local
1351 * 10ms at any baud rate. in lpuart_start_rx_dma()
1353 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2; in lpuart_start_rx_dma()
1354 sport->rx_dma_rng_buf_len = (1 << fls(sport->rx_dma_rng_buf_len)); in lpuart_start_rx_dma()
1355 sport->rx_dma_rng_buf_len = max_t(int, in lpuart_start_rx_dma()
1356 sport->rxfifo_size * 2, in lpuart_start_rx_dma()
1357 sport->rx_dma_rng_buf_len); in lpuart_start_rx_dma()
1362 if (sport->rx_dma_rng_buf_len < 16) in lpuart_start_rx_dma()
1363 sport->rx_dma_rng_buf_len = 16; in lpuart_start_rx_dma()
1365 sport->last_residue = 0; in lpuart_start_rx_dma()
1366 sport->dma_rx_timeout = max(nsecs_to_jiffies( in lpuart_start_rx_dma()
1367 sport->port.frame_time * DMA_RX_IDLE_CHARS), 1UL); in lpuart_start_rx_dma()
1369 ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC); in lpuart_start_rx_dma()
1370 if (!ring->buf) in lpuart_start_rx_dma()
1371 return -ENOMEM; in lpuart_start_rx_dma()
1373 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); in lpuart_start_rx_dma()
1374 nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1, in lpuart_start_rx_dma()
1378 dev_err(sport->port.dev, "DMA Rx mapping error\n"); in lpuart_start_rx_dma()
1379 return -EINVAL; in lpuart_start_rx_dma()
1389 dev_err(sport->port.dev, in lpuart_start_rx_dma()
1394 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan, in lpuart_start_rx_dma()
1395 sg_dma_address(&sport->rx_sgl), in lpuart_start_rx_dma()
1396 sport->rx_sgl.length, in lpuart_start_rx_dma()
1397 sport->rx_sgl.length / 2, in lpuart_start_rx_dma()
1400 if (!sport->dma_rx_desc) { in lpuart_start_rx_dma()
1401 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n"); in lpuart_start_rx_dma()
1402 return -EFAULT; in lpuart_start_rx_dma()
1405 sport->dma_rx_desc->callback = lpuart_dma_rx_complete; in lpuart_start_rx_dma()
1406 sport->dma_rx_desc->callback_param = sport; in lpuart_start_rx_dma()
1407 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc); in lpuart_start_rx_dma()
1411 u32 temp = lpuart32_read(&sport->port, UARTBAUD); in lpuart_start_rx_dma()
1413 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD); in lpuart_start_rx_dma()
1415 if (sport->dma_idle_int) { in lpuart_start_rx_dma()
1416 u32 ctrl = lpuart32_read(&sport->port, UARTCTRL); in lpuart_start_rx_dma()
1418 lpuart32_write(&sport->port, ctrl | UARTCTRL_ILIE, UARTCTRL); in lpuart_start_rx_dma()
1421 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS, in lpuart_start_rx_dma()
1422 sport->port.membase + UARTCR5); in lpuart_start_rx_dma()
1432 struct dma_chan *chan = sport->dma_rx_chan; in lpuart_dma_rx_free()
1435 if (!sport->dma_idle_int) in lpuart_dma_rx_free()
1436 del_timer_sync(&sport->lpuart_timer); in lpuart_dma_rx_free()
1438 dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); in lpuart_dma_rx_free()
1439 kfree(sport->rx_ring.buf); in lpuart_dma_rx_free()
1440 sport->rx_ring.tail = 0; in lpuart_dma_rx_free()
1441 sport->rx_ring.head = 0; in lpuart_dma_rx_free()
1442 sport->dma_rx_desc = NULL; in lpuart_dma_rx_free()
1443 sport->dma_rx_cookie = -EINVAL; in lpuart_dma_rx_free()
1449 u8 modem = readb(port->membase + UARTMODEM) & in lpuart_config_rs485()
1451 writeb(modem, port->membase + UARTMODEM); in lpuart_config_rs485()
1453 if (rs485->flags & SER_RS485_ENABLED) { in lpuart_config_rs485()
1454 /* Enable auto RS-485 RTS mode */ in lpuart_config_rs485()
1463 if (rs485->flags & SER_RS485_RTS_ON_SEND) in lpuart_config_rs485()
1465 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) in lpuart_config_rs485()
1469 writeb(modem, port->membase + UARTMODEM); in lpuart_config_rs485()
1493 if (rs485->flags & SER_RS485_ENABLED) { in lpuart32_config_rs485()
1494 /* Enable auto RS-485 RTS mode */ in lpuart32_config_rs485()
1503 if (rs485->flags & SER_RS485_RTS_ON_SEND) in lpuart32_config_rs485()
1505 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) in lpuart32_config_rs485()
1522 reg = readb(port->membase + UARTCR1); in lpuart_get_mctrl()
1545 reg = readb(port->membase + UARTCR1); in lpuart_set_mctrl()
1552 writeb(reg, port->membase + UARTCR1); in lpuart_set_mctrl()
1573 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK; in lpuart_break_ctl()
1578 writeb(temp, port->membase + UARTCR2); in lpuart_break_ctl()
1607 /* Disable the TXINV to turn off break and re-enable transmitter. */ in lpuart32_break_ctl()
1619 cr2 = readb(sport->port.membase + UARTCR2); in lpuart_setup_watermark()
1623 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_setup_watermark()
1625 val = readb(sport->port.membase + UARTPFIFO); in lpuart_setup_watermark()
1627 sport->port.membase + UARTPFIFO); in lpuart_setup_watermark()
1631 sport->port.membase + UARTCFIFO); in lpuart_setup_watermark()
1634 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { in lpuart_setup_watermark()
1635 readb(sport->port.membase + UARTDR); in lpuart_setup_watermark()
1636 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); in lpuart_setup_watermark()
1639 if (uart_console(&sport->port)) in lpuart_setup_watermark()
1640 sport->rx_watermark = 1; in lpuart_setup_watermark()
1641 writeb(0, sport->port.membase + UARTTWFIFO); in lpuart_setup_watermark()
1642 writeb(sport->rx_watermark, sport->port.membase + UARTRWFIFO); in lpuart_setup_watermark()
1645 writeb(cr2_saved, sport->port.membase + UARTCR2); in lpuart_setup_watermark()
1654 cr2 = readb(sport->port.membase + UARTCR2); in lpuart_setup_watermark_enable()
1656 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_setup_watermark_enable()
1663 ctrl = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_setup_watermark()
1667 lpuart32_write(&sport->port, ctrl, UARTCTRL); in lpuart32_setup_watermark()
1670 val = lpuart32_read(&sport->port, UARTFIFO); in lpuart32_setup_watermark()
1674 lpuart32_write(&sport->port, val, UARTFIFO); in lpuart32_setup_watermark()
1677 if (uart_console(&sport->port)) in lpuart32_setup_watermark()
1678 sport->rx_watermark = 1; in lpuart32_setup_watermark()
1679 val = (sport->rx_watermark << UARTWATER_RXWATER_OFF) | in lpuart32_setup_watermark()
1681 lpuart32_write(&sport->port, val, UARTWATER); in lpuart32_setup_watermark()
1684 if (!uart_console(&sport->port)) { in lpuart32_setup_watermark()
1685 val = lpuart32_read(&sport->port, UARTMODIR); in lpuart32_setup_watermark()
1686 val |= FIELD_PREP(UARTMODIR_RTSWATER, sport->rxfifo_size >> 1); in lpuart32_setup_watermark()
1687 lpuart32_write(&sport->port, val, UARTMODIR); in lpuart32_setup_watermark()
1691 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL); in lpuart32_setup_watermark()
1700 temp = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_setup_watermark_enable()
1703 lpuart32_write(&sport->port, temp, UARTCTRL); in lpuart32_setup_watermark_enable()
1708 if (sport->dma_idle_int) in rx_dma_timer_init()
1711 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0); in rx_dma_timer_init()
1712 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout; in rx_dma_timer_init()
1713 add_timer(&sport->lpuart_timer); in rx_dma_timer_init()
1718 sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx"); in lpuart_request_dma()
1719 if (IS_ERR(sport->dma_tx_chan)) { in lpuart_request_dma()
1720 dev_dbg_once(sport->port.dev, in lpuart_request_dma()
1722 PTR_ERR(sport->dma_tx_chan)); in lpuart_request_dma()
1723 sport->dma_tx_chan = NULL; in lpuart_request_dma()
1726 sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx"); in lpuart_request_dma()
1727 if (IS_ERR(sport->dma_rx_chan)) { in lpuart_request_dma()
1728 dev_dbg_once(sport->port.dev, in lpuart_request_dma()
1730 PTR_ERR(sport->dma_rx_chan)); in lpuart_request_dma()
1731 sport->dma_rx_chan = NULL; in lpuart_request_dma()
1740 if (uart_console(&sport->port)) in lpuart_tx_dma_startup()
1743 if (!sport->dma_tx_chan) in lpuart_tx_dma_startup()
1746 ret = lpuart_dma_tx_request(&sport->port); in lpuart_tx_dma_startup()
1750 init_waitqueue_head(&sport->dma_wait); in lpuart_tx_dma_startup()
1751 sport->lpuart_dma_tx_use = true; in lpuart_tx_dma_startup()
1753 uartbaud = lpuart32_read(&sport->port, UARTBAUD); in lpuart_tx_dma_startup()
1754 lpuart32_write(&sport->port, in lpuart_tx_dma_startup()
1757 writeb(readb(sport->port.membase + UARTCR5) | in lpuart_tx_dma_startup()
1758 UARTCR5_TDMAS, sport->port.membase + UARTCR5); in lpuart_tx_dma_startup()
1764 sport->lpuart_dma_tx_use = false; in lpuart_tx_dma_startup()
1772 if (uart_console(&sport->port)) in lpuart_rx_dma_startup()
1775 if (!sport->dma_rx_chan) in lpuart_rx_dma_startup()
1779 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT); in lpuart_rx_dma_startup()
1785 if (!sport->dma_rx_timeout) in lpuart_rx_dma_startup()
1786 sport->dma_rx_timeout = 1; in lpuart_rx_dma_startup()
1788 sport->lpuart_dma_rx_use = true; in lpuart_rx_dma_startup()
1791 if (sport->port.has_sysrq && !lpuart_is_32(sport)) { in lpuart_rx_dma_startup()
1792 cr3 = readb(sport->port.membase + UARTCR3); in lpuart_rx_dma_startup()
1794 writeb(cr3, sport->port.membase + UARTCR3); in lpuart_rx_dma_startup()
1800 sport->lpuart_dma_rx_use = false; in lpuart_rx_dma_startup()
1807 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_hw_setup()
1814 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_hw_setup()
1823 temp = readb(port->membase + UARTPFIFO); in lpuart_startup()
1825 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) & in lpuart_startup()
1827 port->fifosize = sport->txfifo_size; in lpuart_startup()
1829 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) & in lpuart_startup()
1842 temp = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_hw_disable()
1845 lpuart32_write(&sport->port, temp, UARTCTRL); in lpuart32_hw_disable()
1852 temp = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_configure()
1853 if (!sport->lpuart_dma_rx_use) in lpuart32_configure()
1855 if (!sport->lpuart_dma_tx_use) in lpuart32_configure()
1857 lpuart32_write(&sport->port, temp, UARTCTRL); in lpuart32_configure()
1864 uart_port_lock_irqsave(&sport->port, &flags); in lpuart32_hw_setup()
1874 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart32_hw_setup()
1885 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) & in lpuart32_startup()
1887 port->fifosize = sport->txfifo_size; in lpuart32_startup()
1889 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) & in lpuart32_startup()
1898 sport->rxfifo_size = 16; in lpuart32_startup()
1899 sport->txfifo_size = 16; in lpuart32_startup()
1900 port->fifosize = sport->txfifo_size; in lpuart32_startup()
1911 if (sport->lpuart_dma_rx_use) { in lpuart_dma_shutdown()
1912 lpuart_dma_rx_free(&sport->port); in lpuart_dma_shutdown()
1913 sport->lpuart_dma_rx_use = false; in lpuart_dma_shutdown()
1916 if (sport->lpuart_dma_tx_use) { in lpuart_dma_shutdown()
1917 if (wait_event_interruptible_timeout(sport->dma_wait, in lpuart_dma_shutdown()
1918 !sport->dma_tx_in_progress, msecs_to_jiffies(300)) <= 0) { in lpuart_dma_shutdown()
1919 sport->dma_tx_in_progress = false; in lpuart_dma_shutdown()
1920 dmaengine_terminate_sync(sport->dma_tx_chan); in lpuart_dma_shutdown()
1922 sport->lpuart_dma_tx_use = false; in lpuart_dma_shutdown()
1925 if (sport->dma_tx_chan) in lpuart_dma_shutdown()
1926 dma_release_channel(sport->dma_tx_chan); in lpuart_dma_shutdown()
1927 if (sport->dma_rx_chan) in lpuart_dma_shutdown()
1928 dma_release_channel(sport->dma_rx_chan); in lpuart_dma_shutdown()
1940 temp = readb(port->membase + UARTCR2); in lpuart_shutdown()
1943 writeb(temp, port->membase + UARTCR2); in lpuart_shutdown()
1991 unsigned int baud; in lpuart_set_termios() local
1992 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; in lpuart_set_termios()
1995 cr1 = old_cr1 = readb(port->membase + UARTCR1); in lpuart_set_termios()
1996 old_cr2 = readb(port->membase + UARTCR2); in lpuart_set_termios()
1997 cr3 = readb(port->membase + UARTCR3); in lpuart_set_termios()
1998 cr4 = readb(port->membase + UARTCR4); in lpuart_set_termios()
1999 bdh = readb(port->membase + UARTBDH); in lpuart_set_termios()
2000 modem = readb(port->membase + UARTMODEM); in lpuart_set_termios()
2004 * - (7,e/o,1) in lpuart_set_termios()
2005 * - (8,n,1) in lpuart_set_termios()
2006 * - (8,m/s,1) in lpuart_set_termios()
2007 * - (8,e/o,1) in lpuart_set_termios()
2009 while ((termios->c_cflag & CSIZE) != CS8 && in lpuart_set_termios()
2010 (termios->c_cflag & CSIZE) != CS7) { in lpuart_set_termios()
2011 termios->c_cflag &= ~CSIZE; in lpuart_set_termios()
2012 termios->c_cflag |= old_csize; in lpuart_set_termios()
2016 if ((termios->c_cflag & CSIZE) == CS8 || in lpuart_set_termios()
2017 (termios->c_cflag & CSIZE) == CS7) in lpuart_set_termios()
2020 if (termios->c_cflag & CMSPAR) { in lpuart_set_termios()
2021 if ((termios->c_cflag & CSIZE) != CS8) { in lpuart_set_termios()
2022 termios->c_cflag &= ~CSIZE; in lpuart_set_termios()
2023 termios->c_cflag |= CS8; in lpuart_set_termios()
2029 * When auto RS-485 RTS mode is enabled, in lpuart_set_termios()
2032 if (port->rs485.flags & SER_RS485_ENABLED) in lpuart_set_termios()
2033 termios->c_cflag &= ~CRTSCTS; in lpuart_set_termios()
2035 if (termios->c_cflag & CRTSCTS) in lpuart_set_termios()
2040 termios->c_cflag &= ~CSTOPB; in lpuart_set_termios()
2042 /* parity must be enabled when CS7 to match 8-bits format */ in lpuart_set_termios()
2043 if ((termios->c_cflag & CSIZE) == CS7) in lpuart_set_termios()
2044 termios->c_cflag |= PARENB; in lpuart_set_termios()
2046 if (termios->c_cflag & PARENB) { in lpuart_set_termios()
2047 if (termios->c_cflag & CMSPAR) { in lpuart_set_termios()
2049 if (termios->c_cflag & PARODD) in lpuart_set_termios()
2055 if ((termios->c_cflag & CSIZE) == CS8) in lpuart_set_termios()
2057 if (termios->c_cflag & PARODD) in lpuart_set_termios()
2067 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); in lpuart_set_termios()
2071 * baud rate and restart Rx DMA path. in lpuart_set_termios()
2073 * Since timer function acqures port->lock, need to stop before in lpuart_set_termios()
2076 if (old && sport->lpuart_dma_rx_use) in lpuart_set_termios()
2081 port->read_status_mask = 0; in lpuart_set_termios()
2082 if (termios->c_iflag & INPCK) in lpuart_set_termios()
2083 port->read_status_mask |= UARTSR1_FE | UARTSR1_PE; in lpuart_set_termios()
2084 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in lpuart_set_termios()
2085 port->read_status_mask |= UARTSR1_FE; in lpuart_set_termios()
2088 port->ignore_status_mask = 0; in lpuart_set_termios()
2089 if (termios->c_iflag & IGNPAR) in lpuart_set_termios()
2090 port->ignore_status_mask |= UARTSR1_PE; in lpuart_set_termios()
2091 if (termios->c_iflag & IGNBRK) { in lpuart_set_termios()
2092 port->ignore_status_mask |= UARTSR1_FE; in lpuart_set_termios()
2097 if (termios->c_iflag & IGNPAR) in lpuart_set_termios()
2098 port->ignore_status_mask |= UARTSR1_OR; in lpuart_set_termios()
2101 /* update the per-port timeout */ in lpuart_set_termios()
2102 uart_update_timeout(port, termios->c_cflag, baud); in lpuart_set_termios()
2109 port->membase + UARTCR2); in lpuart_set_termios()
2111 sbr = port->uartclk / (16 * baud); in lpuart_set_termios()
2112 brfa = ((port->uartclk - (16 * sbr * baud)) * 2) / baud; in lpuart_set_termios()
2117 writeb(cr4 | brfa, port->membase + UARTCR4); in lpuart_set_termios()
2118 writeb(bdh, port->membase + UARTBDH); in lpuart_set_termios()
2119 writeb(sbr & 0xFF, port->membase + UARTBDL); in lpuart_set_termios()
2120 writeb(cr3, port->membase + UARTCR3); in lpuart_set_termios()
2121 writeb(cr1, port->membase + UARTCR1); in lpuart_set_termios()
2122 writeb(modem, port->membase + UARTMODEM); in lpuart_set_termios()
2125 writeb(old_cr2, port->membase + UARTCR2); in lpuart_set_termios()
2127 if (old && sport->lpuart_dma_rx_use) { in lpuart_set_termios()
2131 sport->lpuart_dma_rx_use = false; in lpuart_set_termios()
2142 u32 clk = port->uartclk; in __lpuart32_serial_setbrg()
2145 * The idea is to use the best OSR (over-sampling rate) possible. in __lpuart32_serial_setbrg()
2146 * Note, OSR is typically hard-set to 16 in other LPUART instantiations. in __lpuart32_serial_setbrg()
2151 * Baud Rate = baud clock / ((OSR+1) × SBR) in __lpuart32_serial_setbrg()
2164 * calculate the baud rate difference based on the temporary in __lpuart32_serial_setbrg()
2167 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate; in __lpuart32_serial_setbrg()
2171 if (tmp_diff > (baudrate - tmp)) { in __lpuart32_serial_setbrg()
2172 tmp_diff = baudrate - tmp; in __lpuart32_serial_setbrg()
2191 dev_warn(port->dev, in __lpuart32_serial_setbrg()
2192 "unacceptable baud rate difference of more than 3%%\n"); in __lpuart32_serial_setbrg()
2200 tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT; in __lpuart32_serial_setbrg()
2216 __lpuart32_serial_setbrg(&sport->port, baudrate, in lpuart32_serial_setbrg()
2217 sport->lpuart_dma_rx_use, in lpuart32_serial_setbrg()
2218 sport->lpuart_dma_tx_use); in lpuart32_serial_setbrg()
2229 unsigned int baud; in lpuart32_set_termios() local
2230 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; in lpuart32_set_termios()
2235 sport->is_cs7 = false; in lpuart32_set_termios()
2239 * - (7,n,1) (imx only) in lpuart32_set_termios()
2240 * - (7,e/o,1) in lpuart32_set_termios()
2241 * - (8,n,1) in lpuart32_set_termios()
2242 * - (8,m/s,1) in lpuart32_set_termios()
2243 * - (8,e/o,1) in lpuart32_set_termios()
2245 while ((termios->c_cflag & CSIZE) != CS8 && in lpuart32_set_termios()
2246 (termios->c_cflag & CSIZE) != CS7) { in lpuart32_set_termios()
2247 termios->c_cflag &= ~CSIZE; in lpuart32_set_termios()
2248 termios->c_cflag |= old_csize; in lpuart32_set_termios()
2252 if ((termios->c_cflag & CSIZE) == CS8 || in lpuart32_set_termios()
2253 (termios->c_cflag & CSIZE) == CS7) in lpuart32_set_termios()
2256 if (termios->c_cflag & CMSPAR) { in lpuart32_set_termios()
2257 if ((termios->c_cflag & CSIZE) != CS8) { in lpuart32_set_termios()
2258 termios->c_cflag &= ~CSIZE; in lpuart32_set_termios()
2259 termios->c_cflag |= CS8; in lpuart32_set_termios()
2265 * When auto RS-485 RTS mode is enabled, in lpuart32_set_termios()
2268 if (port->rs485.flags & SER_RS485_ENABLED) in lpuart32_set_termios()
2269 termios->c_cflag &= ~CRTSCTS; in lpuart32_set_termios()
2271 if (termios->c_cflag & CRTSCTS) in lpuart32_set_termios()
2276 if (termios->c_cflag & CSTOPB) in lpuart32_set_termios()
2282 * imx support 7-bits format, no limitation on parity when CS7 in lpuart32_set_termios()
2283 * for layerscape, parity must be enabled when CS7 to match 8-bits format in lpuart32_set_termios()
2285 if ((termios->c_cflag & CSIZE) == CS7 && !(termios->c_cflag & PARENB)) { in lpuart32_set_termios()
2291 termios->c_cflag |= PARENB; in lpuart32_set_termios()
2294 if ((termios->c_cflag & PARENB)) { in lpuart32_set_termios()
2295 if (termios->c_cflag & CMSPAR) { in lpuart32_set_termios()
2300 if ((termios->c_cflag & CSIZE) == CS8) in lpuart32_set_termios()
2302 if (termios->c_cflag & PARODD) in lpuart32_set_termios()
2312 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4); in lpuart32_set_termios()
2316 * baud rate and restart Rx DMA path. in lpuart32_set_termios()
2318 * Since timer function acqures port->lock, need to stop before in lpuart32_set_termios()
2321 if (old && sport->lpuart_dma_rx_use) in lpuart32_set_termios()
2326 port->read_status_mask = 0; in lpuart32_set_termios()
2327 if (termios->c_iflag & INPCK) in lpuart32_set_termios()
2328 port->read_status_mask |= UARTSTAT_FE | UARTSTAT_PE; in lpuart32_set_termios()
2329 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in lpuart32_set_termios()
2330 port->read_status_mask |= UARTSTAT_FE; in lpuart32_set_termios()
2333 port->ignore_status_mask = 0; in lpuart32_set_termios()
2334 if (termios->c_iflag & IGNPAR) in lpuart32_set_termios()
2335 port->ignore_status_mask |= UARTSTAT_PE; in lpuart32_set_termios()
2336 if (termios->c_iflag & IGNBRK) { in lpuart32_set_termios()
2337 port->ignore_status_mask |= UARTSTAT_FE; in lpuart32_set_termios()
2342 if (termios->c_iflag & IGNPAR) in lpuart32_set_termios()
2343 port->ignore_status_mask |= UARTSTAT_OR; in lpuart32_set_termios()
2346 /* update the per-port timeout */ in lpuart32_set_termios()
2347 uart_update_timeout(port, termios->c_cflag, baud); in lpuart32_set_termios()
2368 lpuart32_serial_setbrg(sport, baud); in lpuart32_set_termios()
2371 /* re-enable the CTS if needed */ in lpuart32_set_termios()
2375 sport->is_cs7 = true; in lpuart32_set_termios()
2377 if (old && sport->lpuart_dma_rx_use) { in lpuart32_set_termios()
2381 sport->lpuart_dma_rx_use = false; in lpuart32_set_termios()
2406 port->type = PORT_LPUART; in lpuart_config_port()
2413 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART) in lpuart_verify_port()
2414 ret = -EINVAL; in lpuart_verify_port()
2415 if (port->irq != ser->irq) in lpuart_verify_port()
2416 ret = -EINVAL; in lpuart_verify_port()
2417 if (ser->io_type != UPIO_MEM) in lpuart_verify_port()
2418 ret = -EINVAL; in lpuart_verify_port()
2419 if (port->uartclk / 16 != ser->baud_base) in lpuart_verify_port()
2420 ret = -EINVAL; in lpuart_verify_port()
2421 if (port->iobase != ser->port) in lpuart_verify_port()
2422 ret = -EINVAL; in lpuart_verify_port()
2423 if (ser->hub6 != 0) in lpuart_verify_port()
2424 ret = -EINVAL; in lpuart_verify_port()
2484 writeb(ch, port->membase + UARTDR); in lpuart_console_putchar()
2496 struct lpuart_port *sport = lpuart_ports[co->index]; in lpuart_console_write()
2502 locked = uart_port_trylock_irqsave(&sport->port, &flags); in lpuart_console_write()
2504 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_console_write()
2507 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); in lpuart_console_write()
2510 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_console_write()
2512 uart_console_write(&sport->port, s, count, lpuart_console_putchar); in lpuart_console_write()
2515 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); in lpuart_console_write()
2517 writeb(old_cr2, sport->port.membase + UARTCR2); in lpuart_console_write()
2520 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_console_write()
2526 struct lpuart_port *sport = lpuart_ports[co->index]; in lpuart32_console_write()
2532 locked = uart_port_trylock_irqsave(&sport->port, &flags); in lpuart32_console_write()
2534 uart_port_lock_irqsave(&sport->port, &flags); in lpuart32_console_write()
2537 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_console_write()
2540 lpuart32_write(&sport->port, cr, UARTCTRL); in lpuart32_console_write()
2542 uart_console_write(&sport->port, s, count, lpuart32_console_putchar); in lpuart32_console_write()
2545 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); in lpuart32_console_write()
2547 lpuart32_write(&sport->port, old_cr, UARTCTRL); in lpuart32_console_write()
2550 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart32_console_write()
2558 lpuart_console_get_options(struct lpuart_port *sport, int *baud, in lpuart_console_get_options() argument
2564 cr = readb(sport->port.membase + UARTCR2); in lpuart_console_get_options()
2571 cr = readb(sport->port.membase + UARTCR1); in lpuart_console_get_options()
2586 bdh = readb(sport->port.membase + UARTBDH); in lpuart_console_get_options()
2588 bdl = readb(sport->port.membase + UARTBDL); in lpuart_console_get_options()
2592 brfa = readb(sport->port.membase + UARTCR4); in lpuart_console_get_options()
2597 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) in lpuart_console_get_options()
2601 if (*baud != baud_raw) in lpuart_console_get_options()
2602 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" in lpuart_console_get_options()
2603 "from %d to %d\n", baud_raw, *baud); in lpuart_console_get_options()
2607 lpuart32_console_get_options(struct lpuart_port *sport, int *baud, in lpuart32_console_get_options() argument
2613 cr = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_console_get_options()
2620 cr = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_console_get_options()
2635 bd = lpuart32_read(&sport->port, UARTBAUD); in lpuart32_console_get_options()
2643 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) in lpuart32_console_get_options()
2647 if (*baud != baud_raw) in lpuart32_console_get_options()
2648 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" in lpuart32_console_get_options()
2649 "from %d to %d\n", baud_raw, *baud); in lpuart32_console_get_options()
2655 int baud = 115200; in lpuart_console_setup() local
2665 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports)) in lpuart_console_setup()
2666 co->index = 0; in lpuart_console_setup()
2668 sport = lpuart_ports[co->index]; in lpuart_console_setup()
2670 return -ENODEV; in lpuart_console_setup()
2673 uart_parse_options(options, &baud, &parity, &bits, &flow); in lpuart_console_setup()
2676 lpuart32_console_get_options(sport, &baud, &parity, &bits); in lpuart_console_setup()
2678 lpuart_console_get_options(sport, &baud, &parity, &bits); in lpuart_console_setup()
2685 return uart_set_options(&sport->port, co, baud, parity, bits, flow); in lpuart_console_setup()
2695 .index = -1,
2705 .index = -1,
2711 struct earlycon_device *dev = con->data; in lpuart_early_write()
2713 uart_console_write(&dev->port, s, n, lpuart_console_putchar); in lpuart_early_write()
2718 struct earlycon_device *dev = con->data; in lpuart32_early_write()
2720 uart_console_write(&dev->port, s, n, lpuart32_console_putchar); in lpuart32_early_write()
2726 if (!device->port.membase) in lpuart_early_console_setup()
2727 return -ENODEV; in lpuart_early_console_setup()
2729 device->con->write = lpuart_early_write; in lpuart_early_console_setup()
2736 if (!device->port.membase) in lpuart32_early_console_setup()
2737 return -ENODEV; in lpuart32_early_console_setup()
2739 if (device->port.iotype != UPIO_MEM32) in lpuart32_early_console_setup()
2740 device->port.iotype = UPIO_MEM32BE; in lpuart32_early_console_setup()
2742 device->con->write = lpuart32_early_write; in lpuart32_early_console_setup()
2751 if (!device->port.membase) in ls1028a_early_console_setup()
2752 return -ENODEV; in ls1028a_early_console_setup()
2754 device->port.iotype = UPIO_MEM32; in ls1028a_early_console_setup()
2755 device->con->write = lpuart32_early_write; in ls1028a_early_console_setup()
2758 if (device->port.uartclk && device->baud) in ls1028a_early_console_setup()
2759 __lpuart32_serial_setbrg(&device->port, device->baud, in ls1028a_early_console_setup()
2763 cr = lpuart32_read(&device->port, UARTCTRL); in ls1028a_early_console_setup()
2765 lpuart32_write(&device->port, cr, UARTCTRL); in ls1028a_early_console_setup()
2773 if (!device->port.membase) in lpuart32_imx_early_console_setup()
2774 return -ENODEV; in lpuart32_imx_early_console_setup()
2776 device->port.iotype = UPIO_MEM32; in lpuart32_imx_early_console_setup()
2777 device->port.membase += IMX_REG_OFF; in lpuart32_imx_early_console_setup()
2778 device->con->write = lpuart32_early_write; in lpuart32_imx_early_console_setup()
2782 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
2783 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
2784 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup);
2785 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
2786 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8ulp-lpuart", lpuart32_imx_early_console_setup);
2787 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup);
2788 OF_EARLYCON_DECLARE(lpuart32, "fsl,imxrt1050-lpuart", lpuart32_imx_early_console_setup);
2814 struct uart_port *port = &sport->port; in lpuart_global_reset()
2820 ret = clk_prepare_enable(sport->ipg_clk); in lpuart_global_reset()
2822 dev_err(port->dev, "failed to enable uart ipg clk: %d\n", ret); in lpuart_global_reset()
2836 dev_warn(port->dev, in lpuart_global_reset()
2838 clk_disable_unprepare(sport->ipg_clk); in lpuart_global_reset()
2843 global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF; in lpuart_global_reset()
2856 clk_disable_unprepare(sport->ipg_clk); in lpuart_global_reset()
2862 const struct lpuart_soc_data *sdata = of_device_get_match_data(&pdev->dev); in lpuart_probe()
2863 struct device_node *np = pdev->dev.of_node; in lpuart_probe()
2869 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); in lpuart_probe()
2871 return -ENOMEM; in lpuart_probe()
2873 sport->port.membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in lpuart_probe()
2874 if (IS_ERR(sport->port.membase)) in lpuart_probe()
2875 return PTR_ERR(sport->port.membase); in lpuart_probe()
2877 sport->port.membase += sdata->reg_off; in lpuart_probe()
2878 sport->port.mapbase = res->start + sdata->reg_off; in lpuart_probe()
2879 sport->port.dev = &pdev->dev; in lpuart_probe()
2880 sport->port.type = PORT_LPUART; in lpuart_probe()
2881 sport->devtype = sdata->devtype; in lpuart_probe()
2882 sport->rx_watermark = sdata->rx_watermark; in lpuart_probe()
2883 sport->dma_idle_int = is_imx7ulp_lpuart(sport) || is_imx8ulp_lpuart(sport) || in lpuart_probe()
2888 sport->port.irq = ret; in lpuart_probe()
2889 sport->port.iotype = sdata->iotype; in lpuart_probe()
2891 sport->port.ops = &lpuart32_pops; in lpuart_probe()
2893 sport->port.ops = &lpuart_pops; in lpuart_probe()
2894 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE); in lpuart_probe()
2895 sport->port.flags = UPF_BOOT_AUTOCONF; in lpuart_probe()
2898 sport->port.rs485_config = lpuart32_config_rs485; in lpuart_probe()
2900 sport->port.rs485_config = lpuart_config_rs485; in lpuart_probe()
2901 sport->port.rs485_supported = lpuart_rs485_supported; in lpuart_probe()
2903 sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); in lpuart_probe()
2904 if (IS_ERR(sport->ipg_clk)) { in lpuart_probe()
2905 ret = PTR_ERR(sport->ipg_clk); in lpuart_probe()
2906 return dev_err_probe(&pdev->dev, ret, "failed to get uart ipg clk\n"); in lpuart_probe()
2909 sport->baud_clk = NULL; in lpuart_probe()
2911 sport->baud_clk = devm_clk_get(&pdev->dev, "baud"); in lpuart_probe()
2912 if (IS_ERR(sport->baud_clk)) { in lpuart_probe()
2913 ret = PTR_ERR(sport->baud_clk); in lpuart_probe()
2914 return dev_err_probe(&pdev->dev, ret, "failed to get uart baud clk\n"); in lpuart_probe()
2920 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); in lpuart_probe()
2924 dev_err(&pdev->dev, "serial%d out of range\n", ret); in lpuart_probe()
2925 return -EINVAL; in lpuart_probe()
2927 sport->port.line = ret; in lpuart_probe()
2932 sport->port.uartclk = lpuart_get_baud_clk_rate(sport); in lpuart_probe()
2934 lpuart_ports[sport->port.line] = sport; in lpuart_probe()
2936 platform_set_drvdata(pdev, &sport->port); in lpuart_probe()
2946 pm_runtime_use_autosuspend(&pdev->dev); in lpuart_probe()
2947 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT); in lpuart_probe()
2948 pm_runtime_set_active(&pdev->dev); in lpuart_probe()
2949 pm_runtime_enable(&pdev->dev); in lpuart_probe()
2950 pm_runtime_mark_last_busy(&pdev->dev); in lpuart_probe()
2956 ret = uart_get_rs485_mode(&sport->port); in lpuart_probe()
2960 ret = uart_add_one_port(&lpuart_reg, &sport->port); in lpuart_probe()
2964 ret = devm_request_irq(&pdev->dev, sport->port.irq, handler, 0, in lpuart_probe()
2972 uart_remove_one_port(&lpuart_reg, &sport->port); in lpuart_probe()
2976 pm_runtime_disable(&pdev->dev); in lpuart_probe()
2977 pm_runtime_set_suspended(&pdev->dev); in lpuart_probe()
2978 pm_runtime_dont_use_autosuspend(&pdev->dev); in lpuart_probe()
2987 uart_remove_one_port(&lpuart_reg, &sport->port); in lpuart_remove()
2991 if (sport->dma_tx_chan) in lpuart_remove()
2992 dma_release_channel(sport->dma_tx_chan); in lpuart_remove()
2994 if (sport->dma_rx_chan) in lpuart_remove()
2995 dma_release_channel(sport->dma_rx_chan); in lpuart_remove()
2997 pm_runtime_disable(&pdev->dev); in lpuart_remove()
2998 pm_runtime_set_suspended(&pdev->dev); in lpuart_remove()
2999 pm_runtime_dont_use_autosuspend(&pdev->dev); in lpuart_remove()
3022 u32 val, baud; in serial_lpuart_enable_wakeup() local
3025 val = lpuart32_read(&sport->port, UARTCTRL); in serial_lpuart_enable_wakeup()
3026 baud = lpuart32_read(&sport->port, UARTBAUD); in serial_lpuart_enable_wakeup()
3029 lpuart32_write(&sport->port, 0, UARTWATER); in serial_lpuart_enable_wakeup()
3032 lpuart32_write(&sport->port, UARTSTAT_RXEDGIF, UARTSTAT); in serial_lpuart_enable_wakeup()
3033 baud |= UARTBAUD_RXEDGIE; in serial_lpuart_enable_wakeup()
3036 baud &= ~UARTBAUD_RXEDGIE; in serial_lpuart_enable_wakeup()
3038 lpuart32_write(&sport->port, val, UARTCTRL); in serial_lpuart_enable_wakeup()
3039 lpuart32_write(&sport->port, baud, UARTBAUD); in serial_lpuart_enable_wakeup()
3041 val = readb(sport->port.membase + UARTCR2); in serial_lpuart_enable_wakeup()
3046 writeb(val, sport->port.membase + UARTCR2); in serial_lpuart_enable_wakeup()
3052 struct tty_port *port = &sport->port.state->port; in lpuart_uport_is_active()
3059 tty_dev = tty->dev; in lpuart_uport_is_active()
3065 (!console_suspend_enabled && uart_console(&sport->port))) in lpuart_uport_is_active()
3074 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); in lpuart_suspend_noirq()
3096 val = lpuart32_read(&sport->port, UARTSTAT); in lpuart_resume_noirq()
3097 lpuart32_write(&sport->port, val, UARTSTAT); in lpuart_resume_noirq()
3110 uart_suspend_port(&lpuart_reg, &sport->port); in lpuart_suspend()
3113 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_suspend()
3116 temp = lpuart32_read(&sport->port, UARTCTRL); in lpuart_suspend()
3118 lpuart32_write(&sport->port, temp, UARTCTRL); in lpuart_suspend()
3121 temp = readb(sport->port.membase + UARTCR2); in lpuart_suspend()
3123 writeb(temp, sport->port.membase + UARTCR2); in lpuart_suspend()
3125 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_suspend()
3127 if (sport->lpuart_dma_rx_use) { in lpuart_suspend()
3130 * non-idle DMA channels. If port wakeup is enabled or if port in lpuart_suspend()
3135 lpuart_dma_rx_free(&sport->port); in lpuart_suspend()
3138 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_suspend()
3140 temp = lpuart32_read(&sport->port, UARTBAUD); in lpuart_suspend()
3141 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE, in lpuart_suspend()
3144 writeb(readb(sport->port.membase + UARTCR5) & in lpuart_suspend()
3145 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5); in lpuart_suspend()
3147 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_suspend()
3150 if (sport->lpuart_dma_tx_use) { in lpuart_suspend()
3151 uart_port_lock_irqsave(&sport->port, &flags); in lpuart_suspend()
3153 temp = lpuart32_read(&sport->port, UARTBAUD); in lpuart_suspend()
3155 lpuart32_write(&sport->port, temp, UARTBAUD); in lpuart_suspend()
3157 temp = readb(sport->port.membase + UARTCR5); in lpuart_suspend()
3159 writeb(temp, sport->port.membase + UARTCR5); in lpuart_suspend()
3161 uart_port_unlock_irqrestore(&sport->port, flags); in lpuart_suspend()
3162 sport->dma_tx_in_progress = false; in lpuart_suspend()
3163 dmaengine_terminate_sync(sport->dma_tx_chan); in lpuart_suspend()
3165 } else if (pm_runtime_active(sport->port.dev)) { in lpuart_suspend()
3167 pm_runtime_disable(sport->port.dev); in lpuart_suspend()
3168 pm_runtime_set_suspended(sport->port.dev); in lpuart_suspend()
3176 struct tty_port *port = &sport->port.state->port; in lpuart_console_fixup()
3177 struct uart_port *uport = &sport->port; in lpuart_console_fixup()
3182 * For console port, console baud rate setting lost and print messy in lpuart_console_fixup()
3190 mutex_lock(&port->mutex); in lpuart_console_fixup()
3192 termios.c_cflag = uport->cons->cflag; in lpuart_console_fixup()
3193 if (port->tty && termios.c_cflag == 0) in lpuart_console_fixup()
3194 termios = port->tty->termios; in lpuart_console_fixup()
3195 uport->ops->set_termios(uport, &termios, NULL); in lpuart_console_fixup()
3196 mutex_unlock(&port->mutex); in lpuart_console_fixup()
3210 } else if (pm_runtime_active(sport->port.dev)) { in lpuart_resume()
3214 pm_runtime_set_active(sport->port.dev); in lpuart_resume()
3215 pm_runtime_enable(sport->port.dev); in lpuart_resume()
3219 uart_resume_port(&lpuart_reg, &sport->port); in lpuart_resume()
3236 .name = "fsl-lpuart",