Lines Matching +full:rs485 +full:- +full:rts +full:- +full:delay
1 // SPDX-License-Identifier: GPL-2.0
3 * Probe module for 8250/16550-type MCHP PCI serial ports.
161 /* Delay RTS before send is not supported */
166 writel(UART_SYSLOCK, port->membase + UART_SYSLOCK_REG); in pci1xxxx_set_sys_lock()
167 return readl(port->membase + UART_SYSLOCK_REG); in pci1xxxx_set_sys_lock()
182 writel(0x0, port->membase + UART_SYSLOCK_REG); in pci1xxxx_release_sys_lock()
188 {0, 1, 2, -1}, /* PCI3p012 */
189 {0, 1, 3, -1}, /* PCI3p013 */
190 {0, 2, 3, -1}, /* PCI3p023 */
191 {1, 2, 3, -1}, /* PCI3p123 */
192 {0, 1, -1, -1}, /* PCI2p01 */
193 {0, 2, -1, -1}, /* PCI2p02 */
194 {0, 3, -1, -1}, /* PCI2p03 */
195 {1, 2, -1, -1}, /* PCI2p12 */
196 {1, 3, -1, -1}, /* PCI2p13 */
197 {2, 3, -1, -1}, /* PCI2p23 */
198 {0, -1, -1, -1}, /* PCI1p0 */
199 {1, -1, -1, -1}, /* PCI1p1 */
200 {2, -1, -1, -1}, /* PCI1p2 */
201 {3, -1, -1, -1}, /* PCI1p3 */
206 switch (dev->subsystem_device) { in pci1xxxx_get_num_ports()
251 *frac = (NSEC_PER_SEC - quot * baud * uart_sample_cnt) * in pci1xxxx_get_divisor()
261 writel(UART_BIT_DIVISOR_8, port->membase + FRAC_DIV_CFG_REG); in pci1xxxx_set_divisor()
263 writel(UART_BIT_DIVISOR_16, port->membase + FRAC_DIV_CFG_REG); in pci1xxxx_set_divisor()
266 port->membase + UART_BAUD_CLK_DIVISOR_REG); in pci1xxxx_set_divisor()
276 adcl_cfg_reg = readl(port->membase + ADCL_CFG_REG); in pci1xxxx_set_mctrl()
282 modem_ctl_reg = readl(port->membase + UART_MODEM_CTL_REG); in pci1xxxx_set_mctrl()
287 line_stat_reg = readl(port->membase + UART_LINE_STAT_REG); in pci1xxxx_set_mctrl()
289 fract_div_cfg_reg = readl(port->membase + in pci1xxxx_set_mctrl()
294 port->membase + FRAC_DIV_CFG_REG); in pci1xxxx_set_mctrl()
299 port->membase + ADCL_CFG_REG); in pci1xxxx_set_mctrl()
302 writel(adcl_cfg_reg, port->membase + ADCL_CFG_REG); in pci1xxxx_set_mctrl()
304 writel(fract_div_cfg_reg, port->membase + in pci1xxxx_set_mctrl()
312 struct serial_rs485 *rs485) in pci1xxxx_rs485_config() argument
321 frac_div = readl(port->membase + FRAC_DIV_CFG_REG); in pci1xxxx_rs485_config()
329 * pci1xxxx's uart hardware supports only RTS delay after in pci1xxxx_rs485_config()
332 if (rs485->flags & SER_RS485_ENABLED) { in pci1xxxx_rs485_config()
335 if (!(rs485->flags & SER_RS485_RTS_ON_SEND)) in pci1xxxx_rs485_config()
338 if (rs485->delay_rts_after_send) { in pci1xxxx_rs485_config()
339 clock_div = readl(port->membase + UART_BAUD_CLK_DIVISOR_REG); in pci1xxxx_rs485_config()
344 rs485->delay_rts_after_send * NSEC_PER_MSEC / in pci1xxxx_rs485_config()
351 rs485->delay_rts_after_send = in pci1xxxx_rs485_config()
356 writel(mode_cfg, port->membase + ADCL_CFG_REG); in pci1xxxx_rs485_config()
364 status = readl(port->membase + UART_BURST_STATUS_REG); in pci1xxxx_read_burst_status()
368 port->membase + UART_FIFO_CTL); in pci1xxxx_read_burst_status()
369 port->icount.overrun++; in pci1xxxx_read_burst_status()
373 port->icount.frame++; in pci1xxxx_read_burst_status()
376 port->icount.parity++; in pci1xxxx_read_burst_status()
394 while (valid_burst_count--) { in pci1xxxx_process_read_data()
395 if (*buff_index > (RX_BUF_SIZE - UART_BURST_SIZE)) in pci1xxxx_process_read_data()
398 *burst_buf = readl(port->membase + UART_RX_BURST_FIFO); in pci1xxxx_process_read_data()
400 *valid_byte_count -= UART_BURST_SIZE; in pci1xxxx_process_read_data()
406 rx_buff[*buff_index] = readb(port->membase + in pci1xxxx_process_read_data()
409 *valid_byte_count -= UART_BYTE_SIZE; in pci1xxxx_process_read_data()
416 struct tty_port *tty_port = &port->state->port; in pci1xxxx_rx_burst()
430 port->icount.overrun += buff_index - copied_len; in pci1xxxx_rx_burst()
432 port->icount.rx += buff_index; in pci1xxxx_rx_burst()
441 struct tty_port *tport = &port->state->port; in pci1xxxx_process_write_data()
453 if (*data_empty_count - UART_BURST_SIZE < 0) in pci1xxxx_process_write_data()
455 if (kfifo_len(&tport->xmit_fifo) < UART_BURST_SIZE) in pci1xxxx_process_write_data()
457 if (WARN_ON(kfifo_out(&tport->xmit_fifo, (u8 *)&c, sizeof(c)) != in pci1xxxx_process_write_data()
460 writel(c, port->membase + UART_TX_BURST_FIFO); in pci1xxxx_process_write_data()
461 *valid_byte_count -= UART_BURST_SIZE; in pci1xxxx_process_write_data()
462 *data_empty_count -= UART_BURST_SIZE; in pci1xxxx_process_write_data()
463 valid_burst_count -= UART_BYTE_SIZE; in pci1xxxx_process_write_data()
469 if (!kfifo_get(&tport->xmit_fifo, &c)) in pci1xxxx_process_write_data()
471 writeb(c, port->membase + UART_TX_BYTE_FIFO); in pci1xxxx_process_write_data()
472 *data_empty_count -= UART_BYTE_SIZE; in pci1xxxx_process_write_data()
473 *valid_byte_count -= UART_BYTE_SIZE; in pci1xxxx_process_write_data()
480 kfifo_len(&tport->xmit_fifo) >= UART_BURST_SIZE) in pci1xxxx_process_write_data()
488 struct tty_port *tport = &port->state->port; in pci1xxxx_tx_burst()
492 if (port->x_char) { in pci1xxxx_tx_burst()
493 writeb(port->x_char, port->membase + UART_TX); in pci1xxxx_tx_burst()
494 port->icount.tx++; in pci1xxxx_tx_burst()
495 port->x_char = 0; in pci1xxxx_tx_burst()
499 if ((uart_tx_stopped(port)) || kfifo_is_empty(&tport->xmit_fifo)) { in pci1xxxx_tx_burst()
500 port->ops->stop_tx(port); in pci1xxxx_tx_burst()
505 valid_byte_count = kfifo_len(&tport->xmit_fifo); in pci1xxxx_tx_burst()
511 port->icount.tx++; in pci1xxxx_tx_burst()
512 if (kfifo_is_empty(&tport->xmit_fifo)) in pci1xxxx_tx_burst()
517 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in pci1xxxx_tx_burst()
525 if (kfifo_is_empty(&tport->xmit_fifo) && in pci1xxxx_tx_burst()
526 !(up->capabilities & UART_CAP_RPM)) in pci1xxxx_tx_burst()
527 port->ops->stop_tx(port); in pci1xxxx_tx_burst()
540 spin_lock_irqsave(&port->lock, flags); in pci1xxxx_handle_irq()
548 spin_unlock_irqrestore(&port->lock, flags); in pci1xxxx_handle_irq()
556 struct uart_port *port = &up->port; in pci1xxxx_port_suspend()
557 struct tty_port *tport = &port->state->port; in pci1xxxx_port_suspend()
562 mutex_lock(&tport->mutex); in pci1xxxx_port_suspend()
563 if (port->suspended == 0 && port->dev) { in pci1xxxx_port_suspend()
564 wakeup_mask = readb(up->port.membase + UART_WAKE_MASK_REG); in pci1xxxx_port_suspend()
567 port->mctrl &= ~TIOCM_OUT2; in pci1xxxx_port_suspend()
568 port->ops->set_mctrl(port, port->mctrl); in pci1xxxx_port_suspend()
574 writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG); in pci1xxxx_port_suspend()
575 mutex_unlock(&tport->mutex); in pci1xxxx_port_suspend()
583 struct uart_port *port = &up->port; in pci1xxxx_port_resume()
584 struct tty_port *tport = &port->state->port; in pci1xxxx_port_resume()
587 mutex_lock(&tport->mutex); in pci1xxxx_port_resume()
588 writeb(UART_BLOCK_SET_ACTIVE, port->membase + UART_ACTV_REG); in pci1xxxx_port_resume()
589 writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG); in pci1xxxx_port_resume()
591 if (port->suspended == 0) { in pci1xxxx_port_resume()
593 port->mctrl |= TIOCM_OUT2; in pci1xxxx_port_resume()
594 port->ops->set_mctrl(port, port->mctrl); in pci1xxxx_port_resume()
597 mutex_unlock(&tport->mutex); in pci1xxxx_port_resume()
609 for (i = 0; i < priv->nr; i++) { in pci1xxxx_suspend()
610 if (priv->line[i] >= 0) { in pci1xxxx_suspend()
611 serial8250_suspend_port(priv->line[i]); in pci1xxxx_suspend()
612 wakeup |= pci1xxxx_port_suspend(priv->line[i]); in pci1xxxx_suspend()
619 return -ENOMEM; in pci1xxxx_suspend()
646 return -ENOMEM; in pci1xxxx_resume()
653 for (i = 0; i < priv->nr; i++) { in pci1xxxx_resume()
654 if (priv->line[i] >= 0) { in pci1xxxx_resume()
655 pci1xxxx_port_resume(priv->line[i]); in pci1xxxx_resume()
656 serial8250_resume_port(priv->line[i]); in pci1xxxx_resume()
668 port->port.flags |= UPF_FIXED_TYPE | UPF_SKIP_TEST; in pci1xxxx_setup()
669 port->port.type = PORT_MCHP16550A; in pci1xxxx_setup()
680 port->port.uartclk = 64 * HZ_PER_MHZ; in pci1xxxx_setup()
681 port->port.set_termios = serial8250_do_set_termios; in pci1xxxx_setup()
682 port->port.get_divisor = pci1xxxx_get_divisor; in pci1xxxx_setup()
683 port->port.set_divisor = pci1xxxx_set_divisor; in pci1xxxx_setup()
684 port->port.rs485_config = pci1xxxx_rs485_config; in pci1xxxx_setup()
685 port->port.rs485_supported = pci1xxxx_rs485_supported; in pci1xxxx_setup()
689 * RTS workaround in mctrl is applicable only to B0. in pci1xxxx_setup()
692 port->port.handle_irq = pci1xxxx_handle_irq; in pci1xxxx_setup()
694 port->port.set_mctrl = pci1xxxx_set_mctrl; in pci1xxxx_setup()
700 writeb(UART_BLOCK_SET_ACTIVE, port->port.membase + UART_ACTV_REG); in pci1xxxx_setup()
701 writeb(UART_WAKE_SRCS, port->port.membase + UART_WAKE_REG); in pci1xxxx_setup()
702 writeb(UART_WAKE_N_PIN, port->port.membase + UART_WAKE_MASK_REG); in pci1xxxx_setup()
712 while (i--) { in pci1xxxx_get_max_port()
713 if (logical_to_physical_port_idx[subsys_dev][i] != -1) in pci1xxxx_get_max_port()
744 regval = readl(priv->membase + UART_DEV_REV_REG); in pci1xxxx_get_device_revision()
745 priv->dev_rev = regval & UART_DEV_REV_MASK; in pci1xxxx_get_device_revision()
755 struct device *dev = &pdev->dev; in pci1xxxx_serial_probe()
774 return -ENOMEM; in pci1xxxx_serial_probe()
776 priv->membase = pci_ioremap_bar(pdev, 0); in pci1xxxx_serial_probe()
777 if (!priv->membase) in pci1xxxx_serial_probe()
778 return -ENOMEM; in pci1xxxx_serial_probe()
786 priv->nr = nr_ports; in pci1xxxx_serial_probe()
788 subsys_dev = pdev->subsystem_device; in pci1xxxx_serial_probe()
793 pci_iounmap(pdev, priv->membase); in pci1xxxx_serial_probe()
802 writeb(UART_PCI_CTRL_SET_MULTIPLE_MSI, priv->membase + UART_PCI_CTRL_REG); in pci1xxxx_serial_probe()
805 priv->line[i] = -ENODEV; in pci1xxxx_serial_probe()
814 rc = pci1xxxx_setup(pdev, &uart, port_idx, priv->dev_rev); in pci1xxxx_serial_probe()
820 priv->line[i] = serial8250_register_8250_port(&uart); in pci1xxxx_serial_probe()
821 if (priv->line[i] < 0) { in pci1xxxx_serial_probe()
825 priv->line[i]); in pci1xxxx_serial_probe()
839 for (i = 0; i < priv->nr; i++) { in pci1xxxx_serial_remove()
840 if (priv->line[i] >= 0) in pci1xxxx_serial_remove()
841 serial8250_unregister_port(priv->line[i]); in pci1xxxx_serial_remove()
845 pci_iounmap(dev, priv->membase); in pci1xxxx_serial_remove()