153 	void __iomem *membase;  member
166 	writel(UART_SYSLOCK, port->membase + UART_SYSLOCK_REG);  in pci1xxxx_set_sys_lock()
167 	return readl(port->membase + UART_SYSLOCK_REG);  in pci1xxxx_set_sys_lock()
182 	writel(0x0, port->membase + UART_SYSLOCK_REG);  in pci1xxxx_release_sys_lock()
261 		writel(UART_BIT_DIVISOR_8, port->membase + FRAC_DIV_CFG_REG);  in pci1xxxx_set_divisor()
263 		writel(UART_BIT_DIVISOR_16, port->membase + FRAC_DIV_CFG_REG);  in pci1xxxx_set_divisor()
266 	       port->membase + UART_BAUD_CLK_DIVISOR_REG);  in pci1xxxx_set_divisor()
276 	adcl_cfg_reg = readl(port->membase + ADCL_CFG_REG);  in pci1xxxx_set_mctrl()
282 	modem_ctl_reg = readl(port->membase + UART_MODEM_CTL_REG);  in pci1xxxx_set_mctrl()
287 		line_stat_reg = readl(port->membase + UART_LINE_STAT_REG);  in pci1xxxx_set_mctrl()
289 			fract_div_cfg_reg = readl(port->membase +  in pci1xxxx_set_mctrl()
294 			       port->membase + FRAC_DIV_CFG_REG);  in pci1xxxx_set_mctrl()
299 			       port->membase + ADCL_CFG_REG);  in pci1xxxx_set_mctrl()
302 			writel(adcl_cfg_reg, port->membase + ADCL_CFG_REG);  in pci1xxxx_set_mctrl()
304 			writel(fract_div_cfg_reg, port->membase +  in pci1xxxx_set_mctrl()
321 	frac_div = readl(port->membase + FRAC_DIV_CFG_REG);  in pci1xxxx_rs485_config()
339 			clock_div = readl(port->membase + UART_BAUD_CLK_DIVISOR_REG);  in pci1xxxx_rs485_config()
356 	writel(mode_cfg, port->membase + ADCL_CFG_REG);  in pci1xxxx_rs485_config()
364 	status = readl(port->membase + UART_BURST_STATUS_REG);  in pci1xxxx_read_burst_status()
368 			       port->membase + UART_FIFO_CTL);  in pci1xxxx_read_burst_status()
398 		*burst_buf = readl(port->membase + UART_RX_BURST_FIFO);  in pci1xxxx_process_read_data()
406 		rx_buff[*buff_index] = readb(port->membase +  in pci1xxxx_process_read_data()
460 		writel(c, port->membase + UART_TX_BURST_FIFO);  in pci1xxxx_process_write_data()
471 		writeb(c, port->membase + UART_TX_BYTE_FIFO);  in pci1xxxx_process_write_data()
493 		writeb(port->x_char, port->membase + UART_TX);  in pci1xxxx_tx_burst()
564 		wakeup_mask = readb(up->port.membase + UART_WAKE_MASK_REG);  in pci1xxxx_port_suspend()
574 	writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG);  in pci1xxxx_port_suspend()
588 	writeb(UART_BLOCK_SET_ACTIVE, port->membase + UART_ACTV_REG);  in pci1xxxx_port_resume()
589 	writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG);  in pci1xxxx_port_resume()
700 	writeb(UART_BLOCK_SET_ACTIVE, port->port.membase + UART_ACTV_REG);  in pci1xxxx_setup()
701 	writeb(UART_WAKE_SRCS, port->port.membase + UART_WAKE_REG);  in pci1xxxx_setup()
702 	writeb(UART_WAKE_N_PIN, port->port.membase + UART_WAKE_MASK_REG);  in pci1xxxx_setup()
744 	regval = readl(priv->membase + UART_DEV_REV_REG);  in pci1xxxx_get_device_revision()
776 	priv->membase = pci_ioremap_bar(pdev, 0);  in pci1xxxx_serial_probe()
777 	if (!priv->membase)  in pci1xxxx_serial_probe()
793 		pci_iounmap(pdev, priv->membase);  in pci1xxxx_serial_probe()
802 		writeb(UART_PCI_CTRL_SET_MULTIPLE_MSI, priv->membase + UART_PCI_CTRL_REG);  in pci1xxxx_serial_probe()
845 	pci_iounmap(dev, priv->membase);  in pci1xxxx_serial_remove()