Lines Matching +full:8 +full:- +full:port
1 // SPDX-License-Identifier: GPL-2.0
3 * Probe module for 8250/16550-type PCI serial ports.
98 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
104 * > 0 - number of ports
105 * = 0 - use board->num_ports
106 * < 0 - error
156 "Please send the output of lspci -vv, this\n" in moan_device()
159 "modem board to <linux-[email protected]>.\n", in moan_device()
160 str, dev->vendor, dev->device, in moan_device()
161 dev->subsystem_vendor, dev->subsystem_device); in moan_device()
165 setup_port(struct serial_private *priv, struct uart_8250_port *port, in setup_port() argument
168 return serial8250_pci_setup_port(priv->dev, port, bar, offset, regshift); in setup_port()
172 * ADDI-DATA GmbH communication cards <info@addi-data.com>
176 struct uart_8250_port *port, int idx) in addidata_apci7800_setup() argument
178 unsigned int bar = 0, offset = board->first_offset; in addidata_apci7800_setup()
179 bar = FL_GET_BASE(board->flags); in addidata_apci7800_setup()
182 offset += idx * board->uart_offset; in addidata_apci7800_setup()
185 offset += ((idx - 2) * board->uart_offset); in addidata_apci7800_setup()
188 offset += ((idx - 4) * board->uart_offset); in addidata_apci7800_setup()
191 offset += ((idx - 6) * board->uart_offset); in addidata_apci7800_setup()
194 return setup_port(priv, port, bar, offset, board->reg_shift); in addidata_apci7800_setup()
199 * Not that ugly ;) -- HW
203 struct uart_8250_port *port, int idx) in afavlab_setup() argument
205 unsigned int bar, offset = board->first_offset; in afavlab_setup()
207 bar = FL_GET_BASE(board->flags); in afavlab_setup()
212 offset += (idx - 4) * board->uart_offset; in afavlab_setup()
215 return setup_port(priv, port, bar, offset, board->reg_shift); in afavlab_setup()
220 * different versions. N-class, L2000 and A500 have two Diva chips, each
229 switch (dev->subsystem_device) { in pci_hp_diva_init()
252 * HP's Diva chip puts the 4th/5th serial port further out, and
258 struct uart_8250_port *port, int idx) in pci_hp_diva_setup() argument
260 unsigned int offset = board->first_offset; in pci_hp_diva_setup()
261 unsigned int bar = FL_GET_BASE(board->flags); in pci_hp_diva_setup()
263 switch (priv->dev->subsystem_device) { in pci_hp_diva_setup()
278 offset += idx * board->uart_offset; in pci_hp_diva_setup()
280 return setup_port(priv, port, bar, offset, board->reg_shift); in pci_hp_diva_setup()
290 if (!(dev->subsystem_device & 0x1000)) in pci_inteli960ni_init()
291 return -ENODEV; in pci_inteli960ni_init()
297 return -ENODEV; in pci_inteli960ni_init()
319 if (dev->vendor == PCI_VENDOR_ID_PANACOM || in pci_plx9050_init()
320 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) in pci_plx9050_init()
323 if ((dev->vendor == PCI_VENDOR_ID_PLX) && in pci_plx9050_init()
324 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) in pci_plx9050_init()
339 return -ENOMEM; in pci_plx9050_init()
424 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
427 struct uart_8250_port *port, int idx) in sbs_setup() argument
429 unsigned int bar, offset = board->first_offset; in sbs_setup()
435 offset += idx * board->uart_offset; in sbs_setup()
436 } else if (idx < 8) { in sbs_setup()
438 offset += idx * board->uart_offset + 0xC00; in sbs_setup()
439 } else /* we have only 8 ports on PMC-OCTALPRO */ in sbs_setup()
442 return setup_port(priv, port, bar, offset, board->reg_shift); in sbs_setup()
452 /* global control register offset for SBS PMC-OctalPro */
462 return -ENOMEM; in sbs_init()
463 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ in sbs_init()
468 /* Set bit-2 (INTENABLE) of Control Register */ in sbs_init()
476 * Disables the global interrupt of PMC-OctalPro
505 * - 10x cards have control registers in IO and/or memory space;
506 * - 20x cards have control registers in standard PCI configuration space.
525 switch (dev->device & 0xfff8) { in pci_siig10x_init()
539 return -ENOMEM; in pci_siig10x_init()
559 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || in pci_siig20x_init()
560 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { in pci_siig20x_init()
569 unsigned int type = dev->device & 0xff00; in pci_siig_init()
577 return -ENODEV; in pci_siig_init()
582 struct uart_8250_port *port, int idx) in pci_siig_setup() argument
584 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; in pci_siig_setup()
588 offset = (idx - 4) * 8; in pci_siig_setup()
591 return setup_port(priv, port, bar, offset, 0); in pci_siig_setup()
630 { 8, timedia_eight_port }
636 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
643 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) in pci_timedia_probe()
645 if ((dev->subsystem_device & 0x00f0) >= 0x70) { in pci_timedia_probe()
647 dev->subsystem_device); in pci_timedia_probe()
648 return -ENODEV; in pci_timedia_probe()
662 if (dev->subsystem_device == ids[j]) in pci_timedia_init()
670 * Ugh, this is ugly as all hell --- TYT
675 struct uart_8250_port *port, int idx) in pci_timedia_setup() argument
677 unsigned int bar = 0, offset = board->first_offset; in pci_timedia_setup()
684 offset = board->uart_offset; in pci_timedia_setup()
691 offset = board->uart_offset; in pci_timedia_setup()
697 bar = idx - 2; in pci_timedia_setup()
700 return setup_port(priv, port, bar, offset, board->reg_shift); in pci_timedia_setup()
709 struct uart_8250_port *port, int idx) in titan_400l_800l_setup() argument
711 unsigned int bar, offset = board->first_offset; in titan_400l_800l_setup()
722 offset = (idx - 2) * board->uart_offset; in titan_400l_800l_setup()
725 return setup_port(priv, port, bar, offset, board->reg_shift); in titan_400l_800l_setup()
746 return -ENOMEM; in pci_ni8420_init()
777 return -ENOMEM; in pci_ni8430_init()
784 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]); in pci_ni8430_init()
803 /* UART Port Control Register */
810 struct uart_8250_port *port, int idx) in pci_ni8430_setup() argument
812 struct pci_dev *dev = priv->dev; in pci_ni8430_setup()
814 unsigned int bar, offset = board->first_offset; in pci_ni8430_setup()
816 if (idx >= board->num_ports) in pci_ni8430_setup()
819 bar = FL_GET_BASE(board->flags); in pci_ni8430_setup()
820 offset += idx * board->uart_offset; in pci_ni8430_setup()
824 return -ENOMEM; in pci_ni8430_setup()
832 return setup_port(priv, port, bar, offset, board->reg_shift); in pci_ni8430_setup()
837 struct uart_8250_port *port, int idx) in pci_netmos_9900_setup() argument
841 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) && in pci_netmos_9900_setup()
842 (priv->dev->subsystem_device & 0xff00) == 0x3000) { in pci_netmos_9900_setup()
848 return setup_port(priv, port, bar, 0, board->reg_shift); in pci_netmos_9900_setup()
851 return pci_default_setup(priv, board, port, idx); in pci_netmos_9900_setup()
857 * 9900 has varying capabilities and can cascade to sub-controllers
864 unsigned int c = dev->class; in pci_netmos_9900_numports()
873 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { in pci_netmos_9900_numports()
880 sub_serports = dev->subsystem_device & 0xf; in pci_netmos_9900_numports()
884 pci_err(dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n"); in pci_netmos_9900_numports()
895 unsigned int num_serial = dev->subsystem_device & 0xf; in pci_netmos_init()
897 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) || in pci_netmos_init()
898 (dev->device == PCI_DEVICE_ID_NETMOS_9865)) in pci_netmos_init()
901 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && in pci_netmos_init()
902 dev->subsystem_device == 0x0299) in pci_netmos_init()
905 switch (dev->device) { /* FALLTHROUGH on all */ in pci_netmos_init()
919 return -ENODEV; in pci_netmos_init()
926 * These chips are available with optionally one parallel port and up to
944 /* I/O space size (bits 26-24; 8 bytes = 011b) */
946 /* I/O space size (bits 26-24; 32 bytes = 101b) */
964 /* search for the base-ioport */ in pci_ite887x_init()
969 /* write POSIO0R - speed | size | ioport */ in pci_ite887x_init()
973 /* write INTCBAR - ioport */ in pci_ite887x_init()
981 release_region(iobase->start, ITE_887x_IOSIZE); in pci_ite887x_init()
987 return -ENODEV; in pci_ite887x_init()
991 type = inb(iobase->start + 0x18) & 0x0f; in pci_ite887x_init()
1009 ret = -ENODEV; in pci_ite887x_init()
1014 /* read the I/O port from the device */ in pci_ite887x_init()
1031 miscr &= ~(0xf << (12 - 4 * i)); in pci_ite887x_init()
1033 miscr |= 1 << (23 - i); in pci_ite887x_init()
1040 release_region(iobase->start, ITE_887x_IOSIZE); in pci_ite887x_init()
1049 /* the ioport is bit 0-15 in POSIO0R */ in pci_ite887x_exit()
1065 if (dev->vendor == PCI_VENDOR_ID_OXSEMI && in pci_oxsemi_tornado_p()
1066 (dev->device & 0xf000) != 0xc000) in pci_oxsemi_tornado_p()
1070 if (dev->vendor == PCI_VENDOR_ID_ENDRUN && in pci_oxsemi_tornado_p()
1071 (dev->device & 0xf000) != 0xe000) in pci_oxsemi_tornado_p()
1091 return -ENOMEM; in pci_oxsemi_tornado_init()
1099 dev->vendor == PCI_VENDOR_ID_ENDRUN ? in pci_oxsemi_tornado_init()
1106 /* Tornado-specific constants for the TCR and CPR registers; see below. */
1116 * steps of 1/8. Therefore to make calculations on integers we need
1124 * unsigned 16-bit integer.
1130 * by 8. The table is sorted by the decreasing value of the oversampling
1138 * divisor required would be out of its unsigned 16-bit integer range.
1141 * 4-bit value of the oversampling rate and the 9-bit value of the clock
1144 static unsigned int pci_oxsemi_tornado_get_divisor(struct uart_port *port, in pci_oxsemi_tornado_get_divisor() argument
1150 { 16, 10, }, { 16, 9, }, { 16, 8, }, { 15, 17, }, in pci_oxsemi_tornado_get_divisor()
1153 { 15, 8, }, { 14, 18, }, { 14, 17, }, { 14, 14, }, in pci_oxsemi_tornado_get_divisor()
1155 { 14, 9, }, { 14, 8, }, { 13, 19, }, { 13, 18, }, in pci_oxsemi_tornado_get_divisor()
1157 { 13, 10, }, { 13, 9, }, { 13, 8, }, { 12, 19, }, in pci_oxsemi_tornado_get_divisor()
1159 { 12, 8, }, { 11, 23, }, { 11, 22, }, { 11, 21, }, in pci_oxsemi_tornado_get_divisor()
1161 { 11, 11, }, { 11, 10, }, { 11, 9, }, { 11, 8, }, in pci_oxsemi_tornado_get_divisor()
1163 { 10, 17, }, { 10, 10, }, { 10, 9, }, { 10, 8, }, in pci_oxsemi_tornado_get_divisor()
1165 { 9, 18, }, { 9, 17, }, { 9, 9, }, { 9, 8, }, in pci_oxsemi_tornado_get_divisor()
1166 { 8, 31, }, { 8, 29, }, { 8, 23, }, { 8, 19, }, in pci_oxsemi_tornado_get_divisor()
1167 { 8, 17, }, { 8, 8, }, { 7, 35, }, { 7, 31, }, in pci_oxsemi_tornado_get_divisor()
1171 { 7, 9, }, { 7, 8, }, { 6, 41, }, { 6, 37, }, in pci_oxsemi_tornado_get_divisor()
1174 { 6, 9, }, { 6, 8, }, { 5, 67, }, { 5, 47, }, in pci_oxsemi_tornado_get_divisor()
1178 { 5, 10, }, { 5, 9, }, { 5, 8, }, { 4, 61, }, in pci_oxsemi_tornado_get_divisor()
1182 { 4, 9, }, { 4, 8, }, in pci_oxsemi_tornado_get_divisor()
1186 unsigned int sclk = port->uartclk * 2; in pci_oxsemi_tornado_get_divisor()
1196 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { in pci_oxsemi_tornado_get_divisor()
1197 unsigned int cust_div = port->custom_divisor; in pci_oxsemi_tornado_get_divisor()
1218 srem = spre - srem; in pci_oxsemi_tornado_get_divisor()
1252 *frac = (cpr << 8) | (tcr & OXSEMI_TORNADO_TCR_MASK); in pci_oxsemi_tornado_get_divisor()
1264 static void pci_oxsemi_tornado_set_divisor(struct uart_port *port, in pci_oxsemi_tornado_set_divisor() argument
1269 struct uart_8250_port *up = up_to_u8250p(port); in pci_oxsemi_tornado_set_divisor()
1271 u8 cpr = quot_frac >> 8; in pci_oxsemi_tornado_set_divisor()
1277 serial8250_do_set_divisor(port, baud, quot); in pci_oxsemi_tornado_set_divisor()
1281 * For Tornado devices we force MCR[7] set for the Divide-by-M N/8 baud rate
1284 static void pci_oxsemi_tornado_set_mctrl(struct uart_port *port, in pci_oxsemi_tornado_set_mctrl() argument
1287 struct uart_8250_port *up = up_to_u8250p(port); in pci_oxsemi_tornado_set_mctrl()
1289 up->mcr |= UART_MCR_CLKSEL; in pci_oxsemi_tornado_set_mctrl()
1290 serial8250_do_set_mctrl(port, mctrl); in pci_oxsemi_tornado_set_mctrl()
1301 struct pci_dev *dev = priv->dev; in pci_oxsemi_tornado_setup()
1304 up->port.flags |= UPF_FULL_PROBE; in pci_oxsemi_tornado_setup()
1305 up->port.get_divisor = pci_oxsemi_tornado_get_divisor; in pci_oxsemi_tornado_setup()
1306 up->port.set_divisor = pci_oxsemi_tornado_set_divisor; in pci_oxsemi_tornado_setup()
1307 up->port.set_mctrl = pci_oxsemi_tornado_set_mctrl; in pci_oxsemi_tornado_setup()
1352 static int pci_quatech_rqopr(struct uart_8250_port *port) in pci_quatech_rqopr() argument
1354 unsigned long base = port->port.iobase; in pci_quatech_rqopr()
1364 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr) in pci_quatech_wqopr() argument
1366 unsigned long base = port->port.iobase; in pci_quatech_wqopr()
1376 static int pci_quatech_rqmcr(struct uart_8250_port *port) in pci_quatech_rqmcr() argument
1378 unsigned long base = port->port.iobase; in pci_quatech_rqmcr()
1392 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr) in pci_quatech_wqmcr() argument
1394 unsigned long base = port->port.iobase; in pci_quatech_wqmcr()
1406 static int pci_quatech_has_qmcr(struct uart_8250_port *port) in pci_quatech_has_qmcr() argument
1408 unsigned long base = port->port.iobase; in pci_quatech_has_qmcr()
1424 static int pci_quatech_test(struct uart_8250_port *port) in pci_quatech_test() argument
1428 qopr = pci_quatech_rqopr(port); in pci_quatech_test()
1429 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1); in pci_quatech_test()
1430 reg = pci_quatech_rqopr(port) & 0xC0; in pci_quatech_test()
1432 return -EINVAL; in pci_quatech_test()
1433 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2); in pci_quatech_test()
1434 reg = pci_quatech_rqopr(port) & 0xC0; in pci_quatech_test()
1436 return -EINVAL; in pci_quatech_test()
1437 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3); in pci_quatech_test()
1438 reg = pci_quatech_rqopr(port) & 0xC0; in pci_quatech_test()
1440 return -EINVAL; in pci_quatech_test()
1441 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4); in pci_quatech_test()
1442 reg = pci_quatech_rqopr(port) & 0xC0; in pci_quatech_test()
1444 return -EINVAL; in pci_quatech_test()
1446 pci_quatech_wqopr(port, qopr); in pci_quatech_test()
1450 static int pci_quatech_clock(struct uart_8250_port *port) in pci_quatech_clock() argument
1455 if (pci_quatech_test(port) < 0) in pci_quatech_clock()
1458 qopr = pci_quatech_rqopr(port); in pci_quatech_clock()
1460 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8); in pci_quatech_clock()
1461 reg = pci_quatech_rqopr(port); in pci_quatech_clock()
1466 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8); in pci_quatech_clock()
1467 reg = pci_quatech_rqopr(port); in pci_quatech_clock()
1490 pci_quatech_wqopr(port, qopr); in pci_quatech_clock()
1494 static int pci_quatech_rs422(struct uart_8250_port *port) in pci_quatech_rs422() argument
1499 if (!pci_quatech_has_qmcr(port)) in pci_quatech_rs422()
1501 qmcr = pci_quatech_rqmcr(port); in pci_quatech_rs422()
1502 pci_quatech_wqmcr(port, 0xFF); in pci_quatech_rs422()
1503 if (pci_quatech_rqmcr(port)) in pci_quatech_rs422()
1505 pci_quatech_wqmcr(port, qmcr); in pci_quatech_rs422()
1519 amcc = match->driver_data; in pci_quatech_init()
1521 pci_err(dev, "unknown port type '0x%04X'.\n", dev->device); in pci_quatech_init()
1539 struct uart_8250_port *port, int idx) in pci_quatech_setup() argument
1542 return serial_8250_warn_need_ioport(priv->dev); in pci_quatech_setup()
1545 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags)); in pci_quatech_setup()
1547 port->port.uartclk = pci_quatech_clock(port); in pci_quatech_setup()
1549 if (pci_quatech_rs422(port)) in pci_quatech_setup()
1550 pci_warn(priv->dev, "software control of RS422 features not currently supported.\n"); in pci_quatech_setup()
1551 return pci_default_setup(priv, board, port, idx); in pci_quatech_setup()
1556 struct uart_8250_port *port, int idx) in pci_default_setup() argument
1558 unsigned int bar, offset = board->first_offset, maxnr; in pci_default_setup()
1560 bar = FL_GET_BASE(board->flags); in pci_default_setup()
1561 if (board->flags & FL_BASE_BARS) in pci_default_setup()
1564 offset += idx * board->uart_offset; in pci_default_setup()
1566 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> in pci_default_setup()
1567 (board->reg_shift + 3); in pci_default_setup()
1569 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) in pci_default_setup()
1572 return setup_port(priv, port, bar, offset, board->reg_shift); in pci_default_setup()
1578 struct uart_8250_port *port, int idx) in ce4100_serial_setup() argument
1582 ret = setup_port(priv, port, idx, 0, board->reg_shift); in ce4100_serial_setup()
1583 port->port.iotype = UPIO_MEM32; in ce4100_serial_setup()
1584 port->port.type = PORT_XSCALE; in ce4100_serial_setup()
1585 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); in ce4100_serial_setup()
1586 port->port.regshift = 2; in ce4100_serial_setup()
1594 struct uart_8250_port *port, int idx) in pci_omegapci_setup() argument
1596 return setup_port(priv, port, 2, idx * 8, 0); in pci_omegapci_setup()
1602 struct uart_8250_port *port, int idx) in pci_brcm_trumanage_setup() argument
1604 int ret = pci_default_setup(priv, board, port, idx); in pci_brcm_trumanage_setup()
1606 port->port.type = PORT_BRCM_TRUMANAGE; in pci_brcm_trumanage_setup()
1607 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); in pci_brcm_trumanage_setup()
1617 static int pci_fintek_rs485_config(struct uart_port *port, struct ktermios *termios, in pci_fintek_rs485_config() argument
1620 struct pci_dev *pci_dev = to_pci_dev(port->dev); in pci_fintek_rs485_config()
1622 u8 *index = (u8 *) port->private_data; in pci_fintek_rs485_config()
1624 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting); in pci_fintek_rs485_config()
1626 if (rs485->flags & SER_RS485_ENABLED) { in pci_fintek_rs485_config()
1630 if (rs485->flags & SER_RS485_RTS_ON_SEND) { in pci_fintek_rs485_config()
1642 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting); in pci_fintek_rs485_config()
1654 struct uart_8250_port *port, int idx) in pci_fintek_setup() argument
1656 struct pci_dev *pdev = priv->dev; in pci_fintek_setup()
1671 port->port.iotype = UPIO_PORT; in pci_fintek_setup()
1672 port->port.iobase = iobase; in pci_fintek_setup()
1673 port->port.rs485_config = pci_fintek_rs485_config; in pci_fintek_setup()
1674 port->port.rs485_supported = pci_fintek_rs485_supported; in pci_fintek_setup()
1676 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL); in pci_fintek_setup()
1678 return -ENOMEM; in pci_fintek_setup()
1682 port->port.private_data = data; in pci_fintek_setup()
1701 return -ENODEV; in pci_fintek_init()
1703 switch (dev->device) { in pci_fintek_init()
1705 case 0x1108: /* 8 ports */ in pci_fintek_init()
1706 max_port = dev->device & 0xff; in pci_fintek_init()
1712 return -EINVAL; in pci_fintek_init()
1724 /* Calculate Real IO Port */ in pci_fintek_init()
1725 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8; in pci_fintek_init()
1727 /* Enable UART I/O port */ in pci_fintek_init()
1730 /* Select 128-byte FIFO and 8x FIFO threshold */ in pci_fintek_init()
1739 (u8)((iobase & 0xff00) >> 8)); in pci_fintek_init()
1741 pci_write_config_byte(dev, config_base + 0x06, dev->irq); in pci_fintek_init()
1744 /* First init without port data in pci_fintek_init()
1756 struct f815xxa_data *data = p->private_data; in f815xxa_mem_serial_out()
1759 spin_lock_irqsave(&data->lock, flags); in f815xxa_mem_serial_out()
1760 writeb(value, p->membase + offset); in f815xxa_mem_serial_out()
1761 readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */ in f815xxa_mem_serial_out()
1762 spin_unlock_irqrestore(&data->lock, flags); in f815xxa_mem_serial_out()
1767 struct uart_8250_port *port, int idx) in pci_fintek_f815xxa_setup() argument
1769 struct pci_dev *pdev = priv->dev; in pci_fintek_f815xxa_setup()
1772 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); in pci_fintek_f815xxa_setup()
1774 return -ENOMEM; in pci_fintek_f815xxa_setup()
1776 data->idx = idx; in pci_fintek_f815xxa_setup()
1777 spin_lock_init(&data->lock); in pci_fintek_f815xxa_setup()
1779 port->port.private_data = data; in pci_fintek_f815xxa_setup()
1780 port->port.iotype = UPIO_MEM; in pci_fintek_f815xxa_setup()
1781 port->port.flags |= UPF_IOREMAP; in pci_fintek_f815xxa_setup()
1782 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx; in pci_fintek_f815xxa_setup()
1783 port->port.serial_out = f815xxa_mem_serial_out; in pci_fintek_f815xxa_setup()
1794 return -ENODEV; in pci_fintek_f815xxa_init()
1796 switch (dev->device) { in pci_fintek_f815xxa_init()
1798 case 0x1208: /* 8 ports */ in pci_fintek_f815xxa_init()
1799 max_port = dev->device & 0xff; in pci_fintek_f815xxa_init()
1805 return -EINVAL; in pci_fintek_f815xxa_init()
1815 /* Select 128-byte FIFO and 8x FIFO threshold */ in pci_fintek_f815xxa_init()
1818 /* Enable UART I/O port */ in pci_fintek_f815xxa_init()
1827 struct uart_8250_port *port, int idx) in skip_tx_en_setup() argument
1829 port->port.quirks |= UPQ_NO_TXEN_TEST; in skip_tx_en_setup()
1830 pci_dbg(priv->dev, in skip_tx_en_setup()
1832 priv->dev->vendor, priv->dev->device, in skip_tx_en_setup()
1833 priv->dev->subsystem_vendor, priv->dev->subsystem_device); in skip_tx_en_setup()
1835 return pci_default_setup(priv, board, port, idx); in skip_tx_en_setup()
1856 * port registers could return 0 momentarily. Functions like in kt_serial_in()
1861 * that instead. up->ier should be the same value as what is in kt_serial_in()
1864 val = inb(p->iobase + offset); in kt_serial_in()
1867 val = up->ier; in kt_serial_in()
1874 struct uart_8250_port *port, int idx) in kt_serial_setup() argument
1877 return serial_8250_warn_need_ioport(priv->dev); in kt_serial_setup()
1879 port->port.flags |= UPF_BUG_THRE; in kt_serial_setup()
1880 port->port.serial_in = kt_serial_in; in kt_serial_setup()
1881 port->port.handle_break = kt_handle_break; in kt_serial_setup()
1882 return skip_tx_en_setup(priv, board, port, idx); in kt_serial_setup()
1888 return -ENODEV; in pci_eg20t_init()
1897 struct uart_8250_port *port, int idx) in pci_wch_ch353_setup() argument
1900 return serial_8250_warn_need_ioport(priv->dev); in pci_wch_ch353_setup()
1902 port->port.flags |= UPF_FIXED_TYPE; in pci_wch_ch353_setup()
1903 port->port.type = PORT_16550A; in pci_wch_ch353_setup()
1904 return pci_default_setup(priv, board, port, idx); in pci_wch_ch353_setup()
1910 struct uart_8250_port *port, int idx) in pci_wch_ch355_setup() argument
1913 return serial_8250_warn_need_ioport(priv->dev); in pci_wch_ch355_setup()
1915 port->port.flags |= UPF_FIXED_TYPE; in pci_wch_ch355_setup()
1916 port->port.type = PORT_16550A; in pci_wch_ch355_setup()
1917 return pci_default_setup(priv, board, port, idx); in pci_wch_ch355_setup()
1923 struct uart_8250_port *port, int idx) in pci_wch_ch38x_setup() argument
1926 return serial_8250_warn_need_ioport(priv->dev); in pci_wch_ch38x_setup()
1928 port->port.flags |= UPF_FIXED_TYPE; in pci_wch_ch38x_setup()
1929 port->port.type = PORT_16850; in pci_wch_ch38x_setup()
1930 return pci_default_setup(priv, board, port, idx); in pci_wch_ch38x_setup()
1945 switch (dev->device) { in pci_wch_ch38x_init()
1946 case 0x3853: /* 8 ports */ in pci_wch_ch38x_init()
1947 max_port = 8; in pci_wch_ch38x_init()
1950 return -EINVAL; in pci_wch_ch38x_init()
1976 struct uart_8250_port *port, int idx) in pci_sunix_setup() argument
1981 port->port.flags |= UPF_FIXED_TYPE; in pci_sunix_setup()
1982 port->port.type = PORT_SUNIX; in pci_sunix_setup()
1986 offset = idx * board->uart_offset; in pci_sunix_setup()
1989 idx -= 4; in pci_sunix_setup()
1991 offset = idx * 64 + offset * board->uart_offset; in pci_sunix_setup()
1994 return setup_port(priv, port, bar, offset, 0); in pci_sunix_setup()
2021 return 8; in moxa_get_nports()
2042 switch (dev->device & 0x0F00) { in pci_moxa_supported_rs()
2078 unsigned short device = dev->device; in pci_moxa_init()
2113 struct uart_8250_port *port, int idx) in pci_moxa_setup() argument
2115 unsigned int bar = FL_GET_BASE(board->flags); in pci_moxa_setup()
2119 return serial_8250_warn_need_ioport(priv->dev); in pci_moxa_setup()
2121 if (board->num_ports == 4 && idx == 3) in pci_moxa_setup()
2122 offset = 7 * board->uart_offset; in pci_moxa_setup()
2124 offset = idx * board->uart_offset; in pci_moxa_setup()
2126 return setup_port(priv, port, bar, offset, 0); in pci_moxa_setup()
2130 * Master list of serial port init/setup/exit quirks.
2131 * This does not describe the general nature of the port.
2139 * ADDI-DATA GmbH communication cards <info@addi-data.com>
2149 * AFAVLAB cards - these may be called via parport_serial
2419 * SBS Technologies, Inc., PMC-OCTALPRO 232
2431 * SBS Technologies, Inc., PMC-OCTALPRO 422
2443 * SBS Technologies, Inc., P-Octal 232
2455 * SBS Technologies, Inc., P-Octal 422
2467 * SIIG cards - these may be called via parport_serial
2535 * Netmos cards - these may be called via parport_serial
2584 * Brainboxes devices - all Oxsemi based
2819 * Cronyx Omega PCI (PLX-chip based)
2900 /* WCH CH384 8S card (16850 clone) */
3002 if (quirk_id_matches(quirk->vendor, dev->vendor) && in find_quirk()
3003 quirk_id_matches(quirk->device, dev->device) && in find_quirk()
3004 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && in find_quirk()
3005 quirk_id_matches(quirk->subdevice, dev->subsystem_device)) in find_quirk()
3023 * offsetinhex = offset for each sequential port (in hex)
3124 * Board-specific versions.
3178 * uart_offset - the space between channels
3179 * reg_shift - describes how the UART registers are mapped
3181 * For example IER register on SBS, Inc. PMC-OctPro is located at
3192 .uart_offset = 8,
3198 .uart_offset = 8,
3204 .uart_offset = 8,
3210 .uart_offset = 8,
3216 .uart_offset = 8,
3220 .num_ports = 8,
3222 .uart_offset = 8,
3228 .uart_offset = 8,
3234 .uart_offset = 8,
3240 .uart_offset = 8,
3247 .uart_offset = 8,
3254 .uart_offset = 8,
3261 .uart_offset = 8,
3268 .uart_offset = 8,
3274 .uart_offset = 8,
3281 .uart_offset = 8,
3288 .uart_offset = 8,
3294 .uart_offset = 8,
3300 .uart_offset = 8,
3304 .num_ports = 8,
3306 .uart_offset = 8,
3313 .uart_offset = 8,
3319 .uart_offset = 8,
3325 .uart_offset = 8,
3332 .uart_offset = 8,
3338 .uart_offset = 8,
3344 .uart_offset = 8,
3348 .num_ports = 8,
3350 .uart_offset = 8,
3357 .uart_offset = 8,
3363 .uart_offset = 8,
3369 .uart_offset = 8,
3373 .num_ports = 8,
3375 .uart_offset = 8,
3381 .uart_offset = 8,
3388 .uart_offset = 8,
3394 .uart_offset = 8,
3400 .uart_offset = 8,
3404 .num_ports = 8,
3406 .uart_offset = 8,
3412 .uart_offset = 8,
3419 .uart_offset = 8,
3425 .uart_offset = 8,
3431 .uart_offset = 8,
3438 .uart_offset = 8,
3445 .uart_offset = 8,
3451 .uart_offset = 8,
3457 .uart_offset = 8,
3461 .num_ports = 8,
3463 .uart_offset = 8,
3470 .uart_offset = 8,
3476 .uart_offset = 8,
3482 .uart_offset = 8,
3486 .num_ports = 8,
3488 .uart_offset = 8,
3495 .uart_offset = 8,
3501 .uart_offset = 8,
3505 .num_ports = 8,
3507 .uart_offset = 8,
3513 .uart_offset = 8,
3520 .uart_offset = 8,
3526 .uart_offset = 8,
3530 .num_ports = 8,
3532 .uart_offset = 8,
3537 .num_ports = 8,
3539 .uart_offset = 8,
3546 .uart_offset = 8,
3552 .uart_offset = 8,
3558 .uart_offset = 8,
3565 .uart_offset = 8,
3571 .uart_offset = 8,
3578 .uart_offset = 8,
3584 .uart_offset = 8,
3588 .num_ports = 8,
3590 .uart_offset = 8,
3597 .uart_offset = 8,
3603 .uart_offset = 8,
3607 .num_ports = 8,
3609 .uart_offset = 8,
3613 * Entries following this are board-specific.
3617 * Panacom - IOMEM
3641 /* I think this entry is broken - the first_offset looks wrong --rmk */
3646 .uart_offset = 8 << 2,
3659 .uart_offset = 8,
3684 .num_ports = 8,
3692 * EKF addition for i960 Boards form EKF with serial port.
3699 .uart_offset = 8 << 2,
3707 .uart_offset = 8,
3713 * Computone - uses IOMEM.
3733 .num_ports = 8,
3741 .num_ports = 8,
3747 * PA Semi PWRficient PA6T-1682M on-chip UART
3766 .num_ports = 8,
3786 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3811 .num_ports = 8,
3824 .num_ports = 8,
3841 .uart_offset = 8,
3846 .num_ports = 8,
3847 .uart_offset = 8,
3853 .uart_offset = 8,
3859 .uart_offset = 8,
3863 .num_ports = 8,
3864 .uart_offset = 8,
3869 .uart_offset = 8,
3876 .uart_offset = 8,
3883 .uart_offset = 8,
3888 .num_ports = 8,
3890 .uart_offset = 8,
3909 .num_ports = 8,
3941 .num_ports = 8,
3960 .num_ports = 8,
3975 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3976 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3978 /* multi-io cards handled by parport_serial */
4027 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && in serial_pci_is_class_communication()
4028 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) && in serial_pci_is_class_communication()
4029 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || in serial_pci_is_class_communication()
4030 (dev->class & 0xff) > 6) in serial_pci_is_class_communication()
4031 return -ENODEV; in serial_pci_is_class_communication()
4039 * serial specs. Returns 0 on success, -ENODEV on failure.
4044 int num_iomem, num_port, first_port = -1, i; in serial_pci_guess_board()
4054 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL) in serial_pci_guess_board()
4055 return -ENODEV; in serial_pci_guess_board()
4061 if (first_port == -1) in serial_pci_guess_board()
4069 * If there is 1 or 0 iomem regions, and exactly one port, in serial_pci_guess_board()
4074 board->flags = first_port; in serial_pci_guess_board()
4075 board->num_ports = pci_resource_len(dev, first_port) / 8; in serial_pci_guess_board()
4081 * Each IO BAR should be 8 bytes, and they should follow in serial_pci_guess_board()
4084 first_port = -1; in serial_pci_guess_board()
4088 pci_resource_len(dev, i) == 8 && in serial_pci_guess_board()
4089 (first_port == -1 || (first_port + num_port) == i)) { in serial_pci_guess_board()
4091 if (first_port == -1) in serial_pci_guess_board()
4097 board->flags = first_port | FL_BASE_BARS; in serial_pci_guess_board()
4098 board->num_ports = num_port; in serial_pci_guess_board()
4102 return -ENODEV; in serial_pci_guess_board()
4110 board->num_ports == guessed->num_ports && in serial_pci_matches()
4111 board->base_baud == guessed->base_baud && in serial_pci_matches()
4112 board->uart_offset == guessed->uart_offset && in serial_pci_matches()
4113 board->reg_shift == guessed->reg_shift && in serial_pci_matches()
4114 board->first_offset == guessed->first_offset; in serial_pci_matches()
4125 nr_ports = board->num_ports; in pciserial_init_ports()
4133 * Run the new-style initialization function. in pciserial_init_ports()
4135 * <0 - error in pciserial_init_ports()
4136 * 0 - use board->num_ports in pciserial_init_ports()
4137 * >0 - number of ports in pciserial_init_ports()
4139 if (quirk->init) { in pciserial_init_ports()
4140 rc = quirk->init(dev); in pciserial_init_ports()
4151 priv = ERR_PTR(-ENOMEM); in pciserial_init_ports()
4155 priv->dev = dev; in pciserial_init_ports()
4156 priv->quirk = quirk; in pciserial_init_ports()
4159 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; in pciserial_init_ports()
4160 uart.port.uartclk = board->base_baud * 16; in pciserial_init_ports()
4162 if (board->flags & FL_NOIRQ) { in pciserial_init_ports()
4163 uart.port.irq = 0; in pciserial_init_ports()
4166 pci_dbg(dev, "Using MSI(-X) interrupts\n"); in pciserial_init_ports()
4168 uart.port.flags &= ~UPF_SHARE_IRQ; in pciserial_init_ports()
4180 uart.port.irq = pci_irq_vector(dev, 0); in pciserial_init_ports()
4183 uart.port.dev = &dev->dev; in pciserial_init_ports()
4186 if (quirk->setup(priv, board, &uart, i)) in pciserial_init_ports()
4189 pci_dbg(dev, "Setup PCI port: port %lx, irq %d, type %d\n", in pciserial_init_ports()
4190 uart.port.iobase, uart.port.irq, uart.port.iotype); in pciserial_init_ports()
4192 priv->line[i] = serial8250_register_8250_port(&uart); in pciserial_init_ports()
4193 if (priv->line[i] < 0) { in pciserial_init_ports()
4195 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", in pciserial_init_ports()
4196 uart.port.iobase, uart.port.irq, in pciserial_init_ports()
4197 uart.port.iotype, priv->line[i]); in pciserial_init_ports()
4201 priv->nr = i; in pciserial_init_ports()
4202 priv->board = board; in pciserial_init_ports()
4206 if (quirk->exit) in pciserial_init_ports()
4207 quirk->exit(dev); in pciserial_init_ports()
4218 for (i = 0; i < priv->nr; i++) in pciserial_detach_ports()
4219 serial8250_unregister_port(priv->line[i]); in pciserial_detach_ports()
4224 quirk = find_quirk(priv->dev); in pciserial_detach_ports()
4225 if (quirk->exit) in pciserial_detach_ports()
4226 quirk->exit(priv->dev); in pciserial_detach_ports()
4240 for (i = 0; i < priv->nr; i++) in pciserial_suspend_ports()
4241 if (priv->line[i] >= 0) in pciserial_suspend_ports()
4242 serial8250_suspend_port(priv->line[i]); in pciserial_suspend_ports()
4247 if (priv->quirk->exit) in pciserial_suspend_ports()
4248 priv->quirk->exit(priv->dev); in pciserial_suspend_ports()
4259 if (priv->quirk->init) in pciserial_resume_ports()
4260 priv->quirk->init(priv->dev); in pciserial_resume_ports()
4262 for (i = 0; i < priv->nr; i++) in pciserial_resume_ports()
4263 if (priv->line[i] >= 0) in pciserial_resume_ports()
4264 serial8250_resume_port(priv->line[i]); in pciserial_resume_ports()
4283 if (quirk->probe) { in pciserial_init_one()
4284 rc = quirk->probe(dev); in pciserial_init_one()
4289 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { in pciserial_init_one()
4290 pci_err(dev, "invalid driver_data: %ld\n", ent->driver_data); in pciserial_init_one()
4291 return -EINVAL; in pciserial_init_one()
4294 board = &pci_boards[ent->driver_data]; in pciserial_init_one()
4298 if (exclude->driver_data) in pciserial_init_one()
4299 pci_warn(dev, "ignoring port, enable %s to handle\n", in pciserial_init_one()
4300 (const char *)exclude->driver_data); in pciserial_init_one()
4301 return -ENODEV; in pciserial_init_one()
4309 if (ent->driver_data == pbn_default) { in pciserial_init_one()
4372 * The device may have been disabled. Re-enable it. in pciserial_resume_one()
4377 pci_err(pdev, "Unable to re-enable ports, trying to continue.\n"); in pciserial_resume_one()
4514 /* Unknown card - subdevice 0x1584 */
4519 /* Unknown card - subdevice 0x1588 */
4728 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4731 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4815 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4818 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4821 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4824 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4829 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4843 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4860 * Digitan DS560-558, from [email protected]
5130 * Dell Remote Access Card 4 - [email protected]
5137 * Dell Remote Access Card III - [email protected]
5144 * RAStel 2 port modem, [email protected]
5151 * EKF addition for i960 Boards form EKF with serial port
5164 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
5226 * IntaShield IS-100
5232 * IntaShield IS-200
5238 * IntaShield IS-400
5244 * IntaShield IX-100
5251 * IntaShield IX-200
5258 * IntaShield IX-400
5266 * Brainboxes UC-101
5281 * Brainboxes UC-235/246
5292 * Brainboxes UC-253/UC-734
5299 * Brainboxes UC-260/271/701/756
5303 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5307 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5310 * Brainboxes UC-268
5317 * Brainboxes UC-275/279
5324 * Brainboxes UC-302
5339 * Brainboxes UC-310
5346 * Brainboxes UC-313
5361 * Brainboxes UC-320/324
5368 * Brainboxes UC-346
5379 * Brainboxes UC-357
5394 * Brainboxes UC-368
5409 * Brainboxes UC-420
5416 * Brainboxes UC-607
5431 * Brainboxes UC-836
5438 * Brainboxes UP-189
5453 * Brainboxes UP-200
5468 * Brainboxes UP-869
5483 * Brainboxes UP-880
5498 * Brainboxes PX-101
5509 * Brainboxes PX-235/246
5520 * Brainboxes PX-203/PX-257
5531 * Brainboxes PX-260/PX-701
5538 * Brainboxes PX-275/279
5545 * Brainboxes PX-310
5552 * Brainboxes PX-313
5559 * Brainboxes PX-320/324/PX-376/PX-387
5566 * Brainboxes PX-335/346
5573 * Brainboxes PX-368
5580 * Brainboxes PX-420
5591 * Brainboxes PX-475
5598 * Brainboxes PX-803/PX-857
5613 * Brainboxes PX-820
5624 * Brainboxes PX-835/PX-846
5635 * Brainboxes XC-235
5642 * Brainboxes XC-475
5650 * Perle PCI-RAS cards
5772 * PA Semi PA6T-1682M on-chip UART
5877 * ADDI-DATA GmbH communication cards <info@addi-data.com>
6077 * AgeStar as-prs2-009
6129 /* MKS Tenta SCOM-080x serial cards */
6142 PCI_CLASS_COMMUNICATION_SERIAL << 8,
6146 PCI_CLASS_COMMUNICATION_MODEM << 8,
6150 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
6194 new = pciserial_init_ports(dev, priv->board); in serial8250_io_resume()