Lines Matching +full:up +full:- +full:to
1 // SPDX-License-Identifier: GPL-2.0
3 * 8250-core based driver for the OMAP internal UART
5 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments.
28 #include <linux/dma-mapping.h>
41 * The same errata is applicable to AM335x and DRA7x processors too.
169 return readl(priv->membase + (reg << OMAP_UART_REGSHIFT)); in uart_read()
178 struct uart_8250_port *up = up_to_u8250p(port); in __omap8250_set_mctrl() local
179 struct omap8250_priv *priv = up->port.private_data; in __omap8250_set_mctrl()
184 if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) { in __omap8250_set_mctrl()
189 lcr = serial_in(up, UART_LCR); in __omap8250_set_mctrl()
190 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); in __omap8250_set_mctrl()
191 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) in __omap8250_set_mctrl()
192 priv->efr |= UART_EFR_RTS; in __omap8250_set_mctrl()
194 priv->efr &= ~UART_EFR_RTS; in __omap8250_set_mctrl()
195 serial_out(up, UART_EFR, priv->efr); in __omap8250_set_mctrl()
196 serial_out(up, UART_LCR, lcr); in __omap8250_set_mctrl()
204 err = pm_runtime_resume_and_get(port->dev); in omap8250_set_mctrl()
210 pm_runtime_mark_last_busy(port->dev); in omap8250_set_mctrl()
211 pm_runtime_put_autosuspend(port->dev); in omap8250_set_mctrl()
216 * The access to uart register after MDR1 Access
217 * causes UART to corrupt data.
223 static void omap_8250_mdr1_errataset(struct uart_8250_port *up, in omap_8250_mdr1_errataset() argument
226 serial_out(up, UART_OMAP_MDR1, priv->mdr1); in omap_8250_mdr1_errataset()
228 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | in omap_8250_mdr1_errataset()
235 unsigned int uartclk = port->uartclk; in omap_8250_get_divisor()
242 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { in omap_8250_get_divisor()
243 priv->quot = port->custom_divisor & UART_DIV_MAX; in omap_8250_get_divisor()
246 * would like to specify the divisor _and_ the mode then the in omap_8250_get_divisor()
249 if (port->custom_divisor & (1 << 16)) in omap_8250_get_divisor()
250 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; in omap_8250_get_divisor()
252 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; in omap_8250_get_divisor()
263 abs_d13 = abs(baud - uartclk / 13 / div_13); in omap_8250_get_divisor()
264 abs_d16 = abs(baud - uartclk / 16 / div_16); in omap_8250_get_divisor()
267 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; in omap_8250_get_divisor()
268 priv->quot = div_16; in omap_8250_get_divisor()
270 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; in omap_8250_get_divisor()
271 priv->quot = div_13; in omap_8250_get_divisor()
275 static void omap8250_update_scr(struct uart_8250_port *up, in omap8250_update_scr() argument
280 old_scr = serial_in(up, UART_OMAP_SCR); in omap8250_update_scr()
281 if (old_scr == priv->scr) in omap8250_update_scr()
285 * The manual recommends not to enable the DMA mode selector in the SCR in omap8250_update_scr()
287 * register write because this may lead to malfunction. in omap8250_update_scr()
289 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK) in omap8250_update_scr()
290 serial_out(up, UART_OMAP_SCR, in omap8250_update_scr()
291 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK); in omap8250_update_scr()
292 serial_out(up, UART_OMAP_SCR, priv->scr); in omap8250_update_scr()
295 static void omap8250_update_mdr1(struct uart_8250_port *up, in omap8250_update_mdr1() argument
298 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS) in omap8250_update_mdr1()
299 omap_8250_mdr1_errataset(up, priv); in omap8250_update_mdr1()
301 serial_out(up, UART_OMAP_MDR1, priv->mdr1); in omap8250_update_mdr1()
304 static void omap8250_restore_regs(struct uart_8250_port *up) in omap8250_restore_regs() argument
306 struct omap8250_priv *priv = up->port.private_data; in omap8250_restore_regs()
307 struct uart_8250_dma *dma = up->dma; in omap8250_restore_regs()
308 u8 mcr = serial8250_in_MCR(up); in omap8250_restore_regs()
310 /* Port locked to synchronize UART_IER access against the console. */ in omap8250_restore_regs()
311 lockdep_assert_held_once(&up->port.lock); in omap8250_restore_regs()
313 if (dma && dma->tx_running) { in omap8250_restore_regs()
315 * TCSANOW requests the change to occur immediately however if in omap8250_restore_regs()
316 * we have a TX-DMA operation in progress then it has been in omap8250_restore_regs()
318 * delay DMA completes to prevent this hang from happen. in omap8250_restore_regs()
320 priv->delayed_restore = 1; in omap8250_restore_regs()
324 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); in omap8250_restore_regs()
325 serial_out(up, UART_EFR, UART_EFR_ECB); in omap8250_restore_regs()
327 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); in omap8250_restore_regs()
328 serial8250_out_MCR(up, mcr | UART_MCR_TCRTLR); in omap8250_restore_regs()
329 serial_out(up, UART_FCR, up->fcr); in omap8250_restore_regs()
331 omap8250_update_scr(up, priv); in omap8250_restore_regs()
333 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); in omap8250_restore_regs()
335 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) | in omap8250_restore_regs()
337 serial_out(up, UART_TI752_TLR, in omap8250_restore_regs()
338 TRIGGER_TLR_MASK(priv->tx_trigger) << UART_TI752_TLR_TX | in omap8250_restore_regs()
339 TRIGGER_TLR_MASK(priv->rx_trigger) << UART_TI752_TLR_RX); in omap8250_restore_regs()
341 serial_out(up, UART_LCR, 0); in omap8250_restore_regs()
344 serial8250_out_MCR(up, mcr); in omap8250_restore_regs()
346 serial_out(up, UART_IER, up->ier); in omap8250_restore_regs()
348 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); in omap8250_restore_regs()
349 serial_dl_write(up, priv->quot); in omap8250_restore_regs()
351 serial_out(up, UART_EFR, priv->efr); in omap8250_restore_regs()
354 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); in omap8250_restore_regs()
355 serial_out(up, UART_XON1, priv->xon); in omap8250_restore_regs()
356 serial_out(up, UART_XOFF1, priv->xoff); in omap8250_restore_regs()
358 serial_out(up, UART_LCR, up->lcr); in omap8250_restore_regs()
360 omap8250_update_mdr1(up, priv); in omap8250_restore_regs()
362 __omap8250_set_mctrl(&up->port, up->port.mctrl); in omap8250_restore_regs()
364 serial_out(up, UART_OMAP_MDR3, priv->mdr3); in omap8250_restore_regs()
366 if (up->port.rs485.flags & SER_RS485_ENABLED && in omap8250_restore_regs()
367 up->port.rs485_config == serial8250_em485_config) in omap8250_restore_regs()
368 serial8250_em485_stop_tx(up, true); in omap8250_restore_regs()
373 * some differences in how we want to handle flow control.
379 struct uart_8250_port *up = up_to_u8250p(port); in omap_8250_set_termios() local
380 struct omap8250_priv *priv = up->port.private_data; in omap_8250_set_termios()
384 cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag)); in omap_8250_set_termios()
386 if (termios->c_cflag & CSTOPB) in omap_8250_set_termios()
388 if (termios->c_cflag & PARENB) in omap_8250_set_termios()
390 if (!(termios->c_cflag & PARODD)) in omap_8250_set_termios()
392 if (termios->c_cflag & CMSPAR) in omap_8250_set_termios()
396 * Ask the core to calculate the divisor for us. in omap_8250_set_termios()
399 port->uartclk / 16 / UART_DIV_MAX, in omap_8250_set_termios()
400 port->uartclk / 13); in omap_8250_set_termios()
407 pm_runtime_get_sync(port->dev); in omap_8250_set_termios()
411 * Update the per-port timeout. in omap_8250_set_termios()
413 uart_update_timeout(port, termios->c_cflag, baud); in omap_8250_set_termios()
421 up->port.read_status_mask = UART_LSR_OE | UART_LSR_DR; in omap_8250_set_termios()
422 if (termios->c_iflag & INPCK) in omap_8250_set_termios()
423 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; in omap_8250_set_termios()
424 if (termios->c_iflag & (IGNBRK | PARMRK)) in omap_8250_set_termios()
425 up->port.read_status_mask |= UART_LSR_BI; in omap_8250_set_termios()
428 * Characters to ignore in omap_8250_set_termios()
430 up->port.ignore_status_mask = 0; in omap_8250_set_termios()
431 if (termios->c_iflag & IGNPAR) in omap_8250_set_termios()
432 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; in omap_8250_set_termios()
433 if (termios->c_iflag & IGNBRK) { in omap_8250_set_termios()
434 up->port.ignore_status_mask |= UART_LSR_BI; in omap_8250_set_termios()
439 if (termios->c_iflag & IGNPAR) in omap_8250_set_termios()
440 up->port.ignore_status_mask |= UART_LSR_OE; in omap_8250_set_termios()
446 if ((termios->c_cflag & CREAD) == 0) in omap_8250_set_termios()
447 up->port.ignore_status_mask |= UART_LSR_DR; in omap_8250_set_termios()
452 up->ier &= ~UART_IER_MSI; in omap_8250_set_termios()
453 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) in omap_8250_set_termios()
454 up->ier |= UART_IER_MSI; in omap_8250_set_termios()
456 up->lcr = cval; in omap_8250_set_termios()
457 /* Up to here it was mostly serial8250_do_set_termios() */ in omap_8250_set_termios()
462 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt. in omap_8250_set_termios()
463 * - less than RX_TRIGGER number of bytes will also cause an interrupt in omap_8250_set_termios()
465 * - Once THRE is enabled, the interrupt will be fired once the FIFO is in omap_8250_set_termios()
466 * empty - the trigger level is ignored here. in omap_8250_set_termios()
469 * - UART will assert the TX DMA line once there is room for TX_TRIGGER in omap_8250_set_termios()
472 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in in omap_8250_set_termios()
476 up->fcr = UART_FCR_ENABLE_FIFO; in omap_8250_set_termios()
477 up->fcr |= TRIGGER_FCR_MASK(priv->tx_trigger) << OMAP_UART_FCR_TX_TRIG; in omap_8250_set_termios()
478 up->fcr |= TRIGGER_FCR_MASK(priv->rx_trigger) << OMAP_UART_FCR_RX_TRIG; in omap_8250_set_termios()
480 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY | in omap_8250_set_termios()
483 if (up->dma) in omap_8250_set_termios()
484 priv->scr |= OMAP_UART_SCR_DMAMODE_1 | in omap_8250_set_termios()
487 priv->xon = termios->c_cc[VSTART]; in omap_8250_set_termios()
488 priv->xoff = termios->c_cc[VSTOP]; in omap_8250_set_termios()
490 priv->efr = 0; in omap_8250_set_termios()
491 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); in omap_8250_set_termios()
493 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW && in omap_8250_set_termios()
494 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) && in omap_8250_set_termios()
495 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) { in omap_8250_set_termios()
497 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; in omap_8250_set_termios()
498 priv->efr |= UART_EFR_CTS; in omap_8250_set_termios()
499 } else if (up->port.flags & UPF_SOFT_FLOW) { in omap_8250_set_termios()
510 if (termios->c_iflag & IXOFF) { in omap_8250_set_termios()
511 up->port.status |= UPSTAT_AUTOXOFF; in omap_8250_set_termios()
512 priv->efr |= OMAP_UART_SW_TX; in omap_8250_set_termios()
515 omap8250_restore_regs(up); in omap_8250_set_termios()
517 uart_port_unlock_irq(&up->port); in omap_8250_set_termios()
518 pm_runtime_mark_last_busy(port->dev); in omap_8250_set_termios()
519 pm_runtime_put_autosuspend(port->dev); in omap_8250_set_termios()
522 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud; in omap_8250_set_termios()
523 priv->latency = priv->calc_latency; in omap_8250_set_termios()
525 schedule_work(&priv->qos_work); in omap_8250_set_termios()
536 struct uart_8250_port *up = up_to_u8250p(port); in omap_8250_pm() local
539 pm_runtime_get_sync(port->dev); in omap_8250_pm()
544 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); in omap_8250_pm()
545 efr = serial_in(up, UART_EFR); in omap_8250_pm()
546 serial_out(up, UART_EFR, efr | UART_EFR_ECB); in omap_8250_pm()
547 serial_out(up, UART_LCR, 0); in omap_8250_pm()
549 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); in omap_8250_pm()
550 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); in omap_8250_pm()
551 serial_out(up, UART_EFR, efr); in omap_8250_pm()
552 serial_out(up, UART_LCR, 0); in omap_8250_pm()
556 pm_runtime_mark_last_busy(port->dev); in omap_8250_pm()
557 pm_runtime_put_autosuspend(port->dev); in omap_8250_pm()
560 static void omap_serial_fill_features_erratas(struct uart_8250_port *up, in omap_serial_fill_features_erratas() argument
591 dev_warn(up->port.dev, in omap_serial_fill_features_erratas()
592 "Unknown revision, defaulting to highest\n"); in omap_serial_fill_features_erratas()
602 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS; in omap_serial_fill_features_erratas()
605 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | in omap_serial_fill_features_erratas()
609 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | in omap_serial_fill_features_erratas()
618 * don't have RHR_IT_DIS bit in IER2 register. So drop to flag in omap_serial_fill_features_erratas()
619 * to enable errata workaround. in omap_serial_fill_features_erratas()
622 priv->habit &= ~UART_HAS_RHR_IT_DIS; in omap_serial_fill_features_erratas()
630 cpu_latency_qos_update_request(&priv->pm_qos_request, priv->latency); in omap8250_uart_qos_work()
640 struct uart_8250_port *up = serial8250_get_port(priv->line); in omap8250_irq() local
641 struct uart_port *port = &up->port; in omap8250_irq()
645 pm_runtime_get_noresume(port->dev); in omap8250_irq()
647 /* Shallow idle state wake-up to an IO interrupt? */ in omap8250_irq()
648 if (atomic_add_unless(&priv->active, 1, 1)) { in omap8250_irq()
649 priv->latency = priv->calc_latency; in omap8250_irq()
650 schedule_work(&priv->qos_work); in omap8250_irq()
654 if (up->dma) { in omap8250_irq()
656 pm_runtime_mark_last_busy(port->dev); in omap8250_irq()
657 pm_runtime_put(port->dev); in omap8250_irq()
672 if (priv->habit & UART_RX_TIMEOUT_QUIRK && in omap8250_irq()
677 efr2 = serial_in(up, UART_OMAP_EFR2); in omap8250_irq()
678 timeout_h = serial_in(up, UART_OMAP_TO_H); in omap8250_irq()
679 timeout_l = serial_in(up, UART_OMAP_TO_L); in omap8250_irq()
680 serial_out(up, UART_OMAP_TO_H, 0xFF); in omap8250_irq()
681 serial_out(up, UART_OMAP_TO_L, 0xFF); in omap8250_irq()
682 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE); in omap8250_irq()
683 serial_in(up, UART_IIR); in omap8250_irq()
684 serial_out(up, UART_OMAP_EFR2, efr2); in omap8250_irq()
685 serial_out(up, UART_OMAP_TO_H, timeout_h); in omap8250_irq()
686 serial_out(up, UART_OMAP_TO_L, timeout_l); in omap8250_irq()
690 if ((lsr & UART_LSR_OE) && up->overrun_backoff_time_ms > 0) { in omap8250_irq()
695 up->ier = port->serial_in(port, UART_IER); in omap8250_irq()
696 if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) { in omap8250_irq()
697 port->ops->stop_rx(port); in omap8250_irq()
702 cancel_delayed_work(&up->overrun_backoff); in omap8250_irq()
706 delay = msecs_to_jiffies(up->overrun_backoff_time_ms); in omap8250_irq()
707 schedule_delayed_work(&up->overrun_backoff, delay); in omap8250_irq()
710 pm_runtime_mark_last_busy(port->dev); in omap8250_irq()
711 pm_runtime_put(port->dev); in omap8250_irq()
718 struct uart_8250_port *up = up_to_u8250p(port); in omap_8250_startup() local
719 struct omap8250_priv *priv = port->private_data; in omap_8250_startup()
720 struct uart_8250_dma *dma = &priv->omap8250_dma; in omap_8250_startup()
723 if (priv->wakeirq) { in omap_8250_startup()
724 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq); in omap_8250_startup()
729 pm_runtime_get_sync(port->dev); in omap_8250_startup()
731 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); in omap_8250_startup()
733 serial_out(up, UART_LCR, UART_LCR_WLEN8); in omap_8250_startup()
735 up->lsr_saved_flags = 0; in omap_8250_startup()
736 up->msr_saved_flags = 0; in omap_8250_startup()
739 if (dma->fn && !uart_console(port)) { in omap_8250_startup()
740 up->dma = &priv->omap8250_dma; in omap_8250_startup()
741 ret = serial8250_request_dma(up); in omap_8250_startup()
743 dev_warn_ratelimited(port->dev, in omap_8250_startup()
744 "failed to request DMA\n"); in omap_8250_startup()
745 up->dma = NULL; in omap_8250_startup()
748 up->dma = NULL; in omap_8250_startup()
753 up->ier = UART_IER_RLSI | UART_IER_RDI; in omap_8250_startup()
754 serial_out(up, UART_IER, up->ier); in omap_8250_startup()
758 up->capabilities |= UART_CAP_RPM; in omap_8250_startup()
761 /* Enable module level wake up */ in omap_8250_startup()
762 priv->wer = OMAP_UART_WER_MOD_WKUP; in omap_8250_startup()
763 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP) in omap_8250_startup()
764 priv->wer |= OMAP_UART_TX_WAKEUP_EN; in omap_8250_startup()
765 serial_out(up, UART_OMAP_WER, priv->wer); in omap_8250_startup()
767 if (up->dma && !(priv->habit & UART_HAS_EFR2)) { in omap_8250_startup()
769 up->dma->rx_dma(up); in omap_8250_startup()
773 enable_irq(up->port.irq); in omap_8250_startup()
775 pm_runtime_mark_last_busy(port->dev); in omap_8250_startup()
776 pm_runtime_put_autosuspend(port->dev); in omap_8250_startup()
782 struct uart_8250_port *up = up_to_u8250p(port); in omap_8250_shutdown() local
783 struct omap8250_priv *priv = port->private_data; in omap_8250_shutdown()
785 pm_runtime_get_sync(port->dev); in omap_8250_shutdown()
787 flush_work(&priv->qos_work); in omap_8250_shutdown()
788 if (up->dma) in omap_8250_shutdown()
789 omap_8250_rx_dma_flush(up); in omap_8250_shutdown()
791 serial_out(up, UART_OMAP_WER, 0); in omap_8250_shutdown()
792 if (priv->habit & UART_HAS_EFR2) in omap_8250_shutdown()
793 serial_out(up, UART_OMAP_EFR2, 0x0); in omap_8250_shutdown()
797 up->ier = 0; in omap_8250_shutdown()
798 serial_out(up, UART_IER, 0); in omap_8250_shutdown()
800 disable_irq_nosync(up->port.irq); in omap_8250_shutdown()
801 dev_pm_clear_wake_irq(port->dev); in omap_8250_shutdown()
803 serial8250_release_dma(up); in omap_8250_shutdown()
804 up->dma = NULL; in omap_8250_shutdown()
809 if (up->lcr & UART_LCR_SBC) in omap_8250_shutdown()
810 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC); in omap_8250_shutdown()
811 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); in omap_8250_shutdown()
813 pm_runtime_mark_last_busy(port->dev); in omap_8250_shutdown()
814 pm_runtime_put_autosuspend(port->dev); in omap_8250_shutdown()
819 struct omap8250_priv *priv = port->private_data; in omap_8250_throttle()
822 pm_runtime_get_sync(port->dev); in omap_8250_throttle()
825 port->ops->stop_rx(port); in omap_8250_throttle()
826 priv->throttled = true; in omap_8250_throttle()
829 pm_runtime_mark_last_busy(port->dev); in omap_8250_throttle()
830 pm_runtime_put_autosuspend(port->dev); in omap_8250_throttle()
835 struct omap8250_priv *priv = port->private_data; in omap_8250_unthrottle()
836 struct uart_8250_port *up = up_to_u8250p(port); in omap_8250_unthrottle() local
839 pm_runtime_get_sync(port->dev); in omap_8250_unthrottle()
843 priv->throttled = false; in omap_8250_unthrottle()
844 if (up->dma) in omap_8250_unthrottle()
845 up->dma->rx_dma(up); in omap_8250_unthrottle()
846 up->ier |= UART_IER_RLSI | UART_IER_RDI; in omap_8250_unthrottle()
847 serial_out(up, UART_IER, up->ier); in omap_8250_unthrottle()
850 pm_runtime_mark_last_busy(port->dev); in omap_8250_unthrottle()
851 pm_runtime_put_autosuspend(port->dev); in omap_8250_unthrottle()
858 struct omap8250_priv *priv = port->private_data; in omap8250_rs485_config()
859 struct uart_8250_port *up = up_to_u8250p(port); in omap8250_rs485_config() local
866 * register is going empty to allow time for the stop bit to transition in omap8250_rs485_config()
867 * through the transceiver before direction is changed to receive. in omap8250_rs485_config()
869 * Additionally there appears to be a 1 bit clock delay between writing in omap8250_rs485_config()
870 * to the THR register and transmission of the start bit, per page 8783 in omap8250_rs485_config()
873 if (priv->quot) { in omap8250_rs485_config()
874 if (priv->mdr1 == UART_OMAP_MDR1_16X_MODE) in omap8250_rs485_config()
875 baud = port->uartclk / (16 * priv->quot); in omap8250_rs485_config()
877 baud = port->uartclk / (13 * priv->quot); in omap8250_rs485_config()
884 * Fall back to RS485 software emulation if the UART is missing in omap8250_rs485_config()
886 * (indicates that RTS is unavailable due to a pinmux conflict) in omap8250_rs485_config()
889 if (!(priv->habit & UART_HAS_NATIVE_RS485) || in omap8250_rs485_config()
890 mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) || in omap8250_rs485_config()
891 rs485->delay_rts_after_send > fixed_delay_rts_after_send || in omap8250_rs485_config()
892 rs485->delay_rts_before_send > fixed_delay_rts_before_send) { in omap8250_rs485_config()
893 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN; in omap8250_rs485_config()
894 serial_out(up, UART_OMAP_MDR3, priv->mdr3); in omap8250_rs485_config()
896 port->rs485_config = serial8250_em485_config; in omap8250_rs485_config()
900 rs485->delay_rts_after_send = fixed_delay_rts_after_send; in omap8250_rs485_config()
901 rs485->delay_rts_before_send = fixed_delay_rts_before_send; in omap8250_rs485_config()
903 if (rs485->flags & SER_RS485_ENABLED) in omap8250_rs485_config()
904 priv->mdr3 |= UART_OMAP_MDR3_DIR_EN; in omap8250_rs485_config()
906 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN; in omap8250_rs485_config()
912 if (rs485->flags & SER_RS485_RTS_ON_SEND) in omap8250_rs485_config()
913 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_POL; in omap8250_rs485_config()
915 priv->mdr3 |= UART_OMAP_MDR3_DIR_POL; in omap8250_rs485_config()
917 serial_out(up, UART_OMAP_MDR3, priv->mdr3); in omap8250_rs485_config()
925 /* Must be called while priv->rx_dma_lock is held */
928 struct uart_8250_dma *dma = p->dma; in __dma_rx_do_complete()
929 struct tty_port *tty_port = &p->port.state->port; in __dma_rx_do_complete()
930 struct omap8250_priv *priv = p->port.private_data; in __dma_rx_do_complete()
931 struct dma_chan *rxchan = dma->rxchan; in __dma_rx_do_complete()
938 if (!dma->rx_running) in __dma_rx_do_complete()
941 cookie = dma->rx_cookie; in __dma_rx_do_complete()
942 dma->rx_running = 0; in __dma_rx_do_complete()
944 /* Re-enable RX FIFO interrupt now that transfer is complete */ in __dma_rx_do_complete()
945 if (priv->habit & UART_HAS_RHR_IT_DIS) { in __dma_rx_do_complete()
953 count = dma->rx_size - state.residue + state.in_flight_bytes; in __dma_rx_do_complete()
954 if (count < dma->rx_size) { in __dma_rx_do_complete()
958 * Poll for teardown to complete which guarantees in in __dma_rx_do_complete()
965 poll_count--) in __dma_rx_do_complete()
968 if (poll_count == -1) in __dma_rx_do_complete()
969 dev_err(p->port.dev, "teardown incomplete\n"); in __dma_rx_do_complete()
974 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count); in __dma_rx_do_complete()
976 p->port.icount.rx += ret; in __dma_rx_do_complete()
977 p->port.icount.buf_overrun += count - ret; in __dma_rx_do_complete()
986 struct omap8250_priv *priv = p->port.private_data; in __dma_rx_complete()
987 struct uart_8250_dma *dma = p->dma; in __dma_rx_complete()
992 uart_port_lock_irqsave(&p->port, &flags); in __dma_rx_complete()
999 if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) != in __dma_rx_complete()
1001 uart_port_unlock_irqrestore(&p->port, flags); in __dma_rx_complete()
1005 if (!priv->throttled) { in __dma_rx_complete()
1006 p->ier |= UART_IER_RLSI | UART_IER_RDI; in __dma_rx_complete()
1007 serial_out(p, UART_IER, p->ier); in __dma_rx_complete()
1008 if (!(priv->habit & UART_HAS_EFR2)) in __dma_rx_complete()
1012 uart_port_unlock_irqrestore(&p->port, flags); in __dma_rx_complete()
1017 struct omap8250_priv *priv = p->port.private_data; in omap_8250_rx_dma_flush()
1018 struct uart_8250_dma *dma = p->dma; in omap_8250_rx_dma_flush()
1023 spin_lock_irqsave(&priv->rx_dma_lock, flags); in omap_8250_rx_dma_flush()
1025 if (!dma->rx_running) { in omap_8250_rx_dma_flush()
1026 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); in omap_8250_rx_dma_flush()
1030 ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); in omap_8250_rx_dma_flush()
1032 ret = dmaengine_pause(dma->rxchan); in omap_8250_rx_dma_flush()
1034 priv->rx_dma_broken = true; in omap_8250_rx_dma_flush()
1037 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); in omap_8250_rx_dma_flush()
1042 struct omap8250_priv *priv = p->port.private_data; in omap_8250_rx_dma()
1043 struct uart_8250_dma *dma = p->dma; in omap_8250_rx_dma()
1049 /* Port locked to synchronize UART_IER access against the console. */ in omap_8250_rx_dma()
1050 lockdep_assert_held_once(&p->port.lock); in omap_8250_rx_dma()
1052 if (priv->rx_dma_broken) in omap_8250_rx_dma()
1053 return -EINVAL; in omap_8250_rx_dma()
1055 spin_lock_irqsave(&priv->rx_dma_lock, flags); in omap_8250_rx_dma()
1057 if (dma->rx_running) { in omap_8250_rx_dma()
1060 state = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, NULL); in omap_8250_rx_dma()
1063 * Disable RX interrupts to allow RX DMA completion in omap_8250_rx_dma()
1064 * callback to run. in omap_8250_rx_dma()
1066 p->ier &= ~(UART_IER_RLSI | UART_IER_RDI); in omap_8250_rx_dma()
1067 serial_out(p, UART_IER, p->ier); in omap_8250_rx_dma()
1072 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr, in omap_8250_rx_dma()
1073 dma->rx_size, DMA_DEV_TO_MEM, in omap_8250_rx_dma()
1076 err = -EBUSY; in omap_8250_rx_dma()
1080 dma->rx_running = 1; in omap_8250_rx_dma()
1081 desc->callback = __dma_rx_complete; in omap_8250_rx_dma()
1082 desc->callback_param = p; in omap_8250_rx_dma()
1084 dma->rx_cookie = dmaengine_submit(desc); in omap_8250_rx_dma()
1089 * but is yet to be drained by DMA. in omap_8250_rx_dma()
1091 if (priv->habit & UART_HAS_RHR_IT_DIS) { in omap_8250_rx_dma()
1097 dma_async_issue_pending(dma->rxchan); in omap_8250_rx_dma()
1099 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); in omap_8250_rx_dma()
1108 struct uart_8250_dma *dma = p->dma; in omap_8250_dma_tx_complete()
1109 struct tty_port *tport = &p->port.state->port; in omap_8250_dma_tx_complete()
1112 struct omap8250_priv *priv = p->port.private_data; in omap_8250_dma_tx_complete()
1114 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr, in omap_8250_dma_tx_complete()
1117 uart_port_lock_irqsave(&p->port, &flags); in omap_8250_dma_tx_complete()
1119 dma->tx_running = 0; in omap_8250_dma_tx_complete()
1121 uart_xmit_advance(&p->port, dma->tx_size); in omap_8250_dma_tx_complete()
1123 if (priv->delayed_restore) { in omap_8250_dma_tx_complete()
1124 priv->delayed_restore = 0; in omap_8250_dma_tx_complete()
1128 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in omap_8250_dma_tx_complete()
1129 uart_write_wakeup(&p->port); in omap_8250_dma_tx_complete()
1131 if (!kfifo_is_empty(&tport->xmit_fifo) && !uart_tx_stopped(&p->port)) { in omap_8250_dma_tx_complete()
1137 } else if (p->capabilities & UART_CAP_RPM) { in omap_8250_dma_tx_complete()
1142 dma->tx_err = 1; in omap_8250_dma_tx_complete()
1146 uart_port_unlock_irqrestore(&p->port, flags); in omap_8250_dma_tx_complete()
1151 struct uart_8250_dma *dma = p->dma; in omap_8250_tx_dma()
1152 struct omap8250_priv *priv = p->port.private_data; in omap_8250_tx_dma()
1153 struct tty_port *tport = &p->port.state->port; in omap_8250_tx_dma()
1156 int skip_byte = -1; in omap_8250_tx_dma()
1159 if (dma->tx_running) in omap_8250_tx_dma()
1161 if (uart_tx_stopped(&p->port) || kfifo_is_empty(&tport->xmit_fifo)) { in omap_8250_tx_dma()
1164 * Even if no data, we need to return an error for the two cases in omap_8250_tx_dma()
1168 if (dma->tx_err || p->capabilities & UART_CAP_RPM) { in omap_8250_tx_dma()
1169 ret = -EBUSY; in omap_8250_tx_dma()
1177 ret = kfifo_dma_out_prepare_mapped(&tport->xmit_fifo, &sg, 1, in omap_8250_tx_dma()
1178 UART_XMIT_SIZE, dma->tx_addr); in omap_8250_tx_dma()
1184 dma->tx_size = sg_dma_len(&sg); in omap_8250_tx_dma()
1186 if (priv->habit & OMAP_DMA_TX_KICK) { in omap_8250_tx_dma()
1191 * We need to put the first byte into the FIFO in order to start in omap_8250_tx_dma()
1196 * leaving the FIFO seem not to trigger the DMA transfer. It is in omap_8250_tx_dma()
1200 * just completed its work. We don't have to wait the complete in omap_8250_tx_dma()
1201 * 86us at 115200,8n1 but around 60us (not to mention lower in omap_8250_tx_dma()
1206 if (tx_lvl == p->tx_loadsz) { in omap_8250_tx_dma()
1207 ret = -EBUSY; in omap_8250_tx_dma()
1210 if (dma->tx_size < 4) { in omap_8250_tx_dma()
1211 ret = -EINVAL; in omap_8250_tx_dma()
1214 if (!kfifo_get(&tport->xmit_fifo, &c)) { in omap_8250_tx_dma()
1215 ret = -EINVAL; in omap_8250_tx_dma()
1219 /* now we need to recompute due to kfifo_get */ in omap_8250_tx_dma()
1220 kfifo_dma_out_prepare_mapped(&tport->xmit_fifo, &sg, 1, in omap_8250_tx_dma()
1221 UART_XMIT_SIZE, dma->tx_addr); in omap_8250_tx_dma()
1224 desc = dmaengine_prep_slave_sg(dma->txchan, &sg, 1, DMA_MEM_TO_DEV, in omap_8250_tx_dma()
1227 ret = -EBUSY; in omap_8250_tx_dma()
1231 dma->tx_running = 1; in omap_8250_tx_dma()
1233 desc->callback = omap_8250_dma_tx_complete; in omap_8250_tx_dma()
1234 desc->callback_param = p; in omap_8250_tx_dma()
1236 dma->tx_cookie = dmaengine_submit(desc); in omap_8250_tx_dma()
1238 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr, in omap_8250_tx_dma()
1241 dma_async_issue_pending(dma->txchan); in omap_8250_tx_dma()
1242 if (dma->tx_err) in omap_8250_tx_dma()
1243 dma->tx_err = 0; in omap_8250_tx_dma()
1249 dma->tx_err = 1; in omap_8250_tx_dma()
1256 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir) in handle_rx_dma() argument
1262 omap_8250_rx_dma_flush(up); in handle_rx_dma()
1265 return omap_8250_rx_dma(up); in handle_rx_dma()
1268 static u16 omap_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, u16 status) in omap_8250_handle_rx_dma() argument
1272 if (handle_rx_dma(up, iir)) { in omap_8250_handle_rx_dma()
1273 status = serial8250_rx_chars(up, status); in omap_8250_handle_rx_dma()
1274 omap_8250_rx_dma(up); in omap_8250_handle_rx_dma()
1281 static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, in am654_8250_handle_rx_dma() argument
1284 /* Port locked to synchronize UART_IER access against the console. */ in am654_8250_handle_rx_dma()
1285 lockdep_assert_held_once(&up->port.lock); in am654_8250_handle_rx_dma()
1291 (up->ier & UART_IER_RDI)) { in am654_8250_handle_rx_dma()
1292 omap_8250_rx_dma(up); in am654_8250_handle_rx_dma()
1293 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE); in am654_8250_handle_rx_dma()
1296 * Disable RX timeout, read IIR to clear in am654_8250_handle_rx_dma()
1297 * current timeout condition, clear EFR2 to in am654_8250_handle_rx_dma()
1298 * periodic timeouts, re-enable interrupts. in am654_8250_handle_rx_dma()
1300 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); in am654_8250_handle_rx_dma()
1301 serial_out(up, UART_IER, up->ier); in am654_8250_handle_rx_dma()
1302 omap_8250_rx_dma_flush(up); in am654_8250_handle_rx_dma()
1303 serial_in(up, UART_IIR); in am654_8250_handle_rx_dma()
1304 serial_out(up, UART_OMAP_EFR2, 0x0); in am654_8250_handle_rx_dma()
1305 up->ier |= UART_IER_RLSI | UART_IER_RDI; in am654_8250_handle_rx_dma()
1306 serial_out(up, UART_IER, up->ier); in am654_8250_handle_rx_dma()
1313 * use the default routine in the non-DMA case and this one for with DMA.
1317 struct uart_8250_port *up = up_to_u8250p(port); in omap_8250_dma_handle_irq() local
1318 struct omap8250_priv *priv = up->port.private_data; in omap_8250_dma_handle_irq()
1332 if (priv->habit & UART_HAS_EFR2) in omap_8250_dma_handle_irq()
1333 am654_8250_handle_rx_dma(up, iir, status); in omap_8250_dma_handle_irq()
1335 status = omap_8250_handle_rx_dma(up, iir, status); in omap_8250_dma_handle_irq()
1338 serial8250_modem_status(up); in omap_8250_dma_handle_irq()
1339 if (status & UART_LSR_THRE && up->dma->tx_err) { in omap_8250_dma_handle_irq()
1340 if (uart_tx_stopped(&up->port) || in omap_8250_dma_handle_irq()
1341 kfifo_is_empty(&up->port.state->port.xmit_fifo)) { in omap_8250_dma_handle_irq()
1342 up->dma->tx_err = 0; in omap_8250_dma_handle_irq()
1343 serial8250_tx_chars(up); in omap_8250_dma_handle_irq()
1346 * try again due to an earlier failure which in omap_8250_dma_handle_irq()
1349 if (omap_8250_tx_dma(up)) in omap_8250_dma_handle_irq()
1350 serial8250_tx_chars(up); in omap_8250_dma_handle_irq()
1368 return -EINVAL; in omap_8250_rx_dma()
1408 { .compatible = "ti,am654-uart", .data = &am654_platdata, },
1409 { .compatible = "ti,omap2-uart" },
1410 { .compatible = "ti,omap3-uart" },
1411 { .compatible = "ti,omap4-uart", .data = &omap4_platdata, },
1412 { .compatible = "ti,am3352-uart", .data = &am33xx_platdata, },
1413 { .compatible = "ti,am4372-uart", .data = &am33xx_platdata, },
1414 { .compatible = "ti,dra742-uart", .data = &omap4_platdata, },
1421 struct device_node *np = pdev->dev.of_node; in omap8250_probe()
1424 struct uart_8250_port up; in omap8250_probe() local
1431 dev_err(&pdev->dev, "missing registers\n"); in omap8250_probe()
1432 return -EINVAL; in omap8250_probe()
1435 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); in omap8250_probe()
1437 return -ENOMEM; in omap8250_probe()
1439 membase = devm_ioremap(&pdev->dev, regs->start, in omap8250_probe()
1442 return -ENODEV; in omap8250_probe()
1444 memset(&up, 0, sizeof(up)); in omap8250_probe()
1445 up.port.dev = &pdev->dev; in omap8250_probe()
1446 up.port.mapbase = regs->start; in omap8250_probe()
1447 up.port.membase = membase; in omap8250_probe()
1449 * It claims to be 16C750 compatible however it is a little different. in omap8250_probe()
1450 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to in omap8250_probe()
1452 * just to get things going. UNKNOWN does not work for a few reasons and in omap8250_probe()
1456 up.port.type = PORT_8250; in omap8250_probe()
1457 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW | UPF_HARD_FLOW; in omap8250_probe()
1458 up.port.private_data = priv; in omap8250_probe()
1460 up.tx_loadsz = 64; in omap8250_probe()
1461 up.capabilities = UART_CAP_FIFO; in omap8250_probe()
1464 * Runtime PM is mostly transparent. However to do it right we need to a in omap8250_probe()
1465 * TX empty interrupt before we can put the device to auto idle. So if in omap8250_probe()
1469 up.capabilities |= UART_CAP_RPM; in omap8250_probe()
1471 up.port.set_termios = omap_8250_set_termios; in omap8250_probe()
1472 up.port.set_mctrl = omap8250_set_mctrl; in omap8250_probe()
1473 up.port.pm = omap_8250_pm; in omap8250_probe()
1474 up.port.startup = omap_8250_startup; in omap8250_probe()
1475 up.port.shutdown = omap_8250_shutdown; in omap8250_probe()
1476 up.port.throttle = omap_8250_throttle; in omap8250_probe()
1477 up.port.unthrottle = omap_8250_unthrottle; in omap8250_probe()
1478 up.port.rs485_config = omap8250_rs485_config; in omap8250_probe()
1480 up.port.rs485_supported = serial8250_em485_supported; in omap8250_probe()
1481 up.rs485_start_tx = serial8250_em485_start_tx; in omap8250_probe()
1482 up.rs485_stop_tx = serial8250_em485_stop_tx; in omap8250_probe()
1483 up.port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE); in omap8250_probe()
1485 ret = uart_read_port_properties(&up.port); in omap8250_probe()
1489 up.port.regshift = OMAP_UART_REGSHIFT; in omap8250_probe()
1490 up.port.fifosize = 64; in omap8250_probe()
1492 if (!up.port.uartclk) { in omap8250_probe()
1495 clk = devm_clk_get(&pdev->dev, NULL); in omap8250_probe()
1497 if (PTR_ERR(clk) == -EPROBE_DEFER) in omap8250_probe()
1498 return -EPROBE_DEFER; in omap8250_probe()
1500 up.port.uartclk = clk_get_rate(clk); in omap8250_probe()
1504 if (of_property_read_u32(np, "overrun-throttle-ms", in omap8250_probe()
1505 &up.overrun_backoff_time_ms) != 0) in omap8250_probe()
1506 up.overrun_backoff_time_ms = 0; in omap8250_probe()
1508 pdata = of_device_get_match_data(&pdev->dev); in omap8250_probe()
1510 priv->habit |= pdata->habit; in omap8250_probe()
1512 if (!up.port.uartclk) { in omap8250_probe()
1513 up.port.uartclk = DEFAULT_CLK_SPEED; in omap8250_probe()
1514 dev_warn(&pdev->dev, in omap8250_probe()
1519 priv->membase = membase; in omap8250_probe()
1520 priv->line = -ENODEV; in omap8250_probe()
1521 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; in omap8250_probe()
1522 priv->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; in omap8250_probe()
1523 cpu_latency_qos_add_request(&priv->pm_qos_request, priv->latency); in omap8250_probe()
1524 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work); in omap8250_probe()
1526 spin_lock_init(&priv->rx_dma_lock); in omap8250_probe()
1530 device_set_wakeup_capable(&pdev->dev, true); in omap8250_probe()
1531 if (of_property_read_bool(np, "wakeup-source")) in omap8250_probe()
1532 device_set_wakeup_enable(&pdev->dev, true); in omap8250_probe()
1534 pm_runtime_enable(&pdev->dev); in omap8250_probe()
1535 pm_runtime_use_autosuspend(&pdev->dev); in omap8250_probe()
1539 * enabled by the user via sysfs. This is the historic way to in omap8250_probe()
1540 * prevent an unsafe default policy with lossy characters on wake-up. in omap8250_probe()
1544 if (!of_get_available_child_count(pdev->dev.of_node)) in omap8250_probe()
1545 pm_runtime_set_autosuspend_delay(&pdev->dev, -1); in omap8250_probe()
1547 pm_runtime_get_sync(&pdev->dev); in omap8250_probe()
1549 omap_serial_fill_features_erratas(&up, priv); in omap8250_probe()
1550 up.port.handle_irq = omap8250_no_handle_irq; in omap8250_probe()
1551 priv->rx_trigger = RX_TRIGGER; in omap8250_probe()
1552 priv->tx_trigger = TX_TRIGGER; in omap8250_probe()
1556 * we will fall back to a generic DMA channel which does not in omap8250_probe()
1557 * really work here. To ensure that we do not get a generic DMA in omap8250_probe()
1559 * To avoid "failed to request DMA" messages we check for DMA in omap8250_probe()
1562 ret = of_property_count_strings(np, "dma-names"); in omap8250_probe()
1565 struct uart_8250_dma *dma = &priv->omap8250_dma; in omap8250_probe()
1567 dma->fn = the_no_dma_filter_fn; in omap8250_probe()
1568 dma->tx_dma = omap_8250_tx_dma; in omap8250_probe()
1569 dma->rx_dma = omap_8250_rx_dma; in omap8250_probe()
1571 dma_params = pdata->dma_params; in omap8250_probe()
1574 dma->rx_size = dma_params->rx_size; in omap8250_probe()
1575 dma->rxconf.src_maxburst = dma_params->rx_trigger; in omap8250_probe()
1576 dma->txconf.dst_maxburst = dma_params->tx_trigger; in omap8250_probe()
1577 priv->rx_trigger = dma_params->rx_trigger; in omap8250_probe()
1578 priv->tx_trigger = dma_params->tx_trigger; in omap8250_probe()
1580 dma->rx_size = RX_TRIGGER; in omap8250_probe()
1581 dma->rxconf.src_maxburst = RX_TRIGGER; in omap8250_probe()
1582 dma->txconf.dst_maxburst = TX_TRIGGER; in omap8250_probe()
1587 irq_set_status_flags(up.port.irq, IRQ_NOAUTOEN); in omap8250_probe()
1588 ret = devm_request_irq(&pdev->dev, up.port.irq, omap8250_irq, 0, in omap8250_probe()
1589 dev_name(&pdev->dev), priv); in omap8250_probe()
1593 priv->wakeirq = irq_of_parse_and_map(np, 1); in omap8250_probe()
1595 ret = serial8250_register_8250_port(&up); in omap8250_probe()
1597 dev_err(&pdev->dev, "unable to register 8250 port\n"); in omap8250_probe()
1600 priv->line = ret; in omap8250_probe()
1601 pm_runtime_mark_last_busy(&pdev->dev); in omap8250_probe()
1602 pm_runtime_put_autosuspend(&pdev->dev); in omap8250_probe()
1605 pm_runtime_dont_use_autosuspend(&pdev->dev); in omap8250_probe()
1606 pm_runtime_put_sync(&pdev->dev); in omap8250_probe()
1607 flush_work(&priv->qos_work); in omap8250_probe()
1608 pm_runtime_disable(&pdev->dev); in omap8250_probe()
1609 cpu_latency_qos_remove_request(&priv->pm_qos_request); in omap8250_probe()
1616 struct uart_8250_port *up; in omap8250_remove() local
1619 err = pm_runtime_resume_and_get(&pdev->dev); in omap8250_remove()
1621 dev_err(&pdev->dev, "Failed to resume hardware\n"); in omap8250_remove()
1623 up = serial8250_get_port(priv->line); in omap8250_remove()
1624 omap_8250_shutdown(&up->port); in omap8250_remove()
1625 serial8250_unregister_port(priv->line); in omap8250_remove()
1626 priv->line = -ENODEV; in omap8250_remove()
1627 pm_runtime_dont_use_autosuspend(&pdev->dev); in omap8250_remove()
1628 pm_runtime_put_sync(&pdev->dev); in omap8250_remove()
1629 flush_work(&priv->qos_work); in omap8250_remove()
1630 pm_runtime_disable(&pdev->dev); in omap8250_remove()
1631 cpu_latency_qos_remove_request(&priv->pm_qos_request); in omap8250_remove()
1632 device_set_wakeup_capable(&pdev->dev, false); in omap8250_remove()
1641 priv->is_suspending = true; in omap8250_prepare()
1651 priv->is_suspending = false; in omap8250_complete()
1657 struct uart_8250_port *up = serial8250_get_port(priv->line); in omap8250_suspend() local
1660 serial8250_suspend_port(priv->line); in omap8250_suspend()
1666 priv->wer = 0; in omap8250_suspend()
1667 serial_out(up, UART_OMAP_WER, priv->wer); in omap8250_suspend()
1668 if (uart_console(&up->port) && console_suspend_enabled) in omap8250_suspend()
1670 flush_work(&priv->qos_work); in omap8250_suspend()
1678 struct uart_8250_port *up = serial8250_get_port(priv->line); in omap8250_resume() local
1681 if (uart_console(&up->port) && console_suspend_enabled) { in omap8250_resume()
1687 serial8250_resume_port(priv->line); in omap8250_resume()
1695 static int omap8250_lost_context(struct uart_8250_port *up) in omap8250_lost_context() argument
1699 val = serial_in(up, UART_OMAP_SCR); in omap8250_lost_context()
1701 * If we lose context, then SCR is set to its reset value of zero. in omap8250_lost_context()
1702 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1, in omap8250_lost_context()
1703 * among other bits, to never set the register back to zero again. in omap8250_lost_context()
1712 writel(val, priv->membase + (reg << OMAP_UART_REGSHIFT)); in uart_write()
1728 * and we restore it on resume so this is safe to do on all SoCs in omap8250_soft_reset()
1746 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE)); in omap8250_soft_reset()
1750 return -ETIMEDOUT; in omap8250_soft_reset()
1759 struct uart_8250_port *up = NULL; in omap8250_runtime_suspend() local
1761 if (priv->line >= 0) in omap8250_runtime_suspend()
1762 up = serial8250_get_port(priv->line); in omap8250_runtime_suspend()
1764 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) { in omap8250_runtime_suspend()
1771 if (up) { in omap8250_runtime_suspend()
1772 /* Restore to UART mode after reset (for wakeup) */ in omap8250_runtime_suspend()
1773 omap8250_update_mdr1(up, priv); in omap8250_runtime_suspend()
1775 serial_out(up, UART_OMAP_WER, priv->wer); in omap8250_runtime_suspend()
1779 if (up && up->dma && up->dma->rxchan) in omap8250_runtime_suspend()
1780 omap_8250_rx_dma_flush(up); in omap8250_runtime_suspend()
1782 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; in omap8250_runtime_suspend()
1783 schedule_work(&priv->qos_work); in omap8250_runtime_suspend()
1784 atomic_set(&priv->active, 0); in omap8250_runtime_suspend()
1792 struct uart_8250_port *up = NULL; in omap8250_runtime_resume() local
1794 /* Did the hardware wake to a device IO interrupt before a wakeirq? */ in omap8250_runtime_resume()
1795 if (atomic_read(&priv->active)) in omap8250_runtime_resume()
1798 if (priv->line >= 0) in omap8250_runtime_resume()
1799 up = serial8250_get_port(priv->line); in omap8250_runtime_resume()
1801 if (up && omap8250_lost_context(up)) { in omap8250_runtime_resume()
1802 uart_port_lock_irq(&up->port); in omap8250_runtime_resume()
1803 omap8250_restore_regs(up); in omap8250_runtime_resume()
1804 uart_port_unlock_irq(&up->port); in omap8250_runtime_resume()
1807 if (up && up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2)) { in omap8250_runtime_resume()
1808 uart_port_lock_irq(&up->port); in omap8250_runtime_resume()
1809 omap_8250_rx_dma(up); in omap8250_runtime_resume()
1810 uart_port_unlock_irq(&up->port); in omap8250_runtime_resume()
1813 atomic_set(&priv->active, 1); in omap8250_runtime_resume()
1814 priv->latency = priv->calc_latency; in omap8250_runtime_resume()
1815 schedule_work(&priv->qos_work); in omap8250_runtime_resume()
1838 idx = *omap_str - '0'; in omap8250_console_fixup()