15 #include <linux/mtd/physmap.h>
36 	.name		= "physmap-flash",
47 	return ssb_read32(mcore->dev, offset);  in mips_read32()
54 	ssb_write32(mcore->dev, offset, value);  in mips_write32()
85 	struct ssb_bus *bus = rdev->bus;  in find_device()
87 	for (i = 0; i < bus->nr_devices; i++) {  in find_device()
89 		dev = &(bus->devices[i]);  in find_device()
103 	struct ssb_bus *bus = dev->bus;  in ssb_mips_irq()
104 	struct ssb_device *mdev = bus->mipscore.dev;  in ssb_mips_irq()
113 	ipsflag = ssb_read32(bus->mipscore.dev, SSB_IPSFLAG);  in ssb_mips_irq()
129 	struct ssb_device *dev = bus->mipscore.dev;  in clear_irq()
144 	struct ssb_bus *bus = dev->bus;  in set_irq()
145 	struct ssb_device *mdev = bus->mipscore.dev;  in set_irq()
150 	dev->irq = irq + 2;  in set_irq()
173 	dev_dbg(dev->dev, "set_irq: core 0x%04x, irq %d => %d\n",  in set_irq()
174 		dev->id.coreid, oldirq+2, irq+2);  in set_irq()
180 	dev_dbg(dev->dev,  in print_irq()
182 		dev->id.coreid,  in print_irq()
195 	for (i = 0; i < bus->nr_devices; i++) {  in dump_irq()
197 		dev = &(bus->devices[i]);  in dump_irq()
204 	struct ssb_bus *bus = mcore->dev->bus;  in ssb_mips_serial_init()
206 	if (ssb_extif_available(&bus->extif))  in ssb_mips_serial_init()
207 		mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);  in ssb_mips_serial_init()
208 	else if (ssb_chipco_available(&bus->chipco))  in ssb_mips_serial_init()
209 		mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);  in ssb_mips_serial_init()
211 		mcore->nr_serial_ports = 0;  in ssb_mips_serial_init()
216 	struct ssb_bus *bus = mcore->dev->bus;  in ssb_mips_flash_detect()
217 	struct ssb_sflash *sflash = &mcore->sflash;  in ssb_mips_flash_detect()
218 	struct ssb_pflash *pflash = &mcore->pflash;  in ssb_mips_flash_detect()
220 	/* When there is no chipcommon on the bus there is 4MB flash */  in ssb_mips_flash_detect()
221 	if (!ssb_chipco_available(&bus->chipco)) {  in ssb_mips_flash_detect()
222 		pflash->present = true;  in ssb_mips_flash_detect()
223 		pflash->buswidth = 2;  in ssb_mips_flash_detect()
224 		pflash->window = SSB_FLASH1;  in ssb_mips_flash_detect()
225 		pflash->window_size = SSB_FLASH1_SZ;  in ssb_mips_flash_detect()
229 	/* There is ChipCommon, so use it to read info about flash */  in ssb_mips_flash_detect()
230 	switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {  in ssb_mips_flash_detect()
233 		dev_dbg(mcore->dev->dev, "Found serial flash\n");  in ssb_mips_flash_detect()
234 		ssb_sflash_init(&bus->chipco);  in ssb_mips_flash_detect()
237 		dev_dbg(mcore->dev->dev, "Found parallel flash\n");  in ssb_mips_flash_detect()
238 		pflash->present = true;  in ssb_mips_flash_detect()
239 		pflash->window = SSB_FLASH2;  in ssb_mips_flash_detect()
240 		pflash->window_size = SSB_FLASH2_SZ;  in ssb_mips_flash_detect()
241 		if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)  in ssb_mips_flash_detect()
243 			pflash->buswidth = 1;  in ssb_mips_flash_detect()
245 			pflash->buswidth = 2;  in ssb_mips_flash_detect()
250 	if (sflash->present) {  in ssb_mips_flash_detect()
252 		bcm47xx_nvram_init_from_mem(sflash->window, sflash->size);  in ssb_mips_flash_detect()
254 	} else if (pflash->present) {  in ssb_mips_flash_detect()
256 		bcm47xx_nvram_init_from_mem(pflash->window, pflash->window_size);  in ssb_mips_flash_detect()
259 		ssb_pflash_data.width = pflash->buswidth;  in ssb_mips_flash_detect()
260 		ssb_pflash_resource.start = pflash->window;  in ssb_mips_flash_detect()
261 		ssb_pflash_resource.end = pflash->window + pflash->window_size;  in ssb_mips_flash_detect()
267 	struct ssb_bus *bus = mcore->dev->bus;  in ssb_cpu_clock()
270 	if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)  in ssb_cpu_clock()
271 		return ssb_pmu_get_cpu_clock(&bus->chipco);  in ssb_cpu_clock()
273 	if (ssb_extif_available(&bus->extif)) {  in ssb_cpu_clock()
274 		ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);  in ssb_cpu_clock()
275 	} else if (ssb_chipco_available(&bus->chipco)) {  in ssb_cpu_clock()
276 		ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);  in ssb_cpu_clock()
280 	if ((pll_type == SSB_PLLTYPE_5) || (bus->chip_id == 0x5365)) {  in ssb_cpu_clock()
300 	if (!mcore->dev)  in ssb_mipscore_init()
303 	dev_dbg(mcore->dev->dev, "Initializing MIPS core...\n");  in ssb_mipscore_init()
305 	bus = mcore->dev->bus;  in ssb_mipscore_init()
311 	if (ssb_extif_available(&bus->extif))  in ssb_mipscore_init()
312 		ssb_extif_timing_init(&bus->extif, ns);  in ssb_mipscore_init()
313 	else if (ssb_chipco_available(&bus->chipco))  in ssb_mipscore_init()
314 		ssb_chipco_timing_init(&bus->chipco, ns);  in ssb_mipscore_init()
317 	for (irq = 2, i = 0; i < bus->nr_devices; i++) {  in ssb_mipscore_init()
319 		dev = &(bus->devices[i]);  in ssb_mipscore_init()
322 			dev->irq = 0;  in ssb_mipscore_init()
324 			dev->irq = mips_irq + 2;  in ssb_mipscore_init()
325 		if (dev->irq > 5)  in ssb_mipscore_init()
327 		switch (dev->id.coreid) {  in ssb_mipscore_init()
329 			/* shouldn't need a separate irq line for non-4710, most of them have a proper  in ssb_mipscore_init()
331 			if ((bus->chip_id == 0x4710) && (irq <= 4)) {  in ssb_mipscore_init()
351 	dev_dbg(mcore->dev->dev, "after irq reconfiguration\n");  in ssb_mipscore_init()