106 				ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);  in ssb_chipco_set_clockmode()
130 			if (tmp & 0x10)  in chipco_pctl_get_slowclksrc()
137 		tmp &= 0x7;  in chipco_pctl_get_slowclksrc()
138 		if (tmp == 0)  in chipco_pctl_get_slowclksrc()
215 	if (bus->chip_id == 0x4321) {  in chipco_powercontrol_init()
216 		if (bus->chip_rev == 0)  in chipco_powercontrol_init()
217 			chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0x3A4);  in chipco_powercontrol_init()
219 			chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0xA4);  in chipco_powercontrol_init()
229 				0x0000FFFF) | 0x00040000);  in chipco_powercontrol_init()
247 	case 0x4312:  in pmu_fast_powerup_delay()
248 	case 0x4322:  in pmu_fast_powerup_delay()
249 	case 0x4328:  in pmu_fast_powerup_delay()
251 	case 0x4325:  in pmu_fast_powerup_delay()
277 	minfreq = chipco_pctl_clockfreqlimit(cc, 0);  in calc_fast_powerup_delay()
280 	WARN_ON(tmp & ~0xFFFF);  in calc_fast_powerup_delay()
306 		return 0xffffffff;  in ssb_chipco_watchdog_get_max_timer()
316 		return 0;  in ssb_chipco_watchdog_timer_set_wdt()
327 		return 0;  in ssb_chipco_watchdog_timer_set_ms()
357 	dev_dbg(cc->dev->dev, "chipcommon status is 0x%x\n", cc->status);  in ssb_chipcommon_init()
360 		chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);  in ssb_chipcommon_init()
361 		chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0);  in ssb_chipcommon_init()
424 		if (cc->dev->bus->chip_id != 0x5365) {  in ssb_chipco_get_clockcontrol()
442 	chipco_write32(cc, SSB_CHIPCO_PROG_CFG, 0x11);  in ssb_chipco_timing_init()
445 	tmp |= DIV_ROUND_UP(240, ns);				/* Waitcount-0 = 240ns */  in ssb_chipco_timing_init()
446 	chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp);	/* 0x01020a0c for a 100Mhz clock */  in ssb_chipco_timing_init()
451 	tmp |= DIV_ROUND_UP(120, ns);				/* Waitcount-0 = 120nS */  in ssb_chipco_timing_init()
452 	if ((bus->chip_id == 0x5365) ||  in ssb_chipco_timing_init()
455 	if ((bus->chip_id == 0x5365) ||  in ssb_chipco_timing_init()
457 	    ((bus->chip_id == 0x5350) && (bus->chip_rev == 0)))  in ssb_chipco_timing_init()
460 	if (bus->chip_id == 0x5350) {  in ssb_chipco_timing_init()
465 		tmp |= DIV_ROUND_UP(120, ns);			  /* Waitcount-0 = 120ns */  in ssb_chipco_timing_init()
466 		chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */  in ssb_chipco_timing_init()
512 	u32 res = 0;  in ssb_chipco_gpio_out()
524 	u32 res = 0;  in ssb_chipco_gpio_outen()
536 	u32 res = 0;  in ssb_chipco_gpio_control()
549 	u32 res = 0;  in ssb_chipco_gpio_intmask()
561 	u32 res = 0;  in ssb_chipco_gpio_polarity()
573 	u32 res = 0;  in ssb_chipco_gpio_pullup()
576 		return 0xffffffff;  in ssb_chipco_gpio_pullup()
588 	u32 res = 0;  in ssb_chipco_gpio_pulldown()
591 		return 0xffffffff;  in ssb_chipco_gpio_pulldown()
605 	int nr_ports = 0;  in ssb_chipco_serial_init()
661 		if ((ccrev > 0) &&  in ssb_chipco_serial_init()
676 	for (i = 0; i < n; i++) {  in ssb_chipco_serial_init()
682 		/* Offset changed at after rev 0 */  in ssb_chipco_serial_init()
683 		if (ccrev == 0)  in ssb_chipco_serial_init()
692 		ports[i].reg_shift = 0;  in ssb_chipco_serial_init()