Lines Matching full:arbiter
22 /* PMIC Arbiter configuration registers */
35 /* PMIC Arbiter channel registers offsets */
91 * PMIC arbiter version 5 uses different register offsets for read/write vs
135 * struct spmi_pmic_arb_bus - SPMI PMIC Arbiter Bus object
137 * @pmic_arb: the SPMI PMIC Arbiter the bus belongs to.
140 * @cnfg: address of the PMIC Arbiter configuration registers.
178 * struct spmi_pmic_arb - SPMI PMIC Arbiter object
188 * @buses: per arbiter buses instances
261 * @pmic_arb: the SPMI PMIC arbiter
276 * @pmic_arb: the SPMI PMIC arbiter
1173 * In order to allow multiple EEs to write to a single PPID in arbiter in pmic_arb_read_apid_map_v5()
1180 * In arbiter version 7, the APID numbering space is divided between in pmic_arb_read_apid_map_v5()
1567 * For arbiter version 7, APID ownership table registers have independent
1835 dev_info(dev, "PMIC arbiter version %s (0x%x)\n", in spmi_pmic_arb_probe()
1892 MODULE_DESCRIPTION("Qualcomm MSM SPMI Controller (PMIC Arbiter) driver");