69 #define SPI_CS_SETUP_HOLD(reg, cs, val)			\  argument
82 #define SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(reg, cs, val)		\  argument
85 #define SPI_SET_CYCLES_BETWEEN_PACKETS(reg, cs, val)		\  argument
92 #define SPI_BLK_CNT(val)			(((val) >> 0) & 0xFFFF)  argument
93 #define SPI_SLV_IDLE_COUNT(val)			(((val) >> 16) & 0xFF)  argument
108 #define SPI_TX_FIFO_EMPTY_COUNT(val)		(((val) >> 16) & 0x7F)  argument
109 #define SPI_RX_FIFO_FULL_COUNT(val)		(((val) >> 23) & 0x7F)  argument
233 		u32 val, unsigned long reg)  in tegra_spi_writel()
244 	u32 val;  in tegra_spi_clear_status()  local
259 	struct spi_transfer *t)  in tegra_spi_calculate_curr_xfer_param()
292 	struct tegra_spi_data *tspi, struct spi_transfer *t)  in tegra_spi_fill_tx_fifo_from_client_txbuf()
344 		struct tegra_spi_data *tspi, struct spi_transfer *t)  in tegra_spi_read_rx_fifo_to_client_rxbuf()
388 		struct tegra_spi_data *tspi, struct spi_transfer *t)  in tegra_spi_copy_client_txbuf_to_spi_txbuf()
427 		struct tegra_spi_data *tspi, struct spi_transfer *t)  in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
535 		struct tegra_spi_data *tspi, struct spi_transfer *t)  in tegra_spi_start_dma_based_transfer()
537 	u32 val;  in tegra_spi_start_dma_based_transfer()  local
629 		struct tegra_spi_data *tspi, struct spi_transfer *t)  in tegra_spi_start_cpu_based_transfer()
631 	u32 val;  in tegra_spi_start_cpu_based_transfer()  local
771 					struct spi_transfer *t,  in tegra_spi_setup_transfer_one()
866 		struct spi_transfer *t, u32 command1)  in tegra_spi_start_transfer_one()
947 	u32 val;  in tegra_spi_setup()  local
1121 	struct spi_transfer *t = tspi->curr_xfer;  in handle_cpu_based_xfer()  local
1162 	struct spi_transfer *t = tspi->curr_xfer;  in handle_dma_based_xfer()  local